JPH02214164A - Mosfet with input protection circuit - Google Patents

Abstract

PURPOSE:To keep gate voltage to be constantly lower than gate oxide film breakdown voltage for preventing gate breakdown by forming emitter/collector and diode of a horizontal type transistor at a demarcated region of epitaxial layer as a gate voltage limiting diode. CONSTITUTION:An n<-> type epitaxial layer 10 is set to the demarcated region by a p<+> type isolation 3 and a p<+> type emitter region 11 produced by excluding the base region diffusion process of a horizontal PNP transistor as well as a p<+> type collector region 12 surrounding it are formed within the demarcated region 10. Then, both regions 11 and 12 operate as the cathode and anode regions of each gate voltage limiting diode. Thus, since the base-open horizontal type PNP transistor is formed within the n<-> type epitaxial layer 10 as a voltage limiting diode, the collector/emitter withstand voltage is lower than the gate oxide film breakdown voltage. Thus, it is possible to keep gate voltage to be constantly lower than the breakdown voltage, thus preventing gate breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOSFET that includes an insulated gate field effect transistor and an input protection circuit to prevent the gate from being destroyed in a l-chip.

[Conventional technology]

Conventionally, the circuit configuration of a MOSFET equipped with this type of manual protection circuit is as shown in FIG. It consists of a current limiting resistor R and a gate voltage limiting diode D whose cand is connected to the gate electrode G and whose anode is grounded. In a circuit with such a configuration, when a surge voltage greater than the gate oxide film breakdown voltage Vll+ of the insulated gate field effect transistor M is applied to the input electrode IN, the gate voltage becomes equal to the breakdown voltage VI.
This is suppressed by the breakdown of the gate voltage limiting diode D, which has a breakdown voltage (vo) lower than G, thereby preventing breakdown of the gate oxide. Current limiting resistance is gate voltage limiting diode D
This is to limit the current at the time of breakdown and prevent junction breakdown.

The semiconductor structure of the gate voltage limiting diode D described above is the structure shown in FIGS. It is created in the defined area 4 obtained by separation using Ration 3. Reference numeral 5 denotes a p- type diffusion layer in contact with the n+ type buried layer 2, and within this p- type diffusion layer 5, an n+ region cathode region 6 and a p+ region anode region 7 surrounding it are formed. Cathode region 6 connected to cathode region 6
a is connected to the gate electrode of an insulated gate effect transistor (not shown) built in another defined region, and an anode electrode 7a connected to the anode region 7 is grounded.

Further, an n+ type diffusion region 8 surrounding the p− type diffusion layer 5 is formed in the n− type epitaxial layer of the definition region 4, and a power supply electrode 8a is connected to this. The pn junction of the gate voltage limiting diode D is a junction between the p- type diffusion layer 5 and the cathode region 6, and its breakdown voltage Van is, for example, p- impurity concentration 2xlO''/cj, n+ impurity concentration lXl0''/ V++o::25V when cst
It is.

[Problem to be solved by the invention]

As devices become smaller and faster, the thickness of the gate oxide film of the insulated gate field effect transistor M tends to become thinner. As the thickness of the gate oxide film becomes thinner, its breakdown voltage VIG decreases. For example, if the film thickness is 1000 people, Via: 100V, and if the film thickness is 250 people, It V ma :
It is 25V.

By the way, the breakdown voltage v0 of the gate voltage limiting diode D is about 25V, which is equal to the breakdown voltage VIG of an insulated gate field effect transistor with a film thickness of 250 mm, so when a surge voltage is applied to the manual electrode IN, the gate voltage increases to breakdown voltage VIIG, causing gate breakdown.

Therefore, it is necessary to lower the breakdown voltage of the gate voltage limiting diode D, and the method for doing so is as follows.
Possible methods include changing the impurity concentration of p-type diffusion layer 5 or cathode region 6, and narrowing the distance between cathode region 6 and anode region 7. However, changing the impurity concentration affects the device characteristics of the insulated gate field effect transistor itself, or necessitates the addition of a new diffusion process and mask. Further, narrowing the distance between the cathode region 6 and the anode region 7 causes problems of reliability and variation in breakdown voltage due to mask misalignment and the like.

Therefore, the feature d of the present invention is that by adopting a gate voltage limiting diode with a modified structure, the device characteristics of the insulated gate field effect transistor are not affected, and no new process is added, and the breakdown voltage can be reduced. M with input protection circuit with low breakdown voltage gate voltage limiting diode while maintaining reliability.
Our goal is to provide OSFETs.

[Means to solve the problem]

In order to solve the above problems, the measures taken by the present invention are as follows:
Rather than forming the cathode region and anode region in the p-type diffusion layer, the emitter/collector diode of the lateral transistor formed in the epitaxial layer without the p-type diffusion layer is used as the gate voltage limiting diode. be.

[Effect]

According to this method, a gate voltage limiting diode having a cathode region and an anode region of the opposite conductivity type is formed in the epitaxial layer of the second conductivity type with a relatively low impurity concentration, so that the breakdown voltage can be reduced. For example 2
It can be set to 5V or less, and breakdown can occur before the gate is destroyed.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a plan view of a semiconductor structure according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. Note that the same parts in FIGS. 1 and 2 as those shown in FIGS. 5 and 6 are given the same reference numerals.

An n − type epitaxial layer 10 is formed on a p type substrate l with an n + type buried layer 2 interposed therebetween. The n-type epitaxial layer 10 is defined by a p+-type isolation 3. In this definition area 10, there is a horizontal PN.
P) The p1 type emitter region 11 and the surrounding p” formed without the transistor base region diffusion process
A collector region 12 of the mold is formed. Both areas 11.
The formation of 12 is performed simultaneously with the manufacturing process of an insulated gate field effect transistor (not shown). Emitter area 1
1 is connected to the gate electrode of an insulated gate field effect transistor (not shown) formed in another defined region via an emitter electrode 11a (see FIG. 3), and is connected to the cathode region of a gate voltage limiting diode. It acts as.

Further, the collector region 12 is grounded via a collector electrode 12a (see FIG. 3), and acts as an anode region of a gate voltage limiting diode. Note that 13 is a silicon oxide film, and 14 is LOCO3. In the case of this embodiment, the impurity concentration of the n-type epitaxial layer 10 is 1.5xlOts, the impurity concentration of the emitter region 11 and the collector region 12 is 5.0xIO'', and the collector-emitter breakdown voltage of the base open is BVcto:IO
It is V.

Figure 3 is a circuit configuration diagram of this embodiment, where p is a horizontal PNP with an open base that functions as a gate voltage limiting diode.
) shows a transistor, the emitter E is connected to the gate electrode G, and the collector C is grounded.

In this way, as a voltage limiting diode, a lateral PNP transistor p with an open base is connected to an n-type epitaxial layer l.
Since it is formed in O, its collector-emitter breakdown voltage BVC! ◎ is smaller than the gate oxide film breakdown voltage VIO. Therefore, the gate voltage can always be kept lower than the breakdown voltage v0, and gate breakdown can be prevented.

In addition, since the lateral PNP transistor p is used as a gate voltage limiting diode, the p+ type emitter region 11
Since the formation of the collector region 12 and the collector region 12 are performed simultaneously with the manufacturing process of the insulated gate field effect transistor, the device characteristics are not affected and there is no need to add new processes or masks.
Further, there is no need to make the distance between the emitter region 11 and the collector region 12 particularly narrow. Furthermore, since the entire area of the defined region 10 of the n-type epitaxial layer can be used without forming the conventional p-type diffusion layer 5 (see FIG. 6), Multiple lateral PNP transistors or gate voltage limiting diodes can be formed. Therefore, it is possible to reduce the chip area or achieve high-density integration.

〔Effect of the invention〕

As explained above, the MOSFET equipped with the input protection circuit according to the present invention serves as the gate voltage limiting diode of the human power protection circuit, and the emitter/collector of the horizontal transistor.
Since the diode is formed in the defined region of the epitaxial layer, the following effects are achieved.

■Since a gate voltage limiting diode with a lower breakdown voltage than conventional ones has been realized, the gate voltage can always be kept lower than the gate oxide film breakdown voltage, effectively preventing gate breakdown due to thinning of the gate oxide film. can be prevented.

■It is possible to create a gate voltage limiting diode at the same time as the insulated gate field effect transistor formation process, so the characteristics of the insulated gate field effect transistor itself are not impaired, and additional processes and masks are not required. Furthermore, there is no need to make the interval between the emitter region and the collector region particularly narrow or fine.

(2) Furthermore, since the entire defined area of the epitaxial layer can be used to create a lateral transistor, a plurality of gate voltage limiting diodes can be formed within the same defined area, which has the advantage of reducing the chip area or increasing the density of integration.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1. FIG. 3 is a circuit diagram of the same embodiment. FIG. 4 is a circuit configuration diagram showing an example of a MOSFET equipped with a conventional input protection circuit. FIG. 5 is a plan view showing the semiconductor structure of the conventional example. FIG. 6 is a cross-sectional view taken along the line Vl--Vl in FIG. 5. lp type substrate, 2n+ type buried layer, 3 isolation, 1 On- type epitaxial layer definition region, llp+
type emitter region (cathode region of gate voltage limiting diode), 11a emitter electrode, 12.p+ type collector region (anode region of gate voltage limiting diode), 12a collector electrode, p horizontal open base PN'P) transistor ( gate voltage limiting diode),
M-MOS FET, R diagram

Claims (1)

[Scope of Claims] 1) A defined region in which a second conductivity type epitaxial layer formed on a first conductivity type substrate with a second conductivity type buried layer sandwiched therebetween is separated and defined by isolation; An insulated gate field effect transistor formed in a defined region, a gate voltage limiting diode formed in another defined region, and a connection between an input electrode and a gate electrode of the insulated gate field effect transistor. A MOSFET equipped with an input protection circuit including a current limiting resistor, wherein the gate voltage limiting diode is an emitter/collector diode of a lateral transistor.