JPH03178160A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To eliminate the possibility of troubles like junction breakdown and improve reliability, by diffusing impurities for a well, from the surface of a semiconductor region composed of a substrate and the like, impurities of which have the same conductivity type as the semiconductor region and concentration higher than it, and making the diffusion patterns intersect at least one side offset diffusion layer, under a gate. CONSTITUTION:The diffusion pattern of a well 3a is made to intersect at least one side offset diffusion layer 6, under a gate 7. As the result, the peripheral part of the offset diffusion layer forms a junction with the well of opposite conductivity type, under the gate 7. However said peripheral part forms a junction with the semiconductor region of the same conductivity type as the well, in the other part on the periphery where the junction breakdown has likely occurred in the conventional devices. Although the offset diffusion layer 6 intersecting the diffusion pattern of the well 3a forms junctions with the well 3a and the semiconductor region, the impurity concentration of the well 3a is higher than that of the semiconductor region, so that the breakdown voltage of the junction between the layer 6 and the well is surely lower than the breakdown voltage between the layer 6 and the semiconductor region. Thereby the possibility of junction breakdown can be eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a MOS or MIS type field effect transistor that requires a high breakdown voltage and is suitable for being incorporated into an integrated circuit device together with a normal low voltage field effect transistor. Regarding.

[Conventional technology]

As the scope of application of integrated circuit devices has expanded significantly, not only is the circuit highly integrated, but also the ability to directly drive an external load operating under a predetermined power supply voltage is often required. In such an integrated circuit device, a highly integrated logic circuit section that operates at high speed under a voltage as low as about 5 volts and an output circuit section that includes a high-voltage transistor that can operate under a voltage of several tens of volts are housed on the same chip. It is necessary to incorporate
It is advantageous in terms of manufacturing to incorporate these two circuit parts using a wafer process that is as common as possible.As is well known, it is advantageous to use CMOS IJt for high integration of logic circuit parts. A field effect transistor with a so-called offset gate structure is often employed as a high voltage transistor that can be easily used in a process.

By the way, in order to incorporate a high voltage field effect transistor for an output circuit, it is necessary to appropriately select the impurity concentration of the channel forming region, but it is usually necessary to select the impurity concentration of the channel formation region appropriately, but it is usually necessary to select a low voltage field effect transistor that is highly integrated with a design rule of about 2 microns. On the logic circuit side, a so-called twin well structure is often adopted in which a dedicated well is provided for both the n-channel and p-channel field effect transistors, so on the output circuit side, the substrate is used as the channel formation region of the high voltage field effect transistor. In addition to this, such twin wells or wells capable of simultaneous diffusion are also used.

FIG. 3 shows a conventional example in which a high breakdown voltage field effect transistor is incorporated using such a twin well and a well diffused simultaneously. Figure (a) shows the low voltage n on the logic circuit side.
and p-channel field effect transistors tn and tp
and (b) are cross-sectional views of the high-voltage n-channel field-effect transistor Tn on the output circuit side, and a top view of the diffusion patterns of the main semiconductor layers for the high-voltage n-channel field-effect transistor Tn. There is.

In the example shown in FIG. 3, a p-type substrate or an epitaxial layer grown on it is used as a semiconductor region l as a base for fabricating an integrated circuit, and on the low voltage side, a p-channel field effect transistor is formed from the surface of this semiconductor region l. N-type well 2 for tp and P well 2 for n-channel field effect transistor tn.
shaped well 3 is diffused as the above-mentioned twin well,
For the n-channel field effect transistor Tn on the high voltage side, the p-type well 3d is diffused at the same time as the low-voltage well 3 with an impurity concentration of about 5xlO'' atoms/d. 3d and n-type wells 2 are provided with channel stopper layers 4 and 5 for p-type and n-type, respectively, as usual.

For the high-voltage n-channel field effect transistor Tn, a pair of n-type offset diffusion layers 6 are provided in the p-type well 3d for the purpose of improving the source-drain breakdown voltage. ) are provided in the pattern shown in the figure. The impurity concentration of this offset diffusion layer 6 is usually selected to be relatively low, for example on the order of 5xlO'' atoms/c11.

Note that this pair of offset diffusion layers 6 and the above-mentioned channel stopper layers 4 and 5 are simultaneously thermally diffused after ion implantation of impurities for them, and field oxidation MlO is formed at the same time as this thermal diffusion.

The gate 7 of all the field effect transistors is formed by overlapping the gate oxide film 7a with the field oxide 1110 in this example, and is provided facing the surface of the well.
The periphery of the field oxide 110 is formed so as to overlap the field oxide l110. A pair of p-type and n-type source/drain layers 7 and 8 for the low-voltage field-effect transistor are formed using the gate 7 as a mask, and an n-type source layer 83 and drain layer 8d for the high-voltage field-effect transistor correspond to each other. The impurities are diffused into the offset diffusion layer 6 at a high impurity concentration. Thereafter, the entire surface is covered with the glabellar insulating film 11, and connections 11120 are provided in the windows opened at key points. In the figure (b), the source S, drain D, and gate G terminals of one field effect transistor are shown.

In the integrated circuit device having the above structure, the breakdown voltage between the source and drain is 10 to 10 for the low voltage side field effect transistors tn and tp.
Although it is about 20V, high voltage field effect transistor Tn
Since the depletion layer extends within the offset diffusion layer 6, the voltage is increased to, for example, 40 to 60V. Note that the offset diffusion layer 6
The depletion layer inside extends laterally between the central portion connected to the source layer 8S or drain layer 8d and the lower side of the junction with the well 3d, for example, the gate oxide WA7a. In order to give this field effect transistor Tn a desired high breakdown voltage value,
First, the impurity concentrations of the well 3d and the offset diffusion layer 6 are selected to the optimum values, and then the source layer 8S is selected accordingly.
Alternatively, it is desirable to select the lateral dimension from the drain layer 8d to the periphery of the offset diffusion layer 6.

[Problem to be solved by the invention]

However, in the above-mentioned high-voltage field effect transistor, when the impurity concentration of the offset diffusion layer 6 is lowered in order to improve the source-drain breakdown voltage, the well 3d
There is a problem that the bond between the two is becoming more likely to be permanently destroyed.

For example, the impurity concentration of the P-type well 3d is 5 x
Figure 3 (b
According to the results of an experiment conducted by the present inventor under the condition that the source terminal S of the transistor is grounded and an overvoltage is applied to the drain terminal, the impurity concentration of the n-type offset diffusion layer 6 is 5 x 1.
0'' atoms/cd or more, breakdown of the junction between the two occurs almost uniformly along the lower periphery of the gate oxide film 7a of the offset diffusion layer 6, which is indicated by X marks arranged vertically in the figure. , when the overvoltage disappears, the junction recovers to its original state, whereas if the impurity concentration is lower than the above value, the source-drain breakdown voltage itself increases; Breakdown is likely to occur at the electric field concentration area marked with an X, and in this case, the bond will be locally permanently destroyed.

In other words, if the impurity concentration of the offset diffusion 116 is relatively high, the breakdown will take the form of a so-called punch-through of the channel, but if the impurity concentration is too low, the weakest point of the junction with the well 3d will be damaged during overvoltage breakdown. It will be permanently destroyed.

Another problem with conventional high voltage field effect transistors is that when the impurity concentration of the offset diffusion layer 6 is lowered, abnormal current tends to flow between the source and drain due to the parasitic transistor effect when voltage is applied to the gate 7. It is what happens.

The parasitic transistors related to this are the n-type drain layer 8d and the offset diffusion layer 6 on the right side in FIG. 3(a).
．． P-type well 3d and semiconductor region 1. It is an npn type bipolar transistor formed between the n type source layer 8s and the left offset diffusion N6, and the well 3d, which is the base thereof, is considered to be influenced by the potential of the gate 7. FIG. 3(C) shows the voltage of the field effect transistor Tn when the impurity concentration of the offset diffusion layer 6 is lowered.
Current characteristics. The horizontal axis is the voltage Vd applied to the drain when the source is grounded, and the vertical axis is the current flowing through the transistor.
As shown in the figure, the breakdown voltage is high when the gate voltage Vg is 0, but the characteristic parameter is the gate voltage Vg.
It decreases as the gate voltage is increased and reaches a minimum value at a certain gate voltage.

If the parasitic transistor becomes conductive in this way and a large current flows, there is a risk that the junction between the drain layer 8d and the well 3d will be destroyed, and even if the impurity concentration of the offset diffusion layer 6 is lowered, the breakdown voltage value The improvement effect of this will be diminished.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems, eliminate the possibility of troubles such as junction breakdown in a field effect transistor provided with an offset diffusion layer, and improve its reliability.

[Means to solve the problem]

The present invention provides a field effect transistor that includes, in addition to a well, a gate, and a pair of source/drain layers as described above, a pair of offset diffusion layers surrounding each source/drain layer and having a lower impurity concentration. Then, by diffusing the well from the surface of a semiconductor region made of a substrate or the like with an impurity of the same conductivity type and higher concentration than that of the well, and intersecting the diffusion pattern with at least one of the offset diffusion layers under the gate, the above-described method is achieved. The goal is to achieve the following objectives.

However, as usual, the gate is placed on a part of the surface of the well so as to face each other with a thin gate oxide film interposed therebetween, and the source/drain layer is diffused with the opposite conductivity type from the well, with the gate in between. In addition, each offset diffusion layer is diffused with a conductivity type opposite to that of the well so that a part of its periphery goes under the periphery of the gate oxide film, and a pair of offset diffusion layers under the gate oxide film of the well are diffused. A channel shall be formed on the surface between the peripheral edges of.

[Effect]

As can be seen from the explanation of the prior art described above, in the past, a pair of offset diffusion layers of the opposite conductivity type were built inside the well, but in the present invention, as mentioned above, the diffusion layer of the well is By intersecting the pattern with at least one of the offset diffusion layers below the gate,
Below the gate, the periphery of the offset diffusion layer is bonded to a well of the opposite conductivity type, but at other locations in the periphery where junction breakdown has hitherto been apt to occur, it is bonded to a semiconductor region of the same conductivity type as the well.

Therefore, the offset diffusion layer that intersects with the diffusion pattern of the well will be in contact with the well and the semiconductor region, but in the present invention, as in the above structure, the impurity concentration in the well is higher than that in the semiconductor region, so the offset diffusion layer The breakdown voltage of the junction with the well is always lower than the breakdown voltage of the junction with the semiconductor region.

Therefore, in the field effect transistor according to the present invention, breakdown at the periphery of the offset diffusion layer when an overvoltage is applied always occurs at the junction with the well, and at the junction with the semiconductor region, that is, where junction breakdown has conventionally occurred. This will no longer occur, eliminating the risk of bond failure. Note that the breakdown of the junction between the offset diffusion layer and the well always occurs below the gate, so it occurs uniformly over the entire junction, just like punch-through in the normal channel region, and unless the overvoltage is extremely large, the breakdown will occur at the bottom of the gate. There is no risk of this developing to the point of bond failure.

Further, the influence of parasitic transistors can be reduced by the present invention as described in the next section.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to FIGS. 1 and 2. Portions in these figures that correspond to those in FIG. 3 described above are given the same reference numerals.

In the first embodiment shown in FIG. 1, the cross section shown in FIG. .

It is shown. The semiconductor region 1 is a p-type substrate for an integrated circuit device in which these transistors are incorporated, and its impurity concentration is, for example, about 101s atoms/Cd.

Similarly to FIG. 3, the aforementioned twin wells, an n-type well 2 and a p-type well 3, are provided for the field effect transistor on the low voltage side; for example, the former has an impurity concentration of 10'6 atoms/cj and a Into the depth.

The latter is diffused to a depth of 3-cm with an impurity concentration of 5xlO'' atoms/cj. It is also conventional that channel stopper layers 5 and 4 of n-type and p-type are provided at the periphery of these wells 2 and 3, respectively. It's the same.

In this embodiment as well, the P-type well 3a for the field effect transistor Tn is the p-type well 3a in the above-mentioned twin well.
It is simultaneously diffused to the same impurity concentration and depth as the semiconductor region, thereby making it have the same conductivity type as the semiconductor region but a higher impurity concentration. Furthermore, the diffusion pattern of this well 3a is
As can be seen from a comparison with FIG. 3, the present invention is limited to a much narrower range than the conventional one, particularly in this embodiment, it is limited to approximately the same range as the gate 7 as shown in FIG. 1(b).

The pair of n-type offset diffusion layers 6 for the high breakdown voltage field effect transistor Tn have an impurity concentration of, for example, about 5xlO'' atoms/cdCd, or lower when a high breakdown voltage is required.
As shown in FIG. 1 (0)), the present invention is provided in the same pattern as the conventional one, but the crossing range with the well 3d whose diffusion range is limited as described above is limited to the lower side of the gate 7. Note that the offset expansion ftkJi6 and the channel stoppers N4 and 5 can be thermally diffused to a depth of, for example, 0.5 - at the same time as in the conventional method, and during this thermal diffusion, the field oxide film lO is formed to a thickness of, for example, 1μ. Ru.

From then on, the process is the same as that shown in FIG. 3, resulting in the completed state shown in FIG. 1(a). As an example of implementing the present invention, the gate oxide film 7a is made to have a thickness of approximately 750 mm, and the gate 7 is
．． The n-type source layer 83 and the drain layer 8d are formed by a polycrystalline silicon film with a thickness of about 54 mm/c.
The impurity concentration is diffused to a depth of about 0.5μ with an impurity concentration of about It is better to do so.

As described above, the high voltage field effect transistor Tn according to the present invention is similar to the conventional low voltage field effect transistor Tn.
It can be incorporated into the same chip while using the process for n and tp as is. However, unlike in the past, the offset diffusion layer 6 is in contact not only with the well 3a but also with the semiconductor region 1, and since the impurity concentration of the well 3a is set higher than that of the semiconductor region 1, breakdown of the junction with the well 3a occurs. The voltage is always lower than the breakdown voltage of the junction with the semiconductor region 1, and this does not change even if the impurity concentration of the offset diffusion layer 6 is lowered to increase the breakdown voltage.

Therefore, in the field effect transistor Tn according to the present invention,
Breakdown when an overvoltage is applied occurs uniformly across the periphery of the offset diffusion layer 6 that joins the well 3a below the gate 7, especially over the entire lower part of the gate oxidation M7a, and the offset diffusion that previously caused junction breakdown occurs. This does not occur at the periphery of layer 6 where it joins semiconductor region 1. Therefore, by implementing the present invention, it is possible to eliminate the risk of junction breakdown, and by appropriately lowering the impurity concentration of the offset diffusion layer 6, the withstand voltage value of the field effect transistor can be increased from the conventional approximately 60V to 100V or more. can be improved.

In the second embodiment of the present invention shown in FIG. 2, in addition to this effect, the influence of parasitic transistors can be reduced.

In this second embodiment, the diffusion pattern of the well 3b of the field effect transistor Tn is wider than that of the well 3a of the first embodiment, and a pair of offset diffusion layers 6 are formed as shown in FIGS. In this example, one of the drain layers 8d
It intersects only with the offset diffusion layer 6 connected to the gate 7 below the gate 7 .

Further, in the well 3b of the field effect transistor Tn, a p-type well connection layer 3c is simultaneously diffused with a high impurity concentration, for example, with the source/drain layer 8 of the field effect transistor tp on the low voltage side, and is passed through the well connection layer 3c to the well 3b of the field effect transistor Tn. 3b, the semiconductor region 1 is therefore grounded.

In this state, when the junction between the drain layer 8d and the semiconductor region 1 breaks down due to an overvoltage entering from the drain terminal, the hole current injected into the semiconductor region 1, which is the base of the parasitic transistor, flows through the grounded well. The hole current is bypassed toward the connection layer 3c, and the injection efficiency of the hole current, which is the base current for the parasitic transistor, decreases. Therefore, the influence of the potential of the gate 7 on the well 3b regarding the conduction conditions of the parasitic transistor is reduced.

FIG. 2(C) shows the voltage/current characteristics corresponding to FIG. 3(C) of the field effect transistor Tn according to the second embodiment.As shown in the figure, the breakdown voltage of the field effect transistor Tn is the gate voltage Vg. It can be seen that the parasitic transistor effect is almost constant regardless of the parasitic transistor effect compared to the conventional one.

〔Effect of the invention〕

As explained above, in the present invention, in addition to the usual well, gate, and pair of source/drain layers, a pair of offset diffusion layers with a lower impurity concentration surrounding each source/drain layer to improve the breakdown voltage value are provided. For a field effect transistor comprising a field effect transistor, a well of the same conductivity type is diffused at a higher impurity concentration in a semiconductor region such as a substrate of an integrated circuit device, and the diffusion pattern is formed under at least one of the offset diffusion layers and the gate. By crossing, the location where breakdown occurs when an overvoltage is applied to the field effect transistor is limited to the junction with the well corresponding to the channel formation surface under the gate in the periphery of the offset diffusion layer, and It is possible to eliminate the risk of junction breakdown occurring in a field effect transistor by preventing breakdown from occurring in locations where junction breakdown has conventionally been prone to occur.Furthermore, this advantage can be used to reduce the impurity concentration of the offset diffusion layer. By lowering it, the withstand voltage value of the field effect transistor can be improved.

In the field effect transistor according to the present invention, when a low voltage field effect transistor is incorporated into an integrated circuit device as a high breakdown voltage transistor for an output circuit section together with a highly integrated logic circuit section, its well is diffused at the same time as a so-called twin well. However, it can be fabricated in the same process as low-voltage field effect transistors.

Moreover, according to an advantageous embodiment of the invention in which the diffusion pattern of the well intersects only one offset diffusion layer under the gate, the negative effects of parasitic transistors are almost completely eliminated, and when an overvoltage intrudes, the field effect transistor This reduces the risk of large short-circuit currents flowing inside the
The withstand voltage value can be further improved.

The field effect transistor according to the invention is particularly suitable for integration into integrated circuit devices that directly drive external loads.
While taking advantage of the above-mentioned features, this type of integrated circuit device can be highly effective in increasing its operational reliability, further improving the withstand voltage value of the output circuit, and enabling economical manufacturing.

[Brief explanation of drawings]

1 and 2 relate to the present invention; FIG. 1 is a sectional view and a top view of a first embodiment of a field effect transistor according to the present invention, and a top view of a diffusion pattern, etc., and FIG. 2 is a top view of a second embodiment of a field effect transistor according to the present invention. FIG. 2 is a cross-sectional view, a top view of a diffusion pattern, etc., and a voltage/current characteristic line diagram thereof. FIG. 3 is a sectional view showing a conventional field effect transistor in the same manner as FIG. 2, a top view of a diffusion pattern, etc., and a voltage/current characteristic diagram thereof. In these figures,

Claims (1)

[Claims] A well of one conductivity type in which impurity concentration is diffused into the surface of a semiconductor region of one conductivity type, a thin gate oxide film provided on a part of the surface of the well, and a thin gate oxide film provided on a part of the surface of the well, and a gate disposed so as to face the well, and one of the other conductivity type diffused with the gate in between.
A pair of source/drain layers and the other conductivity type that surrounds each source/drain layer and penetrates a portion of the periphery under the periphery of the gate oxide film and is diffused with an impurity concentration lower than that of the source/drain layer. a pair of offset diffusion layers, the diffusion pattern of the well intersects at least one of the offset diffusion layers below the gate, and a channel is formed between the edges of the pair of offset diffusion layers under the gate oxide film of the well. A field effect transistor that serves as a formation surface.