JPH11214531A - High breakdown voltage semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to easily realize a high breakdown voltage semiconductor device which hardly has a latchup, by making the thickness of an epitaxial layer of a second conductivity type below a well region of a first conductivity type larger than the other sections. SOLUTION: In the surface of an n-type epitaxial layer 6 formed on one face of a p-type semiconductor substrate 10, p-type drain regions 11 and n-type source regions 14 are formed. In p-type well regions 7, n-type drain regions 13 and n-type source regions 16 are formed. Then, gate electrodes 8 are formed on the surface of the drain regions 11, 13 and the source regions 14, 16 through an insulating film to fabricate a p-channel MOS and an n-channel MOS. A high-side section 30 and a low-side section 40 are electrically separated by a p-type isolation region 9. The thickness of a section 6a of the n-type epitaxial layer 6 below the p-type well region 7 in the high-side section 30 is made thicker than the other section. By this method, the width of the base of a parasitic transistor constituted of the section 6a becomes large, thereby reducing a current amplification factor of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high breakdown voltage semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art There is a high-side switch 1 as shown in FIG. 3 for switching when a load is directly connected to a ground potential, and a half-bridge inverter circuit also requires a high-side switch. As shown in FIG.
To configure the semiconductor device of the high-side driver circuit 3 for driving the high-voltage high-side switch 1 connected between the high-voltage power supply and the high-voltage power supply, a signal from the control circuit 5 to the high-side driver circuit 3 is supplied to a high potential And a component of a separation structure for electrically separating the high-side driver circuit 3 from other low-voltage circuit portions are required. As a method of configuring these elements on the same semiconductor substrate, a p-type isolation region is formed in an n-type epitaxial layer on a p-type semiconductor substrate, and a high-side driver is formed in an island separated by pn junction isolation. A method is used in which the circuit 3 is formed, and the structure around the p-type isolation region and the impurity concentration of the n-type epitaxial layer are appropriately selected to electrically isolate even a voltage as high as several hundred volts.
The high-side driver circuit 3 is often formed of a general CMOS device.

In general, in a CMOS device, a phenomenon called latch-up may occur due to a pnpn thyristor structure which is parasitically present in the device structure. When latch-up occurs, the bias power supply voltage applied to the CMOS element (normally about 5 V, 1 in the high-side driver circuit 3)
(About 5 V) and the ground potential. Usually, the structure of the element is devised so that the latch-up hardly occurs, so that the base resistance of the parasitic transistor is reduced and the amplification factor is reduced. Even if latch-up occurs, the power supply voltage is low, so that a certain amount of current does not lead to element destruction.

[0004]

However, in the high breakdown voltage semiconductor device used for the high side driver circuit 3 and the like,
When a latch-up occurs in the CMOS element in the high-side driver circuit 3 due to any cause, a transistor parasitically present in the high breakdown voltage isolation structure constituting the high-side driver circuit 3 due to the current. Is turned on, and a very high current applied between the high side and the low side may cause a very large current to flow through the element, in which case the element is surely destroyed.

The mechanism by which latch-up occurs between the high side and the low side where a high voltage is applied by the parasitic transistor of the element constituting the high side driver circuit 3 is as follows. FIG. 4 is a cross-sectional structural view of a semiconductor device in which a high-side part 30 forming a conventional high-side driver circuit and a low-side part 40 forming a low-side driver circuit are formed by CMOS elements, and an equivalent circuit diagram of the high-side part 30 by parasitic elements. Is shown. A pnp transistor Tr ₁ and an npn transistor Tr ₂ can be parasitically formed in the CMOS device. These transistors Tr ₁ , Tr ₂ and the resistances Repi, R of the n-type epitaxial layer 6 and the p-type well region 7 are
Depending on the w component, due to some cause (for example, CM
For example, negative voltage noise enters the output terminal H _{0 of the} OS with respect to the power supply terminal V _S ), and one of the parasitic transistors is turned on, and the other parasitic transistor is also turned on by the current, and pn
Current will continue to flow through the pn thyristor structure. The above is a common CMOS latch-up phenomenon.
However, in the case of the high-side unit 30 of FIG. 4, there is a parasitic pnp transistor Tr ₃ in addition to the above, and the base potential of the pnp transistor Tr ₃ drops due to the normal CMOS latch-up current and the base current flows. When, the high voltage and high current from the power source V ₁ is flowing between pnp transistor Tr ₃ is turned on since the power terminal Vs-p-type semiconductor substrate 10 (COM). Transistor T
base potential of r ₃ is the potential of the base side is lowered by the voltage drop greater the resistance Repi epitaxial layer 6. Therefore, unless the base resistance by the n-type epitaxial layer 6 is reduced as much as possible, the possibility of latch-up between the high side and the low side increases.

However, in the case where a high-side driver circuit is formed by a high-voltage semiconductor device, the resistance Repi of the n-type epitaxial layer 6 must be set to a high resistance to some extent, so that the high-side-low-side separation voltage is high. Cannot be kept high. Therefore, the resistance of the n-type epitaxial layer 6 cannot be reduced too much in the element structure constituting the high-side high-side driver circuit.

The high-side portion 30 includes a p-channel MOS having a drain region 11 and a source region 14 on the surface of the epitaxial layer 6 and an n-type drain region 13 and a source region 16 in the p-type well region 7. And a gate electrode 8 provided on each surface via an insulating film. The source region 12 of the p-channel MOS is connected to the epitaxial layer 6 by an epitaxial contact region 14, and the source region 16 of the n-channel MOS is connected to the well region 7 via the p + region 15. Between the power source terminal VB and VS are connected to the low voltage power supply V _2.

The low side section 40 is also formed of a p-channel MOS and an n-channel MOS like the high side section 30, and the source region, the drain region and the gate electrode are given the same numbers as those of the high side section 30 respectively. Also L
₀ is an output terminal of the low side unit 40, COM is a common terminal,
Vcc indicates a power supply terminal. Reference numeral 9 denotes a p-type separation region for electrically separating the high side portion 30 and the low side portion 40.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a high withstand voltage semiconductor device in which latch-up does not easily occur, and a manufacturing method of the high withstand voltage semiconductor device which can be easily realized. It is to provide a method.

[0010]

According to the first aspect of the present invention, a semiconductor substrate of a first conductivity type and a surface of a second conductivity type epitaxial layer provided on one surface of the semiconductor substrate are provided. Forming a drain region of the first conductivity type and a source region, forming a drain region of the second conductivity type and a source region in a well region of the first conductivity type provided on the surface of the semiconductor substrate, and forming each drain region; A gate electrode is provided on the surface of the source region via an insulating film to form a p-channel MOS and an n-channel MOS, respectively.
A channel MOS, comprising a complementary MOS semiconductor device in which the circuit regions of both MOSs are electrically separated by an isolation region of the first conductivity type, wherein the second conductivity type lower portion of the well region of the first conductivity type is formed. It is characterized in that the thickness of the epitaxial layer is thicker than other portions.

According to a second aspect of the present invention, in the method of manufacturing a high-voltage semiconductor device according to the first aspect, the first conductivity type semiconductor substrate is etched by etching at a position where the first conductivity type well region is to be formed. And then forming the second conductivity type epitaxial layer and then forming the complementary CMOS semiconductor device. Therefore, according to the present invention, in the high breakdown voltage semiconductor device constituting the high side driver circuit and the like, the n under the p-type well region is reduced.
By making the thickness of the type epitaxial layer thicker than the other portions, the base width of the parasitic pnp transistor is increased, and the current amplification factor of the transistor is reduced, so that the parasitic pnp transistor is less likely to be turned on. Is less likely to occur.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. FIG. 1 is a structural sectional view of a high breakdown voltage semiconductor device according to one embodiment of the present invention. In the figure, a p-type semiconductor substrate 1
An n-type epitaxial layer 6 is formed on one surface of P. 0, and a p-type isolation region 9 is provided for electrically separating the high side portion 30 and the low side portion 40. High side part 30
Then, a p-channel M formed by a p-type drain region 11 and a source region 14 is provided on the surface of the epitaxial layer 6.
An n-channel MO including an OS and an n-type drain region 13 and a source region 16 in a p-type well region 7;
S, and a gate electrode 8 is provided on each of the S through an insulating film. The source region 12 of the p-channel MOS is n + in the n + epitaxial contact region 14.
It is connected to the epitaxial layer 6 of the mold type. Similarly, the source region 14 of the n-channel MOS includes the p-type well region 7 and the p-type well region 7.
It is connected via a + well contact region 15.

Although the basic structure is the same as that of the conventional example shown in FIG. 4, in this embodiment, the thickness of the portion 6a of the n-type epitaxial layer 6 below the p-type well region 7 is made larger than that of other portions. The base width of the parasitic transistor (corresponding to Tr ₃ in FIG. 4) formed by the portion 6a is wider than that of the conventional transistor. The other components are the same as those in FIG.
A symbol is attached and the description is omitted.

Next, a method of manufacturing the high breakdown voltage semiconductor device of FIG. 1 will be described with reference to FIG. First, a mask 20 of an appropriate material is applied to the p-type semiconductor substrate 10 shown in FIG. 2A except for a place where the p-type well region 7 is to be finally formed, for example, KOH (potassium hydroxide solution) or the like. FIG. 2 shows the seven portions that become p-type well regions using a silicon anisotropic etching solution.
As shown in FIG. 3B, a proper depth is dug by etching. The digging depth is the parasitic p that is finally formed in the device.
The selection may be made so that the base width of the np transistor is sufficiently wide and the current amplification factor is sufficiently low. Further, the etching method is not limited to the above method.

Next, as shown in FIG. 2C, an n-type layer is deposited by an epitaxial growth method to form an n-type epitaxial layer 6. At this time, the p-type semiconductor substrate 1
Although a step is formed in a portion where 0 is dug by etching, the surface may be polished to a desired thickness after the epitaxial layer 6 is stacked thicker. Epitaxial layer 6
Thickness and impurity concentration may be selected so that the separation withstand voltage of the high side portion 30 can be obtained.

Next, as shown in FIG. 2D, the separation region 9 for separating the high side portion 30 and the low side portion 40 is formed by p
It is formed by diffusing a mold impurity. Then, a p-type well region 7 is formed above the portion where the p-type semiconductor substrate 10 is dug by etching as shown in FIG.
Thereafter, CMOS transistors required for the circuit may be formed on each island using a normal process.

[0017]

According to the first aspect of the present invention, a first conductivity type semiconductor substrate and a first conductivity type drain region and a source region are formed on the surface of the second conductivity type epitaxial layer provided on one surface of the semiconductor substrate. A drain region and a source region of the second conductivity type are formed in a well region of the first conductivity type provided on the surface of the semiconductor substrate, and a gate is formed on the surface of each drain region and source region via an insulating film. A complementary MOS semiconductor device in which electrodes are provided to form a p-channel MOS and an n-channel MOS, respectively, and the circuit regions of both MOSs are electrically separated by a first conductive type separation region; Since the thickness of the second conductivity type epitaxial layer below the region is made thicker than the other portions, even when a normal CMOS portion causes latch-up due to a parasitic transistor,
Without turning on a parasitic transistor existing between the high side and the low side, it is possible to prevent latch-up from occurring in a portion to which a high voltage is applied. In a pressure-resistant integrated circuit, it is possible to prevent a failure directly leading to the destruction of the element, and therefore, the reliability of the element is increased and the quality is significantly improved.

According to a second aspect of the present invention, in the method for manufacturing a high-voltage semiconductor device according to the first aspect, the first conductivity type semiconductor substrate is etched by etching at a position where the first conductivity type well region is to be formed. Since the complementary CMOS semiconductor device is formed after forming the second conductivity type epitaxial layer after that, the desired high breakdown voltage semiconductor device can be easily realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of a high-side driver circuit according to the present invention.

FIG. 2 is an explanatory diagram of a manufacturing method according to the embodiment.

FIG. 3 is a circuit diagram of a high-side switch.

FIG. 4 is a cross-sectional view of a semiconductor device constituting a conventional high-side switch circuit.

[Explanation of symbols]

 Reference Signs List 6 n-type epitaxial layer 7 p-type well region 8 gate region 9 p-type isolation region 10 p-type semiconductor substrate 11 drain region 12 source region 13 source region 14 epitaxial contact region 16 drain region 15 well contact region 30 high side portion 40 low side portion

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 9, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

Generally , in a CMOS device, a phenomenon called latch-up may occur due to a pnpn thyristor structure which is parasitically present in the device structure. When the latch-up occurs, the bias power supply voltage applied to the CMOS element (normally about 5 V, 15
V) and the ground potential.
Usually, the structure of the element is devised so that the latch-up hardly occurs, so that the base resistance of the parasitic transistor is reduced and the amplification factor is reduced. Even if latch-up occurs, the power supply voltage is low, so that a certain amount of current does not lead to element destruction.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

According to a second aspect of the present invention, in the method of manufacturing a high-voltage semiconductor device according to the first aspect, the first conductivity type semiconductor substrate is etched by etching at a position where the first conductivity type well region is to be formed. And then forming the second conductivity type epitaxial layer and then forming the complementary CMOS semiconductor device. Therefore, in the present invention, in the high breakdown voltage semiconductor device that make up the high-side driver circuit or the like to a structure in which the thickness of the lower portion of the n-type epitaxial layer of the p-type well region thicker than the other portions, the parasitic pnp Since the base width of the transistor is increased, the current amplification factor of the transistor is reduced, and the parasitic pnp transistor is less likely to be turned on.
Therefore, latch-up hardly occurs.

Claims (2)

[Claims] A semiconductor substrate of a first conductivity type, and a drain region and a source region of a first conductivity type are formed on the surface of an epitaxial layer of a second conductivity type provided on one surface of the semiconductor substrate. A drain region and a source region of the second conductivity type are formed in the well region of the first conductivity type provided in the semiconductor device, and a gate electrode is provided on the surface of each of the drain region and the source region via an insulating film to form a p-channel. A complementary MOS semiconductor device comprising a MOS and an n-channel MOS, wherein the circuit regions of both MOSs are electrically separated by an isolation region of a first conductivity type; A high breakdown voltage semiconductor device, characterized in that the thickness of a conductive type epitaxial layer is made thicker than other portions. 2. A method for manufacturing a high breakdown voltage semiconductor device according to claim 1, wherein said first conductivity type semiconductor substrate is dug by etching at a position where said first conductivity type well region is to be formed. Thereafter, the complementary CMOS semiconductor device is formed after forming the second conductivity type epitaxial layer.