JPH09139633A - Isolation gate type semiconductor device incorporating control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain negative gate protection and high frequency processing required to be used for a source follower circuit in the isolation gate semiconductor device incorporating a control circuit such as an overheat protection circuit and an overcurrent protection circuit. SOLUTION: A MOSFET 33 is connected between a gate terminal 61 and an internal gate 64 of a power MOSFET to attain high frequency processing. A drain of a MOSFET 34 connects to the gate terminal 61, a source and a body are connected to a body of the MOSFET 33, and a gate connects to a source terminal 62. The body and the source of a MOSFET 41 connect to the body of a MOSFET 33 via a resistor 58, the drain connects to the source terminal and the gate connects to the gate terminal. Even when a negative voltage is applied to the gate terminal 61, the MOSFETs 34, 41 prevent the operation of a parasitic npn transistor(TR) where the drain and the body of the MOSFET 33 are used for the emitter and the base respectively and the drain region of the power MOSFET is used for the collector.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a power MOSF.
ET and IGBT (Insulated gate bipolar transistor)
In particular, the present invention relates to an insulated gate semiconductor device including a control circuit including a control circuit such as a negative gate voltage protection circuit and an overheat protection circuit on the same chip.

[0002]

2. Description of the Related Art Conventionally, as an insulated gate type semiconductor device having a built-in control circuit of this type, for example, in order to improve reliability, an overheat protection circuit or the like is provided on the same chip as disclosed in JP-A-7-58293. Power MOS with built-in control circuit
FETs are known. In this conventional example, a gate resistor is connected between the external gate terminal and the internal gate terminal, and a gate cutoff circuit MOSFET is connected between the internal gate terminal and the external source terminal. As a result, when the chip temperature rises above the specified temperature, the MOSFET for gate cutoff circuit is turned on, a gate current is passed through the resistor, and the power MO before the power MOSFET is destroyed.
The SFET can be turned off.

In this conventional example, the control circuit built in the same chip is constructed by using an element of a self-isolation type element isolation structure formed in the drain region of the power MOSFET in order to suppress an increase in process steps. There is. Therefore, although the cost is suppressed low, the parasitic npn transistor existing between the drain of the MOSFET for gate cutoff circuit and the drain of the power MOSFET when the gate voltage becomes negative is changed from the external drain terminal to the external gate terminal. There is a possibility that a leak current will flow to.
Therefore, as a countermeasure against this, a diode for cutting off the base current of the parasitic npn transistor is connected in series with the MOSFET for gate cutoff circuit, and a diode for preventing the diode from breaking down is connected to the external gate terminal and the external source terminal. Was connected between.

A power MO having a built-in overheat protection circuit is provided.
An example in which a MOSFET is used instead of the above-mentioned gate resistor in order to increase the frequency of SFET is disclosed in Japanese Patent Laid-Open No. 6-24441.
No. 4 discloses this. In this conventional example, instead of using a gate resistor between the external gate terminal and the internal gate terminal, a MOSFET in which the body potential is fixed to the source terminal voltage is used.

[0005]

However, according to the former conventional example described above, even if an attempt is made to use a MOSFET instead of the gate resistance to increase the frequency as in the latter conventional example, it is necessary to increase the frequency. Since the source and drain of the MOSFET inserted between the internal gate terminal and the external gate terminal are not connected to the source terminal of the power MOSFET, the series circuit of the MOSFET and the diode for the gate cutoff circuit and the external gate terminal Depending on the diode provided between the external source terminal and the external source terminal, it is possible to prevent the parasitic npn transistor existing between the drain of the inserted MOSFET and the drain of the power MOSFET from operating when the gate voltage becomes negative. I couldn't. Further, due to the voltage drop of the diode of the series circuit inserted between the internal gate terminal and the external source terminal of the power MOSFET, the power MOSFET cannot be completely shut off, or the minimum gate terminal for the control circuit to operate normally. There is a problem in that the voltage becomes high by inserting this diode.

Further, in the latter conventional example in which the frequency is increased, a MOSFET formed in the substrate instead of the gate resistor is used.
In the case of using, the threshold voltage becomes high due to the substrate bias effect, and the on-resistance of the MOSFET used in place of the gate resistance does not decrease, so that it is difficult to achieve a high frequency. The MOSF instead of the gate resistor
Polycrystalline silicon MOSFET formed on ET substrate
In the case of using, the carrier mobility in the polycrystalline silicon is low, the power MOSFET cannot be sufficiently driven, and the on-resistance is not so low, so that it is difficult to increase the frequency.

Therefore, a first object of the present invention is that the source and drain of the control circuit MOSFET are both power MOS.
It is an object of the present invention to provide an insulated gate semiconductor device with a built-in control circuit, which has a negative gate voltage protection in which the parasitic npn transistor operation does not matter even when it is not connected to the source terminal of the FET.

A second object of the present invention is power MO.
An object of the present invention is to provide an insulated gate semiconductor device with a built-in control circuit, which can surely cut off the SFET and reduce the minimum gate terminal voltage for the normal operation of the control circuit as compared with the conventional case.

Furthermore, a third object of the present invention is to control the body potential so as to avoid the influence of the substrate bias effect of the MOSFET used in place of the gate resistance to reduce the on-resistance and to enable high frequency control. An object is to provide an insulated gate semiconductor device with a built-in circuit.

Furthermore, a fourth object of the present invention is to provide a MIS.
In a general semiconductor device using an FET (insulated gate type field effect transistor), the source / source of the MISFET is
Even if a reverse polarity signal (negative polarity with respect to the normal body potential in the case of an n-channel FET) is input to the drain path, the parasitic bipolar transistor operation formed by the semiconductor substrate, the body, and the source or drain is It is to provide a device that does not pose a problem.

[0011]

In order to achieve the above object, an insulated gate semiconductor device with a built-in control circuit according to the present invention has a drain terminal 60, a gate terminal 61, and a source terminal as shown in FIG. A power MOSFET 29 having at least 62, a drain connected to the drain terminal 60, and a source connected to the source terminal 62;
First MOSFET for controlling a power MOSFET provided between the gate 64 and the gate terminal 61 of the OSFET
At least a T33 and a second MOSFET 34 whose body and source are connected to the body of the first MOSFET, whose drain is connected to the gate terminal 61, and whose gate is connected to the source terminal 62 are characterized by the above-mentioned characteristics.

In the insulated gate semiconductor device with a built-in control circuit, instead of the second MOSFET, the body and source are connected to the body of the first MOSFET, the drain is connected to the source terminal, and the gate is connected to the gate terminal. The third MOSFET (in FIG. 1, the MOSFET 4
1) and / or a first diode (diode 18 in FIG. 4) connected between the body of the first MOSFET and the source terminal may be used, or the second diode may be used. And the third MOSFET
Can also be configured.

Further, the insulated gate semiconductor device with a built-in control circuit according to the present invention is provided with at least a drain terminal 60, a gate terminal 61 and a source terminal 62 as shown in FIG. 5, and the drain is connected to the drain terminal 60. Power MOSFET 29 whose source is connected to the source terminal 62
A first MOSFET 33 for controlling the power MOSFET provided between the gate of the power MOSFET and the gate terminal 61; and a body and a source of the first MOSF.
A third MOS connected to the body of the ET33, connected to the source terminal 62 at the drain and connected at the gate to the gate terminal 61
In addition to the FET 41, the body and source are the third MOSF.
At least one fourth M connected to the body of the ET41
OSFET, that is, MOSFET 31 and MOSFET 3
2 or the like, or, for example, as shown in FIG. 6, the first diode 18 is used instead of the third MOSFET 41, and the body and source of the fourth MOSFET such as MOSFET 31 and MOSFET 32 are first. It may be configured to be connected to the diode.

In this case, the body and the source are further connected to the body of the first MOSFET 33, the drain is connected to the gate terminal 61, and the gate is connected to the source terminal 62.
It is preferable to provide the MOSFET 34.

Furthermore, the body and the source are connected to the source terminal 6
At least one fifth MOSFET connected to 2, ie MOSFET 36 in FIG. 3, may be provided. In this case, the drain and gate terminal 6 of the fifth MOSFET
It is preferable that a second diode 16 is further provided between the gate 1 and the gate of the power MOSFET.

Further, for example, as shown in FIG. 7, at least one sixth MOSF whose body is connected to the body of the third MOSFET 41 and whose source is connected to the source terminal 62.
ET, for example, MOSFET37, MOSFET38 and the like may be further provided. In this case, the third diode 1 is provided between the drain of the sixth MOSFET and the gate terminal 61.
It is preferable to further provide 1, 14 or 17.

Further, for example, as shown in FIG. 1, a fourth diode 12 is further provided between the gate terminal 61 and the source terminal 62, or the fourth diode 12 and the fourth diode 12 are connected in series in the opposite direction. It is preferable to provide the fifth diode 13 as well. Further, for example, as shown in FIG. 1, it is preferable to further provide a first resistor 58 between the body of the first MOSFET 33 and the source terminal 62.

Further, for example, as shown in FIG.
It is preferable that the OSFET 33 has a source connected to the gate 64 of the power MOSFET and a drain connected to the gate terminal 61. In this case, the gate 6 of the power MOSFET
4 and the gate terminal 61 between the sixth diode 15 and /
Alternatively, a second resistor 50 may be provided, and a seventh MOSFET 48 having a gate and a drain connected to the gate 64 of the power MOSFET, a body connected to the body of the first MOSFET 33, and a source connected to the gate terminal 61 is provided. May be.

Further, for example, as shown in FIG.
A third gate is provided between the gate of the OSFET 33 and the gate terminal 61.
Is preferably provided with the resistor 51 and / or the seventh diode 14, and further preferably provided with the capacitor 25 between the gate and the source of the first MOSFET 33.

Further, the first MOSFET to the third M
It is preferable to use the depletion type OSFET. The insulated gate semiconductor device with a built-in control circuit according to the present invention includes a first MOSFET 3 as shown in FIG.
The body region 104a of No. 3 and the body region 107 of the power MOSFET 29 are preferably separated by the drain region 102 of the power MOSFET.

The insulated gate semiconductor device with a built-in control circuit according to the present invention is provided with at least a drain terminal 60, a gate terminal 61 and a source terminal 62 as shown in FIG. 8, and the drain is connected to the drain terminal 61. Power MOSFET 29 whose source is connected to the source terminal 62
, The gate and source are connected and the drain is connected to the gate terminal 61
At least one depletion type eighth MOSFET connected to the power MOSFET 29 for use in the control circuit of the power MOSFET 29
That is, the MOSFET 43, the MOSFET 44, etc., the body and the source are connected to the body of the eighth MOSFET, the drain is connected to the gate terminal 61, and the gate is the source terminal 6
At least the second MOSFET 34 connected to the second MOSFET 34.

In this case, instead of the second MOSFET,
A third MOSFET 41 having a body and a source connected to the body of the eighth MOSFET, a drain connected to the source terminal, and a gate connected to the gate terminal, and / or an eighth M
The first connected between the body of the OSFET and the source terminal
The diode (the diode 18 in FIG. 4) may be used, or the third MOSFET may be used together with the second MOSFET.

Also in this case, it is preferable that the body region of the eighth MOSFET and the body region of the power MOSFET are separated by the drain region of the power MOSFET.

Further, the present invention is generalized to a MISFE.
When applied to a semiconductor device using T, for example, as shown in FIG.
As shown in FIG. 2, a substrate, a first conductivity type first region 102 provided on the substrate, a second conductivity type second region 104a in contact with the first region 102, and the second region. 104
a first MISF of the first conductivity type channel provided in a
In a semiconductor device including the ET33, when a first input voltage in the forward direction of a pn junction between the source or drain and the second region is input to the source or drain 109b of the first MISFET. , A switching means (34, 34) which either brings the second region into a floating state or connects the source or drain to which the first input voltage is input and the second region.
41) may be provided.

In this case, the source or the drain of the switch means is connected to the source or the drain of the first MISFET to which the first input voltage is input,
It is preferable that the body of the first MISFET is connected to the drain or source thereof and the body thereof, and the gate thereof is composed of the second MISFET 34 connected to the first potential.

The switching means may be the first
The MISFET of which the gate is connected to the source or drain to which the first input voltage is input,
The source or drain and the body of the SFET may be connected to the body, and the drain or the source may be formed of the third MISFET 41 connected to the first potential, or may be combined with the second MISFET 34. Good. Third MISFET 41 and second MISFET 34
In the case of combining and, it is preferable to provide a resistance element connected between the body of the first MISFET and the source or drain and the body of the third MISFET.

The switching means may be the first
May be constituted by a diode connected between the body of the MISFET and the first potential.
It may be combined with ET34. Diode and second M
When combined with the ISFET 34, it is preferable to provide a resistance element connected between the body of the first MISFET and the diode.

Further, the first area 102 is the second area.
P between the first region 102 and the second region 104a when the region 104a is connected to the first potential.
The second such that a reverse voltage is applied to the n-junction
If it is connected to the electric potential of, breakdown is prevented, which is preferable.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the conventional insulated gate type semiconductor device with a built-in control circuit, the control circuit is configured by using the lateral MOSFET having the self-isolation type element isolation structure formed in the drain region of the power MOSFET. Power M as before
The first MOSFET that controls the OSFET is a lateral MOS
If the gate terminal is negative, the body of the first MOSFET is the base, the source or drain of the first MOSFET is the emitter, and the power MOSFET is a FET.
The parasitic npn transistor having the drain as the collector is turned on, and a leak current flows from the drain terminal to the gate terminal. On the other hand, according to a preferred embodiment of the insulated gate type semiconductor device with a built-in control circuit according to the present invention, as shown in FIG.
Since the second MOSFET 34 in which the body and the source are connected and the drain is connected to the gate terminal 61 is provided in the body of, the second MOSFET is turned on when the gate terminal becomes negative. MOSFET
It is possible to prevent the parasitic npn transistor existing at 33 from being forward-biased between the emitter and the base and being turned on. Here, when the second MOSFET is of the depletion type, this negative gate voltage protection comes to work quickly.

Further, when the first diode 18 is provided between the body and the source terminal of the first MOSFET 33, the first diode 18 is forward biased when a positive voltage is applied to the gate terminal. Therefore, the first MOS
The body of the FET is almost equal to the source potential, but when a negative voltage is applied to the gate terminal, the first diode is reverse-biased, so a base current flows through the parasitic npn transistor existing in the first MOSFET. Absent. Therefore, the parasitic npn transistor does not turn on.

When the body of the first MOSFET 33 is provided with the third MOSFET 41 in which the body and the source are connected, the drain is connected to the source terminal 62, and the gate is connected to the gate terminal 61, the third MOSFET 41 is provided. M
The OSFET is turned on so that the body of the first MOSFET becomes the source terminal voltage when a positive voltage is applied to the gate terminal, but is turned off when a negative voltage is applied to the gate terminal. No base current flows in the parasitic npn transistor existing in the MOSFET. By providing the third MOSFET 41 in this manner, there is an advantage that the minimum value of the gate terminal voltage can be reduced and the operation margin of the gate voltage is increased, as compared with the negative gate voltage protection circuit using the diode of the conventional example. Further, when the third MOSFET is a depletion type, the body voltage of the first MOSFET becomes equal to the source terminal voltage even if the gate terminal voltage is low, so that the operation margin of the gate voltage can be further improved. .

The second MOSFET 34 is used to prevent forward bias between the emitter and the base of the parasitic npn transistor, and the third MOSFET 41 is used.
Alternatively, when the base current of the parasitic npn transistor is blocked by using the first diode 18, the parasitic npn transistor operation preventing effect is increased. This is the second M
When the current drive capability of the OSFET is sufficiently high, even if only the second MOSFET is used, the parasitic npn operation can be prevented even if the gate terminal voltage drops rapidly. However, since the gate voltage value is around 0 volt, 2 MOS
This is because the effect of preventing the parasitic npn transistor operation may not appear unless the FET is sufficiently turned on. On the other hand, when only the third MOSFET or the first diode is used, the gate voltage value is 0. Although it has the effect of preventing parasitic npn transistor operation even near the voltage,
This is because the parasitic npn transistor may be turned on temporarily when the gate voltage drops at high speed.

For the control circuit MOSFET in which neither the drain nor the source is connected to the source terminal, for example, the MOSFET 33 shown in FIG. 3, the above-mentioned measure for preventing the parasitic npn transistor operation is taken, while the source is grounded. A fifth MOSFET for the control circuit,
For example, in order to prevent the operation of the parasitic npn transistor existing in the MOSFET 36, the second diode 16 is connected in series with the parasitic npn transistor, and the breakdown voltage of the second diode 16 is lower than that of the second diode 16 in order to prevent the second diode from breakdown. The fifth diode 13 may be connected between the gate terminal 61 and the source terminal 62.

The source of the first MOSFET is power MO
First MOSFET connected to the gate of SFET
When the drain of the first MOSFET 33 is connected to the gate terminal, the body of the first MOSFET 33 is connected to the power MOS as shown in FIG.
By separating from the body of the FET 29, the potential of the body of the first MOSFET can also rise when a positive voltage is applied to the gate terminal.
The substrate bias effect of the SFET is reduced. Therefore, the effective on-resistance of the first MOSFET is reduced, and the power MOSFET can be turned on at high speed.

In the case of the fifth MOSFET having the body and the source connected to the source terminal, for example, the MOSFET 36 used in the overcurrent protection circuit in FIG. 3, the second MOSFET is used.
The diode 16 is provided between the gate 64 of the power MOSFET and the drain of the MOSFET 36 to prevent the parasitic npn transistor operation that occurs when a negative gate voltage is applied to the gate terminal. In addition,
A similar source-grounded fifth MOSFET in the control circuit
And the drain is connected to the gate terminal side, the second diode may be provided between the drain of the fifth MOSFET and the gate terminal 61.

Furthermore, by connecting the first resistor between the body and the source terminal of the first MOSFET,
Since the body potential of the MOSFET becomes higher, the power M
Since the OSFET can be turned on at high speed and the body voltage drops near the source voltage in the steady state, the first MO
There is no change in the on resistance of the SFET, and the power MOSF
The ET characteristics can be stabilized.

Further, for example, as shown in FIG.
When the source of the OSFET 33 is connected to the gate 64 of the power MOSFET and the drain of the first MOSFET 33 is connected to the gate terminal 61, the sixth diode 15 is connected to the gate 64 of the power MOSFET and the gate terminal 6.
7 or the gate and the drain are connected to the gate 64 of the power MOSFET and the body is connected to the body of the first MOSFET 33, and the source is connected to the gate terminal 61.
By further providing, the gate charge of the power MOSFET can be discharged at high speed.

Further, by connecting the second resistor 50 between the gate terminal 61 and the gate 64 of the power MOSFET, the gate voltage when the power MOSFET is in the ON state becomes equal to the voltage of the gate terminal, so that the power MO
The ON resistance of the SFET can be reduced.

Further, the seventh diode 14 and the third resistor 51 are provided between the gate of the first MOSFET 33 and the gate terminal 61, and the capacitor 25 is provided between the gate and the source of the first MOSFET. With the bootstrap circuit configuration provided, the first MOSFET
Since the gate voltage becomes high, the on-resistance becomes low, and the on-time of the power MOSFET is improved.

The on-resistance increases because the first MOSFET 33 is subjected to the substrate bias, but the first MOSFET is
By making T a depletion type MOSFET,
Since the on-resistance can be set to be small even when the substrate bias is applied, the turn-on speed of the power MOSFET can be improved.

The body region of the first MOSFET and the body region of the power MOSFET are connected to the power MOSF.
Separation at the ET drain region results in the first MO
The body potential of the first MOSFET can be controlled independently of the potential of the power MOSFET so that the parasitic npn transistor based on the body region of the SFET does not turn on. Further, the potential of the body of the first MOSFET can be made higher than the source potential of the power MOSFET, and it is possible to suppress an effective increase in the on-resistance of the first MOSFET due to the substrate bias effect. The separation of the body region can be realized without any additional process.

At least a depletion type eighth MOSF which is used for the control circuit of the power MOSFET by connecting the gate and the source and connecting the drain to the gate terminal 61.
Second body in which the body and the source are connected to the body and the gate is connected to the source terminal 62 to the body of the ET body, for example, the MOSFETs 43 to 45 constituting the active load in FIG.
The second MOSFET is provided by providing the second MOSFET 34 when a negative gate voltage is applied to the gate terminal.
Is turned on, and the eighth MOS is turned on similarly to the first MOSFET.
It prevents the parasitic npn transistor also present in the FET from operating.

Further, when the first diode is provided between the body and the source terminal of the eighth MOSFET, or
In the case where the body of the MOSFET is provided with a third MOSFET in which the body is connected to the source, the drain is connected to the source terminal, and the gate is connected to the gate terminal, or the second MOSFET and the third MOSFET are provided. The action and effect of are the same as the action and effect provided in the above-described first MOSFET.

Further, when the present invention is generalized, M
When a reverse polarity signal is input to the source / drain path of the ISFET, a forward voltage from p to n is normally applied to the pn junction between the body 104a and the source or drain of the ISFET. There is a problem that a parasitic bipolar transistor operation formed by the body and the source or drain occurs, but when the first input voltage which is a reverse polarity signal is input, the second bipolar transistor becomes a body.
The base current of the parasitic bipolar transistor flows by setting the region 104a in a floating state or connecting the source or drain to which the first input voltage is input and the second region (body) to the same potential. Since there is none, the above problem is solved.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A more specific embodiment of an insulated gate semiconductor device having a control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 1 is a circuit configuration diagram showing a first embodiment of an insulated gate semiconductor device having a control circuit according to the present invention, and FIG. 2 realizes the circuit configuration shown in FIG. FIG. 3 is a cross-sectional structure diagram of a main part of an insulated gate semiconductor device having a control circuit.

The semiconductor device of this embodiment having the structure shown in FIG. 2 can be formed by the same process as the conventional vertical power MOSFET. In FIG. 2, reference numeral 101 is a resistivity of 0.02 Ω · c using antimony or arsenic as an impurity.
A high-concentration n-type semiconductor substrate of about m to 0.002 Ω · cm is shown, and a resistivity of 1 to 2 Ω is provided on the n-type semiconductor substrate 101.
An n-type epitaxial layer 102 having a size of about 10 cm is formed.

About 5 parts are formed in the power MOSFET formation part.
The first p-type well diffusion layer 1 having a depth of 6 μm and a dose amount of about 1 × 10 ¹⁵ cm ⁻² between the patterns of the polycrystalline silicon gate layer 106a formed on the 0 nm gate oxide film 105a.
03a and the polycrystalline silicon gate layer 106a as a mask, formed in a self-aligned manner with a depth of 2 μm and a dose of 5 × 1.
The body p-type diffusion layer 107 having a depth of about 0 ¹³ cm ^-2 and a depth of 0.
An n-type diffusion layer 109a for source having a thickness of 4 μm and a dose amount of about 1 × 10 ¹⁶ cm ⁻² is provided, and the body 107 and the aluminum electrode 11 are provided.
Depth 0.5 to make ohmic contact between 2a
A high-concentration p-type diffusion layer 110a having a thickness of μm and a dose of about 1 × 10 ¹⁵ cm ⁻² is provided, and an aluminum electrode layer 112a serving as a source electrode is formed on the polycrystalline silicon gate layer 106a via an insulating layer 111. There is.

In the protection circuit portion, the second p-type well diffusion layer 104 having a depth of 5 μm and a dose amount of about 2 × ¹³ cm ^−2.
a and 104b as bodies, the high-concentration n-type diffusion layer 109b formed in the same step as the n-type diffusion layer 109a as a drain diffusion layer and a source diffusion layer, and formed in the same step as the high-concentration p-type diffusion layer 110a. The high-concentration p-type diffusion layer 110b is formed on the bodies 104a and 104b and the aluminum electrode 11.
2b to 112e as a high-concentration p-type diffusion layer for establishing ohmic contact, and the polycrystalline silicon gate layer 106b formed in the same step as the polycrystalline silicon gate layer 106a is used as the gate electrode of the protection circuit MOSFET. The low-concentration n-type region 108 is formed as a low-concentration n-type offset region having a dose amount of about 5 × 10 ¹² cm ⁻² for improving the drain breakdown voltage.

Further, the capacitor 25 of FIG. 1 in which both two electrodes fluctuate with respect to the potential of the source terminal 62 is a MOSF.
As one electrode connected to the gate of ET33, a polycrystalline silicon gate layer 106c formed in the same step as the polycrystalline silicon gate layer 106a is used, and power MOSFE is used.
Before the step of forming the polycrystalline silicon gate layer 106c as the other electrode connected to the gate 64 of T29, the dose amount is 1
The n-type diffusion layer 113 is formed by ion-implanting arsenic or phosphorus of about 10 ¹⁵ cm ^-2 .
Reference numeral 105b is a field oxide film, 112g,
112f is an aluminum electrode.

Source-grounded or drain-grounded MOSFETs 31 and 4 which are the control circuit MOSFETs shown in FIG.
1 or MOSF in which both drain and source are not grounded
The ET33 is formed in the n-type epitaxial layer 102 which is the drain region of the power MOSFET (note that
In the cross-sectional structural view of the main part of FIG. 2, MOSFETs 41, 33,
Capacitor 25 and part of power MOSFET 29 are shown). Therefore, although there is an advantage that the control circuit can be built in at low cost as in the conventional power MOSFET process, the drain region 10 of the power MOSFET is provided.
2 is a collector, and MOSF is a control circuit MOSFET
Drain / source region 1 of ET31 and MOSFET33
09b is an emitter, and MO is a control circuit MOSFET.
Body region 104 of SFET 31 and MOSFET 33
There is a problem that there is a parasitic npn transistor based on a and 104b. This problem is solved in the insulated gate semiconductor device with a built-in control circuit of this embodiment by adopting the circuit configuration shown in FIG.

In FIG. 1, reference numeral 60 is a drain terminal, 61 is a gate terminal, 62 is a source terminal, and 63 is a cutoff terminal. The shut-off terminal 63 forcibly powers the power MOS even when a positive voltage is applied to the gate terminal 61.
This is a terminal for shutting off the FET 29. In the case of this figure, when the input voltage of the shutoff terminal 63 is higher than the threshold voltage of the MOSFETs 31, 32, the power MOSFET 29 can be forcibly shut off.

The MOSFET 32, whose drain is connected to the gate of the MOSFET 33 and whose source is connected to the source terminal 62 of the power MOSFET 29, is normally in an off state, and is turned on when a voltage for shutting off is applied to the shutoff terminal 63. Become. By using this MOSFET 32, when the power MOSFET 29 is turned on, the MOSFET 32 is turned off.
The voltage of 1 is applied to the gate of the MOSFET 33 through the series circuit of the diode 14 and the resistor 51. As a result, MOSF
When the ON resistance of the ET33 is lowered to enable high-speed switching and the power MOSFET 29 is forcibly cut off by the cutoff terminal 63, the MOSFET 32 is turned on, so that the gate of the MOSFET 33 is lowered to the voltage of the source terminal 62. Even if the resistance increases and the driving capability of the MOSFET 31 is low, the power MO
The SFET 29 can be turned off.

In this embodiment, the drain of the MOSFET 34 is connected to the gate terminal 61, and the source and body are MOS.
Connected to the body of FET33, the gate is the source terminal 62
Connected to The drain of the MOSFET 41 is connected to the source terminal 62, the source and the body are connected to the body of the MOSFET 33 via the resistor 58, and the gate is connected to the gate terminal 61. In addition, source-grounded MOSFE
The diode 11 is connected to T31 so as to be inserted in series between the gate 64 and the source terminal 62 of the power MOSFET, and the diode 14 is connected to the source-grounded MOSFET 32 in series between the gate terminal 61 and the source terminal 62. I am doing it. Further, a diode 12 and a diode 13 connected in series in opposite directions are connected between the gate terminal 61 and the source terminal 62. The drain of the MOSFET 33 is connected to the gate terminal 61, and the source is the power MOSF.
It is connected to the gate 64 of the ET, the series circuit of the diode 14 and the resistor 51 is connected between the drain and gate of the MOSFET 33, and the capacitor 25 is connected between the gate and source of the MOSFET 33. Although the resistor 58 is not necessary, the presence of the resistor 58 causes the MOSFET 3
Since the body potential of 3 becomes high, the power MOSFET can be turned on at high speed, and in the steady state, the body potential drops near the source voltage, so that the ON resistance of the MOSFET 33 does not fluctuate and the characteristics of the power MOSFET are stabilized. There is an advantage that

In the semiconductor device of this embodiment having such a structure, as is apparent from the cross-sectional structure diagram of FIG. 2, the drains of the source-grounded MOSFETs 31 and 32 serve as emitters, the bodies thereof serve as bases, and the power MOSFETs are used.
There is a parasitic npn transistor having a drain of 29 as a collector, which is disclosed in Japanese Patent Laid-Open No. 7-5.
Similar to the configuration of the negative gate voltage protection circuit described in Japanese Patent No. 8293, the diodes 11 and 14 cut off the base current of the parasitic npn transistor to prevent the operation of the parasitic npn transistor, and are connected in series in the opposite direction. By setting the total breakdown voltage of the diode 12 and the diode 13 lower than the breakdown voltage of the diodes 11 and 14, the breakdown of the diodes 11 and 14 is prevented when the gate terminal 61 becomes negative.

However, the control circuit MOSFET 33 and the power MOSFET whose drain is connected to the gate terminal 61 and whose source is connected to the gate 64 of the power MOSFET.
Between T29, the drain of MOSFET 33 is the emitter, the body of MOSFET 33 is the base, and the power MO
There is a parasitic npn transistor whose collector is the drain terminal 60 of the SFET 29. A MOS in which neither the source nor the drain is connected to the source terminal 62.
Regarding the parasitic npn transistor caused by the FET,
In the configuration of the conventional negative gate voltage protection circuit described above, parasitic npn
Cannot prevent transistor operation.

Therefore, in this embodiment, the MOSFET 34 is used to prevent the operation of the parasitic npn transistor as follows. When a negative gate voltage is applied to the gate terminal 61, the MOSFET 34 turns on,
The drain of 34 (that is, the emitter of the parasitic npn transistor) is connected to the body of MOSFET 33 (that is, the base of the parasitic npn transistor) via a connection node 71 between the source of MOSFET 34 and the body. Therefore, the emitter-base diode of the parasitic npn transistor is short-circuited, which causes parasitic np transistor.
N-transistor operation is prevented. Also, MOSFET
41 operates as follows. When the voltage at the gate terminal 61 is positive, the MOSFET 41 turns on and the MOSFET 33
The body of is connected to the source terminal 62 so as to be the source terminal voltage, but when the voltage of the gate terminal 61 becomes negative, the MOSFET 41 is turned off and the MOSFET 33 is turned off.
The base current of the parasitic npn transistor existing in the above is cut off to prevent the parasitic npn transistor operation.
In this way, it is possible to prevent a leak current from the drain terminal 60 to the gate terminal 61, which is caused by the operation of the parasitic npn transistor described above.

Since the withstand voltage of the parasitic npn transistor is lower than the withstand voltage of the power MOSFET 29, when a negative gate voltage is applied to the gate terminal 61 and a high voltage is also applied to the drain terminal 60, the parasitic npn transistor breaks. Although there is a possibility that the down current is concentrated and the element is destroyed, in the circuit of this embodiment using the diodes 11 and 14 and the MOSFETs 34 and 41, the parasitic npn transistor is almost short-circuited between the base and the emitter, and the base open-breakdown voltage BV _CEO is exceeded. Also high withstand voltage, that is,
Since the withstand voltage is almost close to the collector-base withstand voltage BV _CBO , there is an effect that this element breakdown can be prevented.

Parasitic npn of MOSFET 33 for control circuit
In order to prevent transistor operation, MOSFET3
4 or MOSFET 41 may be used, but in the present embodiment, in order to enhance the effect of negative gate voltage protection, MO
The case where both SFETs 34 and 41 are used is shown. This is because even if the gate driving voltage of the MOSFET 34 is high and the gate terminal voltage drops at a high speed,
Although only the use of the SFET 34 has the effect of preventing the parasitic npn transistor operation, the effect of preventing the parasitic npn transistor operation may not appear because the MOSFET 34 does not easily turn on sufficiently when the value of the gate terminal voltage is around 0 volt. On the other hand, when only the MOSFET 41 is used, the parasitic npn transistor operation is prevented even when the value of the gate terminal voltage is near 0 volt, but the parasitic npn is temporarily reduced when the gate voltage is rapidly reduced.
This is because the transistor may turn on. By making the MOSFET 34 a depletion type, the current driving capability when the negative gate voltage starts to be applied to the gate terminal 61 is improved, so that the effect of preventing the parasitic npn transistor operation can be improved.

Furthermore, in the circuit of this embodiment, when a voltage is applied to the gate terminal 61, the body potential of the MOSFET 33 rises due to the influence of parasitic capacitance.
The substrate bias effect of 33 is reduced. Therefore, MO
The effective on-resistance of the SFET 33 is reduced, and the power MOSFET 29 can be turned on at high speed. After the gate terminal voltage becomes constant at a high potential, the MOSFET 33 has a time constant determined by the resistor 58 and the parasitic capacitance.
The body potential of is lowered to the voltage of the source terminal 62. Here, as the value of the resistor 58 increases, the power MOSFET 2
Although the turn-on speed of 9 improves, when the voltage of the drain terminal 60 decreases, it takes time to release the minority carriers injected from the body region of the MOSFET 33 to the drain region of the power MOSFET. Time can be long. Therefore, the value of resistor 58 is optimized to avoid this problem. In addition, by shorting the resistor 58, the MOSFET
The same effect can be obtained by increasing the on-resistance of 41 and increasing the threshold voltage.

The on-resistance of the MOSFET 33 increases due to the substrate bias effect. However, the depletion type MOSFET can reduce the on-resistance even when a substrate bias is applied to improve the turn-on speed of the power MOSFET 29. .

Further, in the circuit of this embodiment, when a positive voltage is applied to the gate terminal 61, the diode 14 and the resistor 5 are connected.
The gate of the MOSFET 33 is charged via 1 to turn on the power MOSFET 33 and further charge the capacitor 25. Therefore, when the voltage of the gate 64 of the power MOSFET rises, the diode 14 and the capacitor 25 operate as a bootstrap circuit which works to boost the gate of the MOSFET 33. Therefore,
M compared to the case without diode 14 and capacitor 25
Since the gate voltage of OSFET33 becomes high, MOSF
ET33 has low on resistance and high speed power MOSFE
There is an effect that T29 can be turned on. As for the capacitor 25, the parasitic capacitance of the MOSFET 33 can be used when the capacitance value may be small. Also, regarding the diode 14, the MOSFET 3
In some cases, it may not be necessary to arrange it between the drain and gate of No. 3. Even if the gate voltage of the MOSFET 33 is not boosted higher than the voltage of the gate terminal 61, that is, even if the bootstrap principle is not used, the voltage of the gate terminal 61 for turning on the MOSFET 33 is the power MOSF.
This is the case when the voltage can be higher than the voltage of the gate 64 of ET.
In such a case, the frequency of the power MOSFET can be increased, so that the role of the diode 14 is only to prevent the negative drain current from flowing between the drain and the source of the MOSFET 32. Therefore, the diode 14 is
MOSF, not between the gate and drain of SFET33
It may be arranged between the gate of the ET 33 and the drain of the MOSFET 32.

Furthermore, the gate and drain are connected to the power MO.
Connected to the gate 64 of SFET, the source is the gate terminal 6
If the MOSFET 48 connected to the body of the MOSFET 33 is added, the power MO
Since the electric charge of the gate 64 of the SFET is pulled out earlier, the power MOSFET 29 can be cut off at high speed. Even when the diode 15 is added between the gate terminal 61 and the gate 64 of the power MOSFET,
The effect is that the power MOSFET 29 can be cut off faster than the resistance 50 alone.

Further, in this embodiment, the potential of the gate 64 of the power MOSFET is lower than the potential of the gate terminal 61,
By adding the resistor 50, at the DC level, the same voltage as that of the gate terminal 61 is applied to the gate 64 of the power MOSFET, and the ON resistance of the power MOSFET 29 can be sufficiently lowered.

The insulated gate semiconductor device with a built-in control circuit of the present embodiment is characterized by the body region of the vertical power MOSFET 29 and the body region of the lateral MOSFET 33 for the control circuit, as shown in the sectional view of the essential part of FIG. Power M
It is separated by the drain region of the OSFET 29. By separating by the body region in this way, as described above, when a positive gate voltage is applied to the gate terminal 61, the body potential of the MOSFET 33 becomes higher than the source potential of the power MOSFET, and the gate terminal 61 and the power MOSFET are separated. The ON resistance of the MOSFET 33 connected between the gates 64 of the
The SFET 29 can be switched at high speed.

Further, in the case of this embodiment, the MOSFET
Power MOSFET 29 between 41 and MOSFET 33
Are separated by the drain region of. As a result, FIG.
As shown in the circuit of FIG.
The body potential of 3 and the body potential of MOSFET 41 can be separated.

As for the capacitor 25 in FIG. 1 in which the two electrodes forming the capacitor both fluctuate with respect to the potential of the source terminal 62, the polycrystalline silicon gate layer 1 is used as one electrode connected to the gate side of the MOSFET 33.
The polycrystalline silicon gate layer 106c formed in the same step as that of 06a is used, and the n-type diffusion layer 113 is used as the other electrode connected to the gate 64 of the power MOSFET.
The type diffusion layer 113 and the n-type epitaxial layer 102 that serves as the drain of the power MOSFET 29 are reliably separated, and in order to achieve the protection of the negative gate voltage, M is always used.
The p-type diffusion layer 104c whose potential changes together with the body of the OSET 33 is used to separate the n-type diffusion layer 113.

In the case of the circuit of FIG. 1, MOSFET 33 and M
Since the body of the OSFET 34 is directly connected, it can be formed in one body region (p-type diffusion layer 104a). The MOSFET 31 and the MOSFET 32 are connected to the body region of the power MOSFET 29 in the region M
Second p-type well diffusion layer 104 of OSFETs 33 and 41
It is formed by providing the same p-type diffusion layer as a and 104b. Since such an isolation structure can be realized without any additional step in the conventional power MOSFET process, it has an advantage of low cost.

The MOSFET 33 and the MOSFET 4
The second p-type well diffusion layer 1 for protection circuit
04a and 104b, a high-concentration p-type diffusion layer 103b, which has a higher surface concentration than that of the first p-type well diffusion layer 103a and is formed in the same process as the first p-type well diffusion layer 103a, is provided between the MOSFETs in the protection circuit section and between the MOSFET and the power in the protection circuit section A channel is prevented from being formed between the MOSFET and the drain region. Further, the resistors and diodes used in this embodiment are formed of a polycrystalline silicon layer so that parasitic elements are not generated, as in the case of the conventional example disclosed in JP-A-7-58293.

<Embodiment 2> FIG. 3 is a circuit configuration diagram showing a second embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 3, the same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, the MOSFETs 31 and 32 are not controlled by the external terminal 63 as in the first embodiment, but when the temperature inside the semiconductor chip rises above a specified value and when the drain current flows above a specified value. Power MOSFET
It is different from the first embodiment in that it is controlled by a built-in circuit that limits or blocks the drain current of 29. For driving the MOSFET 33, the series circuit of the diode 14 and the resistor 51 provided between the drain and gate of the MOSFET 33 and the power MOSFET 29 such as the capacitor 25 provided between the source and gate of the MOSFET 33, which are described in the configuration of FIG. Configuration, and the gate terminal 61 is the source terminal 6
The configuration of the negative gate voltage protection circuit for preventing the parasitic npn transistor operation that occurs when it becomes lower than 2 and the actions and effects thereof are almost the same as the actions and effects obtained by the first embodiment.

In FIG. 3, diode 9 and resistor 52 form a constant voltage circuit and generate a constant voltage at node 65.
The diode 17 is provided to prevent the operation of the parasitic npn transistor existing in the MOSFETs 37 to 40 when the gate terminal 61 has a negative voltage.
The role of the diode 11 with respect to T31 is the same.

Further, the diode array 10 and the resistors 53 and 54
The MOSFET 40 constitutes a temperature detection circuit, and when the chip temperature rises, the forward voltage of the diode array 10 drops, so that the voltage of the gate 66 of the MOSFET 40 drops. When the voltage of the gate 66 becomes lower than the threshold voltage of the MOSFET 40, the MOSFET 40 turns off and the resistor 5
The input voltage of the latch circuit formed by 5, 56 and MOSFETs 37 to 39 increases. In this latch circuit, the MOSFET 37 is in the ON state at normal temperature and the MOSFETs 38 and 39 are
Is off. However, if the chip temperature rises above the specified temperature and the input voltage of the latch circuit increases, the MO
The SFETs 38 and 39 are turned on, the MOSFET 37 is turned off, and the voltage of the node 67 having the same function as the cutoff terminal 63 in FIG. 1 is increased. Therefore, the power MOSFET 29 is cut off.

Further, the power MOSFET section is composed of MOSFETs 29 and 30 having a cell ratio of, for example, 1000: 1, and about 1/1000 of the drain current flowing through the power MOSFET 29 flows through the MOSFET 30. The resistor 57 and the MOSFET 36 form an overcurrent protection circuit,
When the drain current of the MOSFET 30 increases, the MOSF
The voltage on the gate 68 of the ET 36 increases. When a drain current more than the specified level flows, the MOSFET 36 starts to turn on. Therefore, the drain-source resistance of the MOSFET 33 increases and the voltage of the gate 64 of the power MOSFETs 29 and 30 decreases, so that the drain current of the power MOSFET is controlled to fall within the specified current value.
Further, the diode 16 is a parasitic n existing in the MOSFET 36 when the gate terminal 61 has a negative gate voltage.
It is provided to prevent the operation of the pn transistor, and has the same role as that of the diode 11 with respect to the MOSFET 31.

The cross-sectional structure of the semiconductor device of this embodiment is almost the same as the structure of FIG. 2 shown in the first embodiment. That is, since the body potentials of the MOSFETs 37 to 40 are also equal to the body potential of the power MOSFET 29, M
The same power MO as OSFET31 and MOSFET32
They are substantially the same except that they can be formed in the p-type diffusion layer connected to the body region of the SFET.

<Third Embodiment> FIG. 4 is a circuit configuration diagram showing a third embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 4, the same components as those shown in FIG. 3 of the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the MOSFE is used as the negative gate voltage protection.
The difference from the second embodiment is that a diode 18 is used instead of T41. Therefore, the minimum value of the body potential of the MOSFET 33 does not become zero volt but becomes about 0.5 V, and the other points are exactly the same as the constituent portions shown in FIG. Therefore, the circuit configuration for driving the power MOSFET 29 at a high frequency, and the gate terminal 6
Parasitic n that occurs when 1 becomes lower than the source terminal 62
The circuit configuration of the negative gate voltage protection for preventing the operation of the pn transistor is the same as that of the first and second embodiments described with reference to FIGS. 1 and 3, and the same effects can be obtained. still,
Regarding the cross-sectional structure of the semiconductor device of the present embodiment, the MOSF
It is the same as the case of the second embodiment except that the ET 41 is not necessary.

<Embodiment 4> FIG. 5 is a circuit configuration diagram showing a fourth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 5, the same components as those of the second embodiment shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the ground of the overheat protection circuit portion is not directly connected to the source terminal 62, but the MOSFET 41 is
2 is different from the second embodiment in that it is connected to the body and the diodes 11 and 17 are omitted. Diode 1
1, 17 can be made unnecessary by using the MOSFET 41 as the emitters of the drains of the MOSFETs 31, 32, 37 to 40, and the body of these as the base, and the power MOS.
This is because it is possible to prevent the operation of the parasitic npn transistor having the drain of the FET as the collector. Therefore, FIG.
In the case of the embodiment described above, the gate voltage of the power MOSFET 29 cannot be lowered to about 0.5 V or less due to the presence of the diode 11, and therefore the power MOSFE in the overheat cutoff state.
While there is a possibility that the drain current of T cannot be cut off sufficiently, in the case of this embodiment, a MOSFET with a low on-resistance is used.
By using 41, there is an advantage that the power MOSFET can be surely cut off.

Since the voltage drop in the diode 17 is eliminated as compared with the case of the embodiment of FIG. 3, the operation margin of the gate terminal voltage for the normal operation of the control circuit such as the constant voltage circuit or the latch circuit is improved. There is also the effect.

When the MOSFET 41 is a depletion type MOSFET, the source potentials of the MOSFETs 31, 32, 37-40 can be aligned with the voltage of the source terminal 62 even if the voltage of the gate terminal 61 is low. It is easy to improve the operation margin with respect to the gate voltage of the circuit and the latch circuit.

Further, in the present embodiment, the body and the source of the MOSFET 36 of the overcurrent protection circuit are MOSFETs.
41 is connected to the source terminal 62 without being connected to the body 41, as in the embodiment of FIGS. This is the gate terminal 6
When a voltage is applied to 1 and shortly thereafter, the MOSF
The voltage between the drain and source of ET41 increases and MO
This is to prevent the SFET 36 from turning on easily and preventing the overcurrent protection circuit from operating normally.

The other points are exactly the same as the constituent parts shown in FIG. Therefore, the power MOSFET 2
1 and 3 show a circuit configuration for driving 9 at a high frequency and a circuit configuration for negative gate voltage protection for preventing parasitic npn transistor operation that occurs when the gate terminal 61 becomes lower than the source terminal 62. The same effects as those obtained in the first and second embodiments are obtained.

The cross-sectional structure of the semiconductor device of this embodiment is almost the same as that of the second embodiment, but the MOSFE
The body of T31, 32, 37-40 is power MOSFE
It is formed in a body region (p-type diffusion layer 104b) which is separated from the body region of T and is connected to the body of MOSFET 41.

<Fifth Embodiment> FIG. 6 is a circuit configuration diagram showing a fifth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 6, the same components as those of the fourth embodiment shown in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, this embodiment is different from the fourth embodiment in that the diode 18 is used instead of the MOSFET 41. Therefore, unlike the embodiment having the configuration shown in FIG. 5, there is no improvement in the ability to shut off the power MOSFET at the time of shutting off overheat and no improvement in the operating margin with respect to the gate terminal voltage, but the implementation of the configuration shown in FIGS. The diodes 11 and 17 for protecting the negative gate voltage, which are required in the example, are unnecessary. Others are shown in FIG.
And the effects and advantages obtained by the embodiment shown in FIG.

The sectional structure of the semiconductor device of this embodiment is almost the same as that of the fourth embodiment. That is, since the MOSFET 41 shown in FIG. 5 is not provided in the case of this embodiment, the MOSFETs 31, 32, 37 to 40 are used instead.
Is formed in one body region (p-type diffusion layer 104b).

<Sixth Embodiment> FIG. 7 is a circuit configuration diagram showing a sixth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 7, the same components as those of the fourth embodiment shown in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, MOSFETs T31, 32, 37-
40 sources, diode 9 and diode string 10
Is connected to the source terminal 62 and the diode 1
1 and 17 is different from the fourth embodiment. Therefore, when a positive gate voltage is applied, the MOSFET 41
Is turned on and the bodies and the sources of the MOSFETs T31, 32, 37 to 40 have the same potential. Incidentally, in the case of the present embodiment, the MOSFETs T31,3 can be provided without the diodes 11,17.
The drains of 2, 37 to 40 are used as emitters, and these M
Power MOSFET based on the body of OSFET
The base current of the parasitic npn transistor whose drain is the collector can be cut off. However, since the collector current of the parasitic npn transistor cannot be cut off, when the base current of the parasitic npn transistor transiently flows, a current may flow from the source terminal 62 to the gate terminal 61. Since this collector current may act in the direction of turning on the parasitic npn transistor, the diode 11 and the diode 17 are provided in this embodiment. Others are the same as the actions and effects obtained by the embodiment shown in FIGS.

The sectional structure of the semiconductor device of this embodiment is as follows.
This is almost the same as the case of the fourth embodiment except that the contact between the body of the MOSFET 31, 32, 37 to 40 and the source is different.

<Embodiment 7> FIG. 8 is a circuit configuration diagram showing a seventh embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG. 8, the same components as those of the fourth embodiment shown in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, the depletion type MOSFETs 43 to 45 in which the gates and the sources are connected are used as active loads instead of the resistors 54 to 56 for the overheat protection circuit, and the MOSFET 33 and the MOSF for driving the same are used.
The fourth embodiment is different from the fourth embodiment in that the drive circuit including the ET 48, the resistors 50 and 51, the diodes 14 and 15 and the capacitor 25 is not used, and the resistor 49 is connected between the gate 64 and the gate terminal 61. Each body of the MOSFETs 43 to 45 is connected to the node 71.

With this structure, the resistance area can be reduced in this embodiment, and the active load MOSFET 4 can be compared with the case where the resistors 54 to 56 are used.
By using 3-45, the driving power of the power MOSFET can be driven at a high speed if the driving power is constant, and the driving power can be lowered if the speed is constant. The resistor 49 is a MOSFE
A resistor for lowering the potential of the gate 64 by the voltage drop of the current flowing from the gate terminal 61 through the resistor 49 when the T31 or the MOSFET 36 is turned on,
As a result, the power MOSFET can be cut off to perform overheat protection, or the drain current of the power MOSFET can be reduced to perform overcurrent protection.

FIG. 8 shows the power M used in Examples 1 to 6.
MOSFET for driving the OSFET at high frequency and its driving circuit, that is, MOSFET 33 and MOSFE whose source and drain are not connected to the source terminal 62
Although there is no circuit for driving T33, the MOSFETs 43 to 45 used as active loads have neither source nor drain connected to the source terminal 62.
Since it is an SFET, the same negative gate voltage protection circuit as that for the MOSFET 33, that is, the negative gate voltage protection circuit composed of the MOSFETs 34 and 41 is required for the MOSFETs 43 to 45.

The sectional structure of the semiconductor device of this embodiment is the same as that of the fourth embodiment. Further, it is said that the same action and effect can be obtained even if the configuration using the resistors 54 to 56 as the load described in the embodiment of FIGS. 3 to 7 is replaced with the active loads 43 to 45 as in the present embodiment. There is no end.

<Embodiment 8> FIG. 9 is a circuit diagram showing an eighth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. This embodiment shows a transistor configuration capable of preventing the occurrence of a breakdown voltage failure due to the parasitic bipolar transistor operation or the occurrence of a reverse drain current due to the parasitic diode operation when a reverse polarity signal is input to the drain of the MOSFET 33. In FIG. 9, reference numeral 60 is the drain terminal of the MOSFET 33, and 69 is MO.
The gate terminal of the SFET 33 and 70 denote the source terminal of the MOSFET 33, respectively. MO to this source terminal 70
The gate of the SFET 34 and the drain of the MOSFET 41 are connected, and the body of the MOSFET 33 is connected to the MOSFET 3
The source and body of MOSFET 4 and the source and body of MOSFET 41 are connected, and the drain terminal 6 of MOSFET 33 is connected.
The gate of the MOSFET 41 and the drain of the MOSFET 34 are connected to 0.

The cross-sectional structure of the semiconductor device of this embodiment having such a circuit configuration is the same as the cross-sectional structure diagram and wiring diagram of Embodiment 1 shown in FIG. It is in a short-circuited state. In the case of the circuit configuration of the present embodiment shown in FIG.
Since the resistor 58 in the structure shown in FIG.
The mold well layers 104a and 104b may be connected.
Further, since the vertical power MOSFET 29 is not built in,
N-type epitaxial layer 102 on high concentration n-type substrate 101
Need not be formed, and an n-type substrate used in a conventional MOSFET process may be used. Alternatively, when the p-type substrate is used instead of the n-type substrate, the p-type well layers 104a and 104b may not be formed.

The semiconductor device of this embodiment operates as follows. (a) When the voltage of the gate terminal 69 is equal to the voltage of the source terminal 70: The voltage of the drain terminal 60 becomes high,
When a voltage equal to or higher than the threshold voltage is applied to the gate of the FET 41, the MOSFET 41 turns on, so that the MOSF
The body of ET33 is connected to the source terminal 70. In this case, the parasitic npn transistor existing between the drain terminal 60 and the source terminal 70 and having the source, body, and drain of the MOSFET 33 as the emitter, base, and collector, respectively, is in the cutoff state, so that the drain breakdown voltage of the MOSFET 33 is reduced and the drain leakage current is reduced. Can be prevented. Therefore, the MOSFET 33 is turned off.

On the other hand, the voltage of the drain terminal 60 drops,
When a positive voltage equal to or lower than the threshold voltage is applied to the gate of the MOSFET 41, the MOSFET 41 and the MOSFET
Since both T34 are in the off state, the body potential of the MOSFET 33 becomes floating. Therefore, the parasitic n existing between the drain terminal 60 and the source terminal 70 is
No drain current flows through the pn transistor. In addition, this condition (gate terminal 69 and source terminal 7
When the voltage of 0 is the same, the voltage of the drain terminal 60 is lowered, and a positive voltage below the threshold voltage is applied to the gate of the MOSFET 41), only a low voltage is applied between the drain terminal 60 and the source terminal 70. Therefore, the parasitic npn transistor does not break down.

(B) When the voltage of the gate terminal 69 is equal to the voltage of the drain terminal 60: When the voltage of the source terminal 70 becomes high and a voltage higher than the threshold voltage is applied to the gate of the MOSFET 34, the MOSFET 34 turns on. The body of the MOSFET 33 is connected to the drain terminal 60. In this case, the parasitic npn transistor having the source, body, and drain of the MOSFET 33 as the collector, the base, and the emitter is in the cutoff state.
It is possible to prevent the drain breakdown voltage of the FET 33 from decreasing and a drain leak current from occurring. Therefore, the MOSFET 33 is turned off.

On the other hand, the voltage at the source terminal 70 drops and M
When a positive voltage below the threshold voltage is applied to the gate of the OSFET 34, the MOSFET 34 and the MOSFET
Since both 41 are off, the body potential of the MOSFET 33 becomes floating. Therefore, the parasitic np existing between the drain terminal 60 and the source terminal 70
No drain current flows through the n-transistor. In addition, this condition (gate terminal 69 and drain terminal 6
When the voltage of 0 is the same, the voltage of the source terminal 70 drops, and a positive voltage below the threshold voltage is applied to the gate of the MOSFET 34), only a low voltage is applied between the drain terminal 60 and the source terminal 70. Therefore, the parasitic npn transistor does not break down.

Since the semiconductor device having the circuit configuration of this embodiment operates as described above, the MOSFET 3 is used as a switch element of a power switch circuit using a battery.
Even when the battery is erroneously reverse-connected, that is, the reverse polarity signal is input to the drain of the MOSFET 33, the semiconductor device of the present embodiment blocks the reverse drain current of the MOSFET 33 when the third embodiment is used. Therefore, the MOSFET 33 and the power system using the same can be protected.

In addition, in the present embodiment, FIG.
A diode in which a resistor 58 is inserted as in the circuit configuration shown in FIG. 4 or the cathode is connected to the source terminal 70 instead of the MOSFET 41 and the anode is connected to the body of the MOSFET 33 as in the circuit configuration shown in FIG. 18
The same effect can be obtained with a configuration using. When a polycrystalline silicon diode is used as the diode 18, the breakdown voltage when the drain voltage of the MOSFET 33 is positive can be improved. This is because the built-in potential of the pn junction of the polycrystalline silicon diode is lower than the built-in potential between the body and the source of the MOSFET 33, so that the parasitic bipolar transistor operation is hard to occur.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments,
For example, all MOSFETs including power MOSFETs have been described as n-channel MOSFETs in the above embodiments, but similar effects can be obtained even if all the elements are p-channel MOSFETs, within the range not departing from the spirit of the present invention. Of course, various design changes can be made.

In the above embodiments, the power MOS is used.
An insulated gate semiconductor device with a built-in control circuit using an FET has been described as an example. However, in the case of an IGBT with a built-in control circuit that uses an IGBT (Insulated gate bipolar transistor) instead of a power MOSFET, a parasitic npn transistor is used instead of a parasitic npn transistor. There is a problem that a thyristor is generated and a leak current flows from the collector terminal of the IGBT to the gate terminal. As measures against this, the operation of the parasitic element when a negative gate voltage is applied is prevented in the same manner as the circuit and the device structure described above, and the IG with a built-in control circuit is used.
It is possible to increase the frequency of BT.

[0100]

As is apparent from the above-described embodiments, according to the present invention, for example, a power MOSFE with a built-in control circuit.
A control MOSFET in which neither the drain nor the source used to increase the frequency of T is connected to the source terminal
It is possible to prevent the parasitic npn transistor from operating even if it is formed in the drain region of the power MOSFET. Therefore, even when a negative gate voltage is applied as in the source follower circuit, a leak current can be prevented from occurring between the drain terminal and the gate terminal.

Further, the power MOSFET can be surely cut off, and the operation margin of the gate terminal voltage for the control circuit to operate normally can be expanded as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional structural view showing a main part of a semiconductor device that realizes the circuit configuration shown in FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the semiconductor device according to the present invention.

FIG. 5 is a circuit configuration diagram showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 6 is a circuit configuration diagram showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 7 is a circuit configuration diagram showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 8 is a circuit configuration diagram showing a seventh embodiment of the semiconductor device according to the present invention.

FIG. 9 is a circuit configuration diagram showing an eighth embodiment of the semiconductor device according to the present invention.

[Explanation of symbols]

9 ... Diode, 10 ... Diode array, 11-17 ... Diode, 25 ... Capacitor, 29, 30 ... Power MOSFET, 31-34, 36-41 ... MOSFET, 43-45, 48 ... MOSFET, 49-58 ... Resistor, 60 ... Drain terminal, 61 ... Gate terminal, 62 ... Source terminal, 63 ... Breaking terminal, 64 ... Power MOSFET gate, 65 ... Constant voltage circuit output node, 66 ... MOSFET40 gate, 67 ... Latch circuit output node, 68 ... Gate of MOSFET 36, 69 ... Gate terminal, 70 ... Source terminal, 71 ... Connection node between source and body of MOSFET 34, 101 ... N-type substrate, 102 ... N-type epitaxial layer, 103a, 103b ... First p-type well Layer, 104a, 104b, 104c ... Second p-type well , 105a, 105b ... Oxide film, 106a, 106b ... Gate electrode, 106c ... Polycrystalline silicon gate layer (capacitor electrode), 107 ... P-type diffusion layer, 108 ... Low-concentration n-type diffusion layer, 109a, 109b, 113 ... N Type diffusion layer, 110a, 110b ... N type diffusion layer, 111 ... Insulating layer, 112a-112g ... Aluminum electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78

Claims (40)

[Claims] 1. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, a drain connected to the drain terminal and a source connected to the source terminal, and a gate between the power MOSFET and the gate terminal. For controlling a power MOSFET provided in the
And a second MOSFET having a body and a source connected to the body of the first MOSFET, a drain connected to the gate terminal, and a gate connected to the source terminal. Insulated gate semiconductor device with built-in circuit. 2. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, a drain connected to the drain terminal and a source connected to the source terminal; and a gate between the power MOSFET and the gate terminal. For controlling a power MOSFET provided in the
A control comprising at least a SFET, and a third MOSFET having a body and a source connected to the body of the first MOSFET, a drain connected to the source terminal, and a gate connected to the gate terminal. Insulated gate semiconductor device with built-in circuit. 3. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, a drain connected to the drain terminal and a source connected to the source terminal, and a gate between the power MOSFET and the gate terminal. For controlling a power MOSFET provided in the
An insulated gate semiconductor device with a built-in control circuit, comprising at least an SFET and a first diode connected between the body of the first MOSFET and the source terminal. 4. A body and a source of the third MOSFET.
At least one fourth MOSFE connected to the body of the
The insulated gate semiconductor device with a built-in control circuit according to claim 2, further comprising T. 5. The insulated gate semiconductor device with a built-in control circuit according to claim 3, further comprising at least one fourth MOSFET having a body and a source connected to the first diode. 6. A body and a source for the first MOSFET
6. An insulated gate semiconductor with a built-in control circuit according to any one of claims 2 to 5, further comprising a second MOSFET connected to the body of the device, the drain thereof connected to the gate terminal, and the gate connected to the source terminal. apparatus. 7. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising at least one fifth MOSFET having a body and a source connected to the source terminal. 8. The insulated gate semiconductor device with a built-in control circuit according to claim 7, further comprising a second diode provided between the drain of the fifth MOSFET and the gate terminal or the gate of the power MOSFET. . 9. The method according to claim 1, further comprising at least one sixth MOSFET having a body connected to the body of the third MOSFET and a source connected to the source terminal.
9. An insulated gate semiconductor device with a built-in control circuit according to any one of 8 above. 10. The insulated gate semiconductor device with a built-in control circuit according to claim 9, further comprising a third diode provided between the drain and the gate terminal of the sixth MOSFET. 11. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a fourth diode provided between the gate terminal and the source terminal. 12. The insulated gate semiconductor device with a built-in control circuit according to claim 11, further comprising a fifth diode provided in series with the fourth diode in a reverse direction between the gate terminal and the source terminal. . 13. A first resistor is further provided between the body of the first MOSFET and the source terminal.
13. An insulated gate semiconductor device with a built-in control circuit according to any one of 1 to 12. 14. The insulated gate type with a built-in control circuit according to claim 1, wherein the first MOSFET has a source connected to a gate of a power MOSFET and a drain connected to the gate terminal. Semiconductor device. 15. A sixth diode is provided between the gate and the gate terminal of the power MOSFET.
Insulated gate type semiconductor device with a built-in control circuit according to. 16. A power MOSF having a gate and a drain.
The body is connected to the gate of ET and the body is connected to the first MOSFET.
16. The insulated gate semiconductor device with a built-in control circuit according to claim 14 or 15, further comprising a seventh MOSFET connected to the body of the device and having a source connected to the gate terminal. 17. A second resistor is provided between the gate terminal and the gate of the power MOSFET.
7. An insulated gate semiconductor device with a built-in control circuit according to any one of 6 above. 18. A third resistor and a seventh diode connected in series between the gate of the first MOSFET and the gate terminal, and provided between the gate and the source of the first MOSFET. 15. The insulated gate semiconductor device with a built-in control circuit according to claim 14, further comprising: 19. The insulated gate semiconductor device with a built-in control circuit according to claim 1, wherein the first MOSFET is a depletion type. 20. The insulated gate semiconductor device with a built-in control circuit according to claim 1, wherein the second MOSFET is a depletion type. 21. The insulated gate semiconductor device with a built-in control circuit according to claim 1, wherein the third MOSFET is a depletion type. 22. A body region of the first MOSFET and a body region of the power MOSFET have the power M.
The drain regions of the OSFETs are separated from each other.
22. An insulated gate semiconductor device with a built-in control circuit according to any one of 21. 23. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, the drain being connected to the drain terminal and the source being connected to the source terminal; and the gate being connected to the source and the drain being connected to the gate terminal. At least one depletion type eighth MOSFET connected to and used in the control circuit of the power MOSFET, a body and a source connected to the body of the eighth MOSFET, a drain connected to the gate terminal, and a gate connected to the source terminal An insulated gate semiconductor device with a built-in control circuit, comprising at least a connected second MOSFET. 24. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, the drain being connected to the drain terminal and the source being connected to the source terminal; and the gate being connected to the source and the drain being connected to the gate terminal. At least one depletion type eighth MOSFET connected to and used in the control circuit of the power MOSFET, a body and a source connected to the body of the eighth MOSFET, a drain connected to the source terminal, and a gate connected to the gate terminal An insulated gate semiconductor device with a built-in control circuit, comprising at least a connected third MOSFET. 25. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, the drain being connected to the drain terminal and the source being connected to the source terminal; and the gate being connected to the source and the drain being connected to the gate terminal. At least one depletion-type eighth MOSFET connected to and used in the control circuit of the power MOSFET, and a first diode connected between the body of the eighth MOSFET and the source terminal An insulated gate semiconductor device with a built-in control circuit. 26. A body and a source are the eighth MOSFE
A second MOSFET in which the body of T is connected, the drain is connected to the gate terminal, and the gate is connected to the source terminal.
26. The insulated gate semiconductor device with a built-in control circuit according to claim 24 or 25, further comprising: 27. The body region of the eighth MOSFET and the body region of the power MOSFET have the power M.
24. The drain region of the OSFET is separated.
27. An insulated gate semiconductor device with a built-in control circuit according to any one of claims 26 to 26. 28. The insulated gate semiconductor device with a built-in control circuit according to claim 22, wherein the body region of the first MOSFET is in contact with the drain region of the power MOSFET. 29. The insulated gate semiconductor device with a built-in control circuit according to claim 27, wherein the body region of the eighth MOSFET is in contact with the drain region of the power MOSFET. 30. A substrate, a first-conductivity-type first region provided in the substrate, a second-conductivity-type second region in contact with the first region, and a second region provided in the second region. In a semiconductor device comprising a first conductivity type channel first MISFET, a source or drain of the first MISFET has a pn junction between the source or drain and the second region in a forward direction. A switching means which, when a voltage is input, either brings the second region into a floating state or connects the source or drain to which the first input voltage is input and the second region. A semiconductor device comprising: 31. The switching means includes the first M
The source or drain of the ISFET to which the first input voltage is input is connected to the source or drain, the body of the first MISFET is connected to the drain or source and the body thereof, and the gate thereof is at the first potential. 31. The semiconductor device according to claim 30, further comprising a second MISFET connected to the. 32. The switching means comprises the first M
A gate is connected to a source or a drain of the ISFET to which the first input voltage is input, and the first MI is connected.
31. The semiconductor device according to claim 30, wherein the body of the SFET is connected to its source or drain and its body, and the third MISFET has its drain or source connected to the first potential. 33. The first switching means for the switching means.
31. The semiconductor device according to claim 30, further comprising a diode connected between the body of the ISFET and the first potential. 34. The switching means includes the first M
A gate is connected to a source or a drain of the ISFET to which the first input voltage is input, and the first MISF
32. The semiconductor device according to claim 31, wherein the body of ET is connected to its source or drain and its body, and has a third MISFET whose drain or source is connected to the first potential. 35. The switching means comprises the first M
32. The semiconductor device according to claim 31, further comprising a diode connected between the body of the ISFET and the first potential. 36. The semiconductor according to claim 34, further comprising a first resistance element connected between the body of the first MISFET and the source or drain of the third MISFET and the body. apparatus. 37. The semiconductor device according to claim 36, further comprising a second resistance element connected between the body of the first MISFET and the diode. 38. The first region is opposite to the pn junction between the first region and the second region when the second region is connected to the first potential. 38. A semiconductor device as claimed in any one of claims 31 to 37, characterized in that it is connected to a second potential such that a voltage is applied. 39. The method according to claim 30, wherein the first conductivity type is n-type and the second conductivity type is p-type.
39. The semiconductor device according to any one of 38. 40. A third resistor is provided between the gate of the first MOSFET and the gate terminal.
8. An insulated gate semiconductor device with a built-in control circuit according to any one of 7 above.