JPH09135024A - Insulated gate type semiconductor device incorporating control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-frequency operation of an insulated gate type semiconductor device which incorporates such a control circuit as an overheat protection circuit or an overcurrent protection circuit. SOLUTION: A MOS FET 22 is connected at its drain to a gate terminal 11, at its source to a gate 70 of a power MOS FET 13, and at its gate to a drain terminal 12 through a resistance 41. When it is desired to turn on the power MOS FET, that is, when the drain element is at high potential, a gate voltage of the MOS FET 22 is also at a high potential. Thus, application of the voltage to the gate terminal enables the power MOS FET to be turned on at a high speed. When it is desired to cut off the power MOS FET even at the high potential of the gate terminal, a MOS FET 23 is turned on to increase an on-resistance of the MOS FET 22. Thereby the power MOS FET can be cut off at a high speed even when the driving ability of a MOS FET 24 is low.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a power MOSF.
ET and IGBT (Insulated gate bipolar transistor)
In particular, the present invention relates to an insulated gate semiconductor device including a control circuit including a control circuit such as a negative gate voltage protection circuit and an overheat protection circuit on the same chip.

[0002]

2. Description of the Related Art Conventionally, as an insulated gate type semiconductor device having a built-in control circuit of this type, for example, in order to improve reliability, an overheat protection circuit or the like is provided on the same chip as disclosed in JP-A-7-58293. Power MOS with built-in control circuit
FETs are known. In this conventional example, a gate resistor is connected between the external gate terminal and the internal gate terminal, and a protection circuit MOSFET is connected between the internal gate terminal and the external source terminal. As a result, when the chip temperature rises above the specified temperature, the protection circuit MOS is
The FET can be turned on and a gate current can be passed through the resistor to shut off the power MOSFET before the power MOSFET is destroyed.

In this conventional example, the control circuit built in the same chip is constructed by using an element of a self-isolation type element isolation structure formed in the drain region of the power MOSFET in order to suppress an increase in process steps. There is. Therefore, although the cost is kept low, the parasitic npn transistor existing between the drain of the protection circuit MOSFET and the drain of the power MOSFET when the gate voltage becomes negative is changed from the external drain terminal to the external gate terminal. There is a possibility that a leak current will flow to. Therefore, as a countermeasure against this, a diode for cutting off the base current of the parasitic npn transistor is added to the protection circuit MOS.
A diode that is connected in series with the FET and that prevents the diode from breakdown is connected between the external gate terminal and the external source terminal.

A power MO having a built-in overheat protection circuit is provided.
An example in which a MOSFET is used instead of the above-mentioned gate resistor in order to increase the frequency of SFET is disclosed in Japanese Patent Laid-Open No. 6-24441.
No. 4 discloses this. In this conventional example, instead of using a gate resistor between the external gate terminal and the internal gate terminal, a MOSFET in which the body potential is fixed to the source terminal voltage is used.

[0005]

However, according to the former conventional example described above, even if an attempt is made to use a MOSFET instead of the gate resistance to increase the frequency as in the latter conventional example, it is necessary to increase the frequency. Since the source and drain of the MOSFET inserted between the internal gate terminal and the external gate terminal are not connected to the source terminal of the power MOSFET, the series circuit of the MOSFET and the diode for the gate cutoff circuit and the external gate terminal Depending on the diode provided between the external source terminal and the external source terminal, it is possible to prevent the parasitic npn transistor existing between the drain of the inserted MOSFET and the drain of the power MOSFET from operating when the gate voltage becomes negative. I couldn't.

Further, as in the latter conventional example in which the frequency is increased, a MOSF is formed in the substrate instead of the gate resistor.
When ET is used, the threshold value becomes high due to the substrate bias effect, and the MOSFET used instead of the gate resistance.
However, there was a problem that the on-resistance of was not lowered and it was not possible to achieve high frequency. The MOS instead of the gate resistor
When a polycrystalline silicon MOSFET formed on a substrate so as not to be influenced by the substrate bias is used for the FET, the carrier resistance in the polycrystalline silicon is low, and therefore the ON resistance does not become so low. Therefore, it is difficult to increase the frequency.

Therefore, an object of the present invention is to provide an insulated gate semiconductor device with a built-in control circuit, which is capable of reducing the on-resistance of a MOSFET used in place of the above-mentioned gate resistance and increasing the frequency. Further, another object of the present invention is that both the source and the drain of the control circuit MOSFET have the power MO.
It is an object of the present invention to provide an insulated gate semiconductor device with a built-in control circuit, which has a negative gate voltage protection in which the parasitic npn transistor operation does not matter even when it is not connected to the source terminal of the SFET.

[0008]

In order to achieve the above object, an insulated gate semiconductor device with a built-in control circuit according to the present invention has a drain terminal 12, a gate terminal 11 and a source terminal 10 as shown in FIG. A power MOSFET 13 having at least a drain connected to a drain terminal and a source connected to a source terminal; a first MOSFET 22 having a drain and a source connected between a gate and a gate terminal of the power MOSFET; and a source as a source. A second MOSFET 23 connected to the terminal and having a drain connected to the gate of the first MOSFET; and a drain terminal and the first MOS
At least the first resistor 41 connected between the gate of the FET and the first resistor 41.

In this case, the first diode 51 is provided between the gate and the source terminal 10 of the first MOSFET 22.
May be further provided. Further, as shown in FIG. 3, a second diode 62 may be further provided between the gate of the first MOSFET 22 and the gate 70 of the power MOSFET.

As shown in FIG. 1, a third MOSFET 24 having a drain connected to the gate 70 of the power MOSFET and a source connected to the source terminal 10 may be further provided. Furthermore, a third diode 52 can be provided between the gate of the second MOSFET 23 and the gate terminal 11.

Further, as shown in FIG. 4, the first MO
A second resistor 48 may be further provided between the gate of the SFET 22 and the gate terminal 11. Furthermore, the first M
A fourth gate is provided between the gate of the OSFET 22 and the gate terminal 11.
The diode 59 can be provided. Further, a fifth diode 58 may be further provided between the gate of the first MOSFET 22 and the drain terminal 12. Furthermore,
Gate of the first MOSFET 22 and power MOSF
It is preferable to provide the capacitor 69 with the gate 70 of the ET.

Further, as shown in FIG. 1, the power MO
It is preferable to further provide the third resistor 42 between the gate 70 of the SFET and the gate terminal 11. Furthermore, a fourth M having a drain and a gate connected to the gate 70 of the power MOSFET and a source connected to the gate terminal 11.
The OSFET 30 may be further provided.

Further, as shown in FIG. 7, a sense power MOSFET 21 having a drain and a gate connected to the drain and gate of the power MOSFET, respectively, and a current detecting element between the source and the source terminal 10 of the sense power MOSFET. 46 and the drain to the first MOSF
It is preferable to further provide a fifth MOSFET 31 which is connected to the gate 71 of the ET 22 and whose source is connected to the source terminal and whose gate input is the detection voltage of the current detection element.

Alternatively, a sense power MOSFET 21 having a drain and a gate connected to the drain and gate of the power MOSFET, respectively, and the sense power MOS
Between the source of the FET and the source terminal 10, a current detecting element 4
6 may be provided and the current detection node 76 of this current detection element may be connected to the gate of the second MOSFET 23. still,
In this configuration, a fifth MOS having the same function as the second MOSFET 23 with respect to the gate of the first MOSFET 22 is provided.
It is replaced with the FET 31 and is shown in FIG.

Further, as shown in FIG. 7, a fourth resistor 45 connected between the gate terminal 11 and the source terminal 10 is provided.
And a sixth diode 53 in series, and when the voltage between the anode and the cathode of the sixth diode 53 becomes small, the second MOSFET (or the fifth MO) is formed.
It is preferable to configure the gate potential of the SFET) to be high.

Further, as shown in FIG. 8, a sixth MOSFET 28 having a gate connected to the gate terminal 11, a drain connected to the source terminal 10, and a source and a body connected to the body of the first MOSFET 22 is provided. It is preferable if it is. In this case, connect the gate to the source terminal 10,
A seventh MOSFET 27 having a drain connected to the gate terminal 11 and a source and a body connected to the body of the first MOSFET 22 may be further provided.

The insulated gate semiconductor device with a built-in control circuit according to the present invention, as shown in FIG.
The p-type well regions 104a and 104b are provided in the n-type drain region 102 of the ET 13, and the p-type well region 104 is formed.
An n-type diffusion layer 109b is provided in each of a and 104b, the p-type well regions 104a and 104b are used as a body region of the first MOSFET 22, and the n-type diffusion layer 109b is formed as a first MOSF.
It is characterized in that it is used as a source and a drain of ET22.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of an insulated gate type semiconductor device with a built-in control circuit according to the present invention is applied to a power MOSFET as an insulated gate type semiconductor element, and a drain terminal, a gate terminal and a source terminal. A power MOSFET having at least a drain connected to a drain terminal and a source connected to a source terminal; a first MOSFET having a drain and a source connected between a gate and a gate terminal of the power MOSFET; and a source as a source. A second MOSFET connected to the terminal and a drain connected to the gate of the first MOSFET;
And a first resistor connected between the MOSFET and the gate of the MOSFET.

By the way, a lateral MOSF for controlling the power MOSFET in the drain region of the n-type power MOSFET.
In an insulated gate semiconductor device with a built-in control circuit having a self-isolation type element isolation structure forming ET, a gate terminal and a power MO are provided.
First MOSFET connected between the gate of SFET
In addition to using only n-type devices for this MOSFET,
However, since a substrate bias is applied, it is difficult to reduce the on-resistance, and it is difficult to drive at high speed.

On the other hand, in the semiconductor device of this embodiment, the first MOSFET is provided between the drain terminal and the first MOSFET in order to increase the gate voltage of the first MOSFET.
When the power MOSFET is turned on, that is, when the drain terminal is high,
Since the MOSFET of can be turned on, the power MOS can be operated at high speed when a voltage is applied to the gate terminal.
The FET can be turned on.

When the voltage is applied to the gate terminal, the power MOSFET is forcibly cut off by a signal from another cutoff terminal or a signal for overcurrent protection or overheat protection. Lowers the gate voltage to increase the on-resistance and lowers the gate of the power MOSFET. As a result, the power MOSFET can be cut off at high speed even if the current driving capability of the MOSFET required to cut off the power MOSFET is small. It is also possible to reduce the current flowing through the gate in the cutoff state.

Further, the gate terminal and the first MOSF
When a second resistor and a fourth diode are connected between the gate of ET and a fifth diode is connected in series with the first resistor between the drain terminal and the gate of the first MOSFET. Enables the gate voltage of the first MOSFET to be increased even when the gate terminal has a high potential and the drain terminal has a low potential, and the leakage current from the gate terminal to the drain terminal can be blocked by the fifth diode. When the terminal has a low potential and the drain terminal has a high potential, the fourth diode can prevent a leak current from the drain terminal to the gate terminal.

If a first diode is connected between the gate and the source terminal of the first MOSFET for gate protection of the first MOSFET, within the withstand voltage range of the first diode. A leak current from the drain terminal to the source terminal can be prevented, and even if a voltage higher than the withstand voltage of the first diode is applied to the drain terminal, the first MOSFET is not destroyed and flows from the drain terminal to the source terminal. The breakdown current can be suppressed to a negligible range by increasing the value of the first resistor.

Further, a seventh MOSFE in which the gate is connected to the source terminal, the drain is connected to the gate terminal, and the source and body are connected to the body of the first MOSFET.
When T is provided, even if a negative gate voltage lower than the source terminal voltage is applied to the gate terminal, the first MO
The parasitic npn transistor existing in the SFET is not forward-biased between the emitter and the base. In addition, a sixth connecting the gate to the gate terminal, the drain to the source terminal, and the source and body to the virtual ground of the control circuit section.
If the MOSFET of the
The base current of the parasitic npn transistor existing in the FET can be cut off. Therefore, it is possible to prevent a leak current flowing from the drain terminal to the gate terminal when the parasitic npn transistor is turned on, and it is also possible to prevent device breakdown in the parasitic npn transistor portion.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A more specific embodiment of an insulated gate semiconductor device having a control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing a first embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. In FIG. 1, reference numeral 82 indicates a power MOSFET with a built-in control circuit according to the present invention. The power MOSFET 82 with a built-in control circuit is the power MOSFET 13.
The gate cutoff circuit 14 including the MOSFETs 22 to 24, the MOSFET 30, the resistors 41, 42 and 47, and the diodes 51 and 52, and the gate protection circuit 15 including the diodes 56 and 57 are built in the same semiconductor chip. Further, a battery 80 and a load 81 are connected between the drain terminal 12 and the source terminal 10 of the power MOSFET 82 with a built-in control circuit. Power MO with built-in control circuit
The SFET 82 has a drain terminal 12, a gate terminal 11 and a source terminal 10 like a normal power MOSFET, and also has a cutoff terminal 18 for cutting off the power MOSFET 13 regardless of the voltage of the gate terminal 11.

The drain of the power MOSFET 13 is connected to the drain terminal 12, and the source is the source terminal 1.
0, the drain and source of the MOSFET 22 are connected between the gate 70 and the gate terminal 11 of the power MOSFET, and the gate of the MOSFET 22 has a resistor 4
It is connected to the drain terminal 12 via 1 and to the cathode of the diode 51. Diode 51
The anode of is connected to the source terminal 10. Further, the gate 70 and the gate terminal 11 of the power MOSFET
A resistor 42 is connected between and. Also, MOSFET
The drain and gate of 30 are connected to the gate 70 of the power MOSFET, and the source of the MOSFET 30 is connected to the gate terminal 11. The source of the MOSFET 23 is connected to the source terminal 10, and the drain is the MOSFET 2
The second gate 71 is connected to the cutoff terminal 18 via the resistor 47 and the drain of the MOSFET 22 via the diode 52. MO
The source of the SFET 24 is connected to the source terminal 10, the drain is connected to the gate 70 of the power MOSFET 12, and the gate is connected to the cutoff terminal 18 via the resistor 47.

In the power MOSFET 82 with a built-in control circuit constructed as above, the voltage of the battery 80 is applied to the gate 71 of the MOSFET 22 through the resistor 41 even when the power MOSFET 13 is in the cutoff state.
The MOSFET 22 is on. Therefore, when a positive voltage is applied to the gate terminal 11, the power MOSFET
13 is turned on at high speed. On the other hand, when the cutoff terminal 18 is set to a high potential while the positive voltage is applied to the gate terminal 11, the MOSFET 23 is turned on, so that the MOSFET 2
The gate voltage of 2 decreases and the ON resistance of the MOSFET 22 increases. Therefore, from the gate terminal 11 to the MOSFET
Since the current flowing through 22 decreases and the rate of discharging the gate charge of the power MOSFET 13 increases accordingly, the power MOSFET 13 can be cut off at high speed even if the current driving capability of the MOSFET 24 is low. Further, at this time, the gate current flowing from the gate terminal 11 through the MOSFET 24 to the source terminal 10 can be reduced.

When the potential of the gate terminal 11 is lowered, the resistance 42
The gate charge is discharged through the power MOSFET 13
Shuts off. In this embodiment, the MOSFET 30 having the drain and the gate connected to the gate 70 of the power MOSFET 13 and the source connected to the gate terminal 11 is provided. Therefore, when the potential of the gate terminal 11 is lowered, the MOSFET 3
Even through 0, the gate charge is discharged. Therefore, the power MOSFET 13 can be cut off at high speed. The resistance 42
Is the gate 70 and the gate terminal 1 of the power MOSFET 13.
Since the gate terminal 11 is connected between the two terminals, even if the initial voltage of the drain terminal 12 is low,
SFET13 can be turned on and MOS
Even if the threshold voltage of the FET 22 is high, in terms of DC (direct current), the voltage of the gate terminal 11 and the gate 7 of the power MOSFET are
The zero voltage can be made equal. Therefore, there is an effect that the substantial on-resistance of the power MOSFET can be reduced.

In addition, the gate terminal 11 and the MOSFET 23
Since the diode 52 is connected between the gate and
When the potential of the gate terminal 11 is lowered, the MOSFET 23 shuts off. As a result, from the drain terminal 12 to the MOSF
A leak current can be prevented from flowing to the source terminal 10 through the ET 23.

In this embodiment, the gate protection diode 51 is provided between the gate of the MOSFET 22 and the source terminal 10 so that the gates of the MOSFETs 22, 23 and 24 are not destroyed even if the voltage of the drain terminal 12 rises.
Therefore, a voltage higher than the withstand voltage (for example, 20 V) of the diode 51 can be applied to the drain terminal 12. Since the breakdown current of the diode 51 is suppressed sufficiently low by the resistor 41, the substantial drain breakdown voltage is the power MOS.
It can be regarded as equivalent to the drain breakdown voltage of the FET 13. In addition, the resistor 47 is cut off from the shutoff terminal 18
Since the gate terminals are connected between the gates, even if the gate terminal 11 has a low potential when the cutoff terminal 18 has a high potential, it is possible to prevent a large current from flowing from the cutoff terminal 18 to the gate terminal 11. The diode 56 and the diode 57 are gate protection diodes for the power MOSFET 13 and the MOSFETs 23 and 24, respectively.

Although all the diodes 51, 52, 56 and 57 shown in this embodiment are connected in only one stage, they are connected in multiple stages when high breakdown voltage is required. It is also possible. The same applies to the diodes used in the circuits of Example 3 and the following shown below.

FIG. 2 is a sectional view showing a main part structure of a semiconductor device which constitutes the power MOSFET 82 with a built-in control circuit shown in FIG. This semiconductor device is a conventional vertical power M
It can be formed by a process similar to that of OSFET. In FIG. 2, reference numeral 101 is a high concentration n having a resistivity of about 0.02 to 0.002 Ω · cm using antimony or arsenic as an impurity.
1 shows a semiconductor substrate, and an n-type epitaxial layer 102 having a resistivity of about 1 to 2 Ω · cm is formed on the semiconductor substrate 101.
The thickness is about 0 μm.

In the power MOSFET formation portion, a depth of 6 μm is provided between the patterns of the polycrystalline silicon gate layer 106a formed on the gate oxide film 105a having a thickness of about 50 nm.
The first p-type well diffusion layer 103a having a dose amount of about 1 × 10 ¹⁵ cm ⁻² and the polycrystalline silicon gate layer 106a are used as a mask to form a self-aligned depth of 2 μm, and the dose amount is 5
× 10 ¹³ and cm ^-2 order of p-type diffusion layer 107 for the body, depth 0.4 .mu.m, a dose of 1 × 10 ¹⁶ cm ^-2 order of the source n-type diffusion layer 109a is provided, further body and the aluminum electrode 112a For deep ohmic contact between 0.5 μm and a dose of 1 × 10 ¹⁵ cm ^-2.
The type diffusion layer 110a is provided, and the polycrystalline silicon gate layer 10 is provided.
An aluminum electrode layer 112a serving as a source electrode is provided on 6a via an insulating layer 111.

In the protection circuit portion, the second p-type well diffusion layer 10 having a depth of 5 μm and a dose amount of about 2 × 10 ¹³ cm ⁻² is formed.
4a and 104b as bodies, and the n-type diffusion layer 109a
The high-concentration n-type diffusion layer 109b formed in the same step as above is used as a drain diffusion layer and a source diffusion layer, and the high-concentration p-type diffusion layer 110b formed in the same step as the high-concentration p-type diffusion layer 110a is replaced with the body 104a. , 104b and the aluminum electrodes 112b to 112e are used as high-concentration p-type diffusion layers for forming ohmic contact, and the polycrystalline silicon gate layer 106b formed in the same step as the polycrystalline silicon gate layer 106a is used as a protection circuit MOSFET. And a dose amount of 5 × 10 ¹² cm for improving the drain withstand voltage around the drain diffusion layer of the high-concentration n-type diffusion layer 109b.
MOS with low concentration n-type offset region 108 of about ^-2
FET is provided. In addition, the bodies 104a and 104b
The p-type well diffusion layer 1 formed in the same step as the first p-type well diffusion layer 103a is formed in the vicinity of the above in order to improve the breakdown voltage.
03b and 103c are provided. Incidentally, reference numeral 105b
Is a field oxide film.

In FIG. 2, a part of the power MOSFET 13 and n which is a drain region of the power MOSFET 13 are shown.
MOS FET for control circuit in the epitaxial layer 102
As an example of T, the MOSFETs 22 and 23 shown in FIG. 1 are shown. By thus providing the control circuit MOSFET in the drain region of the power MOSFET 13, there is an advantage that the control circuit can be built in at a low cost as in the conventional power MOSFET process. Each diode may be configured using a diffusion layer,
Regarding the diode 52 in which the potentials at both ends fluctuate together,
The use of a polycrystalline silicon diode is preferable because the generation of parasitic transistors can be prevented. Needless to say, a polycrystalline silicon diode may be used for other diodes.

Further, the MOSFET 2 provided for speeding up
2 has a problem that the effective on-resistance decreases when the voltage of the gate terminal 11 increases due to the substrate bias effect. However, as described in FIG. 1, when the MOSFET 22 has a low on-resistance, the gate voltage of the MOSFET 22 is the drain terminal. Since it increases as the voltage of 12 increases, the on-resistance can be reduced. In addition, the MOSFE of FIG.
In order to further reduce the on-resistance of T22 and T30, it is advisable to add an n-type ion implantation step of forming an n-type layer directly under the gates of these MOSFETs to make it a depletion type.

In this embodiment, the bodies 104a and 103b of the MOSFET 22, the bodies 104b and 103c of the MOSFET 23, and the bodies 107 and 103a of the power MOSFET 13 are separated by the drain region 102 of the power MOSFET 13. However, in the case of the circuit configuration shown in FIG. 1, all the body diffusion layers may be connected.

In this embodiment, an insulated gate semiconductor device with a built-in control circuit using the power MOSFET 13 has been described as an example. However, instead of the power MOSFET 13, an IGBT is used.
Even if T is used, the same action and effect can be obtained. In that case,
The collector of the IGBT is connected to the drain terminal 12 of FIG. 1, the gate of the IGBT is connected to the gate 70 of the power MOSFET 13, and the emitter of the IGBT is connected to the source terminal 10.
You can connect to.

IGB instead of power MOSFET 13
When T is used, it is only necessary to replace the high concentration n-type semiconductor substrate 101 with the high concentration p-type semiconductor substrate in FIG. Further, in this case, in order to limit the injection of minority carriers from the high concentration p-type semiconductor substrate between the high concentration p-type semiconductor substrate and the n-type epitaxial layer 102, a so-called higher concentration of so-called n-type epitaxial layer 102 is required. An n-type buffer layer may be provided if necessary. In the case of replacing with the IGBT, in FIG.
a is the emitter electrode of the IGBT, the polycrystalline silicon gate layer 106a is the gate layer of the IGBT, and the high-concentration p-type semiconductor substrate is the collector of the IGBT.

Hereinafter, power MOSFETs will be used in other embodiments as well.
However, it goes without saying that the control circuit built-in IGBT can be realized by performing the same replacement as described above.

<Embodiment 2> FIG. 3 is a circuit diagram showing a second embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, the first embodiment in FIG.
The same parts as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the first embodiment, the MOSFET 23 and the MOSFET 24 are used for shutting off the power MOSFET 13, but in the present embodiment, only the MOSFET 23 is used and the MOS is used.
It differs from the configuration of FIG. 1 in that the diode 62 is connected between the gate 70 of the power MOSFET 13 and the gate 71 of the MOSFET 22 instead of using the FET 24. The diode 62 is connected to the source of the MOSFET 22 and the power MOSFE from the drain terminal 12 via the resistor 41.
It is provided to prevent current from flowing to the gate 70 of T and the gate terminal 11 and to reduce the voltage of the gate 70 of the power MOSFET when the MOSFET 23 is turned on. Even with such a configuration, the effect of increasing the frequency obtained by the circuit configuration of this embodiment is almost the same as that of the embodiment shown in FIG.

The power MOS with a built-in control circuit of this embodiment is used.
The cross-sectional structure of the FET can be realized by the same structure as that of the first embodiment shown in FIG. Further, as in the case of the first embodiment, the body regions of the MOSFETs 22, 23, etc. have power M.
It is possible to connect to the body region of the OSFET 13.

<Embodiment 3> FIG. 4 is a circuit diagram showing a third embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, the first embodiment in FIG.
The same parts as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the series circuit of the diode 59 and the resistor 48 is provided between the gate terminal 11 and the gate 71 of the MOSFET 22, the capacitor 69 is provided between the gate and the source of the MOSFET 22, and the MOSFET.
It differs from the first embodiment in that a diode 58 connected in series with a resistor 41 is provided between the gate of 22 and the drain terminal 12.

With this configuration, even if the voltage of the drain terminal 12 is low and the voltage of the gate terminal 11 is high, the MOSFE is connected via the diode 59 and the resistor 48.
Since the gate voltage applied to T22 is also high, the MOS
The FET 22 has a low on resistance. Therefore, the power MOSFET 13 can be turned on at high speed. Further, by providing the diode 59, even if the drain terminal 12 has a higher potential than the gate terminal 11, a leak current from the drain terminal 12 to the gate terminal 11 can be prevented. Further, the diode 58 is connected to the drain terminal 12 and the MO.
By connecting between the gate 71 of the SFET 22 and the gate terminal 11, the leak current flowing from the gate terminal 11 to the drain terminal 12 can be prevented when the gate terminal 11 has a high potential.
Since the capacitor 69 constitutes a bootstrap circuit together with the diode 59, there is an effect that the rising speed of the gate voltage of the MOSFET 22 can be improved when the gate terminal 11 has a high potential. The other actions and effects obtained by the circuit configuration of this embodiment are almost the same as those of the first embodiment shown in FIG.

The sectional structure of the semiconductor device of this embodiment can be realized by the same structure as that of the first embodiment shown in FIG. Further, as in the case of the first embodiment, the MOSFET 2
The body regions such as 2, 23 can be connected to the body regions of the power MOSFET 13.

<Fourth Embodiment> FIG. 5 is a circuit diagram showing a fourth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. Note that, for convenience of explanation, in FIG.
The same parts as those shown in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, the diodes 51, 52 shown in FIG.
56, 57, 58 and 59 are diode-connected M
It is different from the third embodiment in that the OSFETs 33, 34, 35, 36, 37, 38 are replaced.

As described above, when the MOSFETs are diode-connected and used, the current capacity can be increased as compared with the case where a polycrystalline silicon diode is used as the diode, so that the element area can be reduced. The other actions and effects obtained by this embodiment are almost the same as those of the third embodiment shown in FIG.

The cross-sectional structure of the semiconductor device of this embodiment can also be realized by the structure shown in FIG. Also, as in the case of the first embodiment, the body regions of the MOSFETs 22 and 23 can be connected to the body regions of the power MOSFET 13.

<Fifth Embodiment> FIG. 6 is a circuit diagram showing a fifth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, the first embodiment in FIG.
The same parts as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the case of the present embodiment, the point that the overcurrent limiting circuit 17 is provided, the point that the gate protection circuit 15 is composed only of the diode 56 because the shutoff terminal 18 is not provided, and the gate shutoff circuit 14 is The constituent MOSFET 23,
24 and resistor 47 are omitted, and power MOS
Main power M with common drain and gate for FET13
It is different from the first embodiment in that it is divided into an OSFET 20 and a sense power MOSFET 21, and a resistor 46 is connected as a current detection element to the source (current detection node 76) of the sense power MOSFET 21. Here, the overcurrent limiting circuit 17 includes a MOSFET 31 whose gate is connected to the current detection node 76, whose source is connected to the source terminal 10 and whose drain is connected to the gate 71 of the MOSFET 22, and whose gate is connected to the current detection node 76 and whose source is the source. It is composed of a MOSFET 32 connected to the terminal 10 and having a drain connected to the gate 70 of the power MOSFET 13, and a resistor 46 connected between the current detection node 76 and the source terminal 10.

With this configuration, when an overcurrent flows through the main power MOSFET 20, a current proportional to the main power MOSFET 20 also flows through the sense power MOSFET 21, and the voltage at the current detection node 76 rises. If the voltage of the current detection node 76 is MOSFET 31,
When the voltage rises above the threshold voltage of 32, MOSFET3
1, 32 are turned on to lower the gate voltage of the power MOSFET 13 and limit the drain current of the power MOSFET 13.

In this embodiment, the current detection node 76 functions as the cutoff terminal 18 of FIG.
32 functions as the MOSFETs 23 and 24 in FIG. Further, a diode having the same function as the diode 52 of FIG. 4 is provided between the gate terminal 11 and the gate of the MOSFET 31,
When the potential of the gate terminal 11 drops, the MOSFET 3
1 may be cut off to prevent a leak current between the drain terminal and the source terminal, but in the case of the present embodiment, since there is the resistor 46, the current flows when the gate terminal 11 becomes a low potential. Since the detection node 76 also has a voltage of zero volt, FIG.
There may be no diode corresponding to the diode 52 of FIG.

In this embodiment, the power MOSFET 13 is the main power MOSFET 20 and the sense power MOSFET.
The reason for dividing into 21 is to reduce the loss for current detection. Therefore, the power MOSFET 13
When the loss in the resistor 46 is negligible as in the case of BT, the power MOSFET 13 need not be divided. That is, the power MO in which the sources of the sense power MOSFET 21 and the main power MOSFET 20 are also connected to each other.
A resistor 4 is provided between the source of the SFET 13 and the source terminal 10.
6 should be connected. Further, the resistor 46 may be externally attached in order to improve the current detection accuracy. The other actions and effects obtained by this embodiment are almost the same as those of the third embodiment shown in FIG.

Although the MOSFET 23 is not used in this embodiment, the corresponding structure is the MOSFET 31, so that the sectional structure of the semiconductor device of this embodiment can be realized by the structure shown in FIG. Further, as in the case of the first embodiment, the body regions of the MOSFETs 22 and 31 and the like have power MO.
It is possible to connect with the body region of the SFET.

<Embodiment 6> FIG. 7 is a circuit diagram showing a sixth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. In addition, for convenience of explanation, in FIG.
The same parts as those shown in FIG. 6 are designated by the same reference numerals and detailed description thereof will be omitted. That is, in the case of this embodiment, the overcurrent limiting circuit 1 shown in FIG.
7, a temperature detection circuit 16 for overheat protection is built in, and a MOSFET is provided in the gate cutoff circuit 14.
23 and 24 is different from the fifth embodiment. Here, the temperature detection circuit 16 includes a gate terminal 11 and a source terminal 1.
A series circuit of a resistor 46 and a diode 54 provided between 0,
A MOSFET 29 whose drain is connected to the node 74 through the resistor 43, whose gate is connected to the node 74 through the resistor 45, and whose source is connected to the source terminal 10;
It is composed of a gate 73 of the OSFET 29 and a diode 53 connected between the source terminals 10.

The semiconductor device of the present embodiment having the above-mentioned overheat protection function operates in the following manner.
The series circuit of the resistor 46 and the diode 54 constitutes a constant voltage circuit, and a constant voltage substantially determined by the breakdown voltage of the diode 54 is generated at the node 74. Since the voltage drop amount of the diode 53 decreases with an increase in temperature, the voltage of the gate 73 of the MOSFET 29 connecting the resistor 45 and the diode 53 decreases with an increase in temperature. This voltage is MOSFET
When the voltage drops below the threshold voltage of 29, the MOSFET 29 is cut off, and the gates of the MOSFETs 23 and 24 have resistors 46 and 4 respectively.
Since the voltage of the gate terminal 11 is applied via
The OSFETs 23 and 24 are turned on to increase the on resistance of the MOSFET 22 and cut off the power MOSFET 13. That is, the drain 72 of the MOSFET 29 also functions as the cutoff terminal 18 in FIG. This provides overheat protection. The other actions and effects obtained by the circuit configuration of the present embodiment are almost the same as those of the fifth embodiment shown in FIG.

The sectional structure of the semiconductor device of this embodiment can also be realized by the structure shown in FIG. Also, as in the case of the first embodiment, the body regions of the MOSFETs 22 and 23 can be connected to the body regions of the power MOSFET 13.

<Embodiment 7> FIG. 8 is a circuit diagram showing a seventh embodiment of an insulated gate semiconductor device having a control circuit according to the present invention. For convenience of explanation, in FIG.
7, the same parts as those shown in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, the gate protection circuit 1 has a built-in negative gate voltage protection function capable of applying a voltage (negative gate voltage) lower than that of the source terminal 10 to the gate terminal 11.
5, a diode 61, a resistor 48, MOSFETs 27 and 2
8 is added, the MOSFET of the temperature detection circuit 16
The body and source of 29 and the diode 53 are separated from the source terminal 10 and connected to the node 75 of the gate protection circuit which is a virtual ground, and the gate cutoff circuit 1.
This is different from the sixth embodiment in that the bodies and sources of the MOSFETs 23 and 24 of No. 4 are separated from the source terminal 10 and connected to the node 75 of the gate protection circuit.

As is apparent from FIG. 2, in this semiconductor device, the high-concentration n-type diffusion layer 109b that is the drain or source of the MOSFETs 22 and 23 for the control circuit is used as the emitter, and the p-type well diffusion that is the body of the MOSFETs 22 and 23 is used. Power MOS based on layers 104a and 104b
N-type epitaxial layer 10 which is the drain of the FET 13
There is a parasitic npn transistor whose collector is 2. Therefore, when a negative gate voltage, that is, a voltage lower than that of the source terminal 10, is applied to the gate terminal 11, the parasitic npn transistor may turn on and a leak current may flow from the drain terminal 12 to the gate terminal 11. Further, in this case, when a high voltage is further applied to the drain terminal 12, there is a possibility that the parasitic npn transistor may be permanently destroyed.

In the case of this embodiment, the MOSFET 22,
The gate is connected to the source terminal 10, the drain is connected to the gate terminal 11, and the source and the body are the body of the MOSFET 22 and the MOSFET 30 so that the emitter-base of the parasitic npn transistors existing at 30, 23, 24 and 29 are not forward biased. MOSFET 27 connected to
Is provided. In addition, MOSFETs 22, 30, 23,
In order to prevent the base current of the parasitic npn transistor existing in 24 and 29, the gate is connected to the gate terminal 11, the drain is connected to the source terminal 10, and the source and the body are connected to the bodies of the MOSFETs 22, 30, 23, 24 and 29. A connected MOSFET 28 is provided. In this embodiment, in order to avoid the accuracy deterioration of the overcurrent limiting circuit 17 due to the potential difference between the node 75 and the source terminal 10, M
The sources of the OSFET 31 and the MOSFET 32 are the node 7
Instead of connecting to 5, the source terminal 10 was connected.

Further, MOSFET 31 and MOSFET 3
The parasitic npn transistor existing in No. 2 is disclosed in JP-A-7-5.
As disclosed in Japanese Patent No. 8293, parasitic npn transistor operation is blocked by diodes 55 and 59, respectively. Here, the breakdown voltage of the diode 61 is set lower than the breakdown voltage of the diode 55 or the diode 59.
Specifically, the breakdown voltage of the diode 61 is about 4V or less, while the breakdown voltage of the diodes 55 and 59 is about 7V or more. Therefore, even if a negative gate voltage is applied, the gate-source voltage is clamped at -4V, so that it is possible to prevent the parasitic npn transistor from operating due to breakdown of the diodes 55 and 59. The diode 55 may be omitted when the bodies and sources of the MOSFETs 31 and 32 are connected to the node 75.

Further, the protection of the negative gate voltage by the MOSFET 27 is necessary when the falling speed of the gate terminal 11 is fast, but in the case of a sufficiently slow change, MOSFE is used.
Negative gate voltage protection can be achieved with T28 alone.

Although the resistor 48 is not always necessary, it is provided for the following reason. When a voltage is applied to the gate terminal 11 to turn on the power MOSFET 13, the substrate potential of the MOSFET 22 which is not grounded due to the parasitic capacitance due to elements and wiring existing between the node 75 and the gate terminal 11 It rises temporarily. In this embodiment, while the time defined by the RC time constant of the resistor 48 and the parasitic capacitance is added to the time until the MOSFET 28 turns on and the node 75 reaches the potential of the source terminal, this temporarily raised substrate potential is Since it suppresses the rapid decrease, when turning on the power MOSFET, the MOS
MOS is used to reduce the effect of the substrate bias of the FET 22.
The ON resistance of the FET 22 becomes low. Therefore, the switching speed can be further increased as compared with the case without the resistor 48. MOSFET when the gate terminal 11 is set to low potential
The diode 52 for turning off 23 is composed of resistors 43, 4
In the case of the present embodiment, there is no need for it because there is 6.

In this embodiment, the diode 54 for the constant voltage circuit
And the gate protection diode 51 are connected to the virtual ground terminal 7
It was connected to the source terminal 10 instead of 5. As a result, when the diode 54 or the diode 51 breaks down, M
It is possible to prevent the virtual ground terminal 75 from becoming higher than the source terminal 10 due to insufficient current driving capability of the OSFET 28. Other functions and effects obtained by the present semiconductor device are almost the same as those of the sixth embodiment shown in FIG. In addition,
The negative gate voltage protection function as described above is required when the semiconductor device is used in the source follower circuit.

The cross-sectional structure of the semiconductor device of this embodiment can also be realized by the structure shown in FIG. In the case of the present embodiment, the MOSFET 22 and the MOSFET are
It is necessary to separate 23 and the power MOSFET 13. Therefore, as shown in FIG. 2, the body region of each MOSFET needs to be separated by the drain region 102 of the power MOSFET 13.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments.
For example, although all MOSFETs including power MOSFETs have been described as n-channel MOSFETs in the above-described embodiments, similar effects can be obtained even if all the elements are p-channel MOSFETs, and various elements can be used without departing from the spirit of the present invention. It goes without saying that the design can be changed.

In the above-described embodiments, the power MOS is used.
An insulated gate semiconductor device with a built-in control circuit using an FET has been described as an example, but the same can be applied to the case of an IGBT with a built-in control circuit that uses an IGBT instead of a power MOSFET.

[0068]

As is apparent from the above-described embodiments, according to the present invention, in the power MOSFET with a built-in control circuit using the conventional power MOSFET process, the power M
MOSFET for control circuit connected to the gate of OSFET
With the configuration in which the gate charge is fed from the drain terminal, it is possible to easily reduce the on-resistance of the control MOSFET. Therefore, the power M with a built-in control circuit
There is an effect that the frequency of the OSFET can be increased. Furthermore, by adding a MOSFET for controlling the body potential of the control circuit MOSFET, a power MOSF
The operation of the parasitic npn transistor existing in the control circuit MOSFET connected to the gate of ET can be prevented. Therefore, even when a negative gate voltage is applied to the gate of the power MOSFET with a built-in control circuit, there is an effect that the leak current flowing from the drain terminal to the gate terminal can be prevented and the element can be further prevented from being destroyed.

When applied to a control circuit built-in IGBT, there is a difference that a parasitic thyristor is generated instead of a parasitic npn transistor. However, according to the present invention, high frequency and negative gate voltage protection of the control circuit built-in IGBT are achieved. The effect is that it can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an insulated gate semiconductor device with a built-in control circuit according to the present invention.

FIG. 2 is a cross-sectional view showing a structure of a main part of a semiconductor device having the circuit configuration shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of an insulated gate semiconductor device with a built-in control circuit according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of an insulated gate semiconductor device having a control circuit according to the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of an insulated gate semiconductor device with a built-in control circuit according to the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention.

FIG. 7 is a circuit diagram showing a sixth embodiment of an insulated gate semiconductor device having a control circuit according to the present invention.

FIG. 8 is a circuit diagram showing a seventh embodiment of an insulated gate semiconductor device with a built-in control circuit according to the present invention.

[Explanation of symbols]

10 ... Source terminal, 11 ... Gate terminal, 12 ... Drain terminal, 13 ... Power MOSFET, 14 ... Gate cutoff circuit, 15 ... Gate protection circuit, 16 ... Temperature detection circuit, 17
... Overcurrent limiting circuit, 18 ... Cutoff terminal, 20 ... Main power MOSFET, 21 ... Sense power MOSFET, 2
2 to 38 ... MOSFET, 41 to 48 ... Resistance, 51 to 6
2 ... Diode, 69 ... Capacitor, 70 ... Power MO
SFET 13 gate, 71 ... MOSFET 22 gate, 72 ... MOSFET 23 gate, 73 ... MOSF
ET23 gate, 74 ... Constant voltage node, 75 ... Node (virtual ground), 76 ... Current detection node, 80 ... Battery, 81 ... Load, 82 ... Control circuit built-in power MOSF
ET, 101 ... N-type substrate, 102 ... N-type epitaxial layer, 103a, 103b ... First p-type well layer, 104
a, 104b ... Second p-type well layer, 105a, 105
b ... Oxide film, 106a, 106b ... Polycrystalline silicon gate layer, 107, 109a, 109b ... P-type diffusion layer, 10
8 ... Low-concentration n-type diffusion layer, 110a, 110b ... N-type diffusion layer, 111 ... Insulating film (protective film), 112a to 112e ...
n-type diffusion layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Yoshida 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Hideki Tsunoda 5 Mizumizumoto-cho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Super LSI Engineering Co., Ltd.

Claims (17)

[Claims] 1. A power MOSFET having at least a drain terminal, a gate terminal and a source terminal, a drain connected to the drain terminal and a source connected to the source terminal, and a drain between the gate and the gate terminal of the power MOSFET. A first MOSFET having a source connected, and a source having a source connected to a source terminal and a drain having a first MOSF.
An insulated gate semiconductor with a built-in control circuit, comprising at least a second MOSFET connected to the gate of ET and a first resistor connected between the drain terminal and the gate of the first MOSFET. apparatus. 2. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a first diode provided between the gate and the source terminal of the first MOSFET. 3. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a second diode provided between the gate of the first MOSFET and the gate of the power MOSFET. 4. A third MO having a drain connected to the gate of the power MOSFET and a source connected to the source terminal.
The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising an SFET. 5. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a third diode provided between the gate and the gate terminal of the second MOSFET. 6. A first resistor is further provided between the gate and the gate terminal of the first MOSFET.
An insulated gate semiconductor device with a built-in control circuit according to any one of 1. 7. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a fourth diode provided between the gate and the gate terminal of the first MOSFET. 8. The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a fifth diode provided between the gate and the drain terminal of the first MOSFET. 9. The insulated gate semiconductor device according to claim 7, further comprising a capacitor provided between the gate of the first MOSFET and the gate of the power MOSFET. 10. A third resistor is further provided between the gate and the gate terminal of the power MOSFET.
9. An insulated gate semiconductor device with a built-in control circuit according to any one of 8 above. 11. A drain and a gate of the power MOSF.
The fourth MOSFET connected to the gate of ET and having the source connected to the gate terminal is further provided.
An insulated gate semiconductor device with a built-in control circuit according to any one of 0. 12. A drain and a gate each having the power MO.
A sense power MOSFET connected to the drain and gate of the SFET, a current detection element between the source and the source terminal of the sense power MOSFET, and a drain connected to the gate of the first MOSFET and a source to the source terminal. The insulated gate semiconductor device with a built-in control circuit according to any one of claims 1 to 11, further comprising a fifth MOSFET that is connected and uses a detection voltage of a current detection element as a gate input. 13. A drain and a gate for the power MO, respectively.
A sense power MOSFET connected to the drain and gate of the SFET, and a current detection element provided between the source and the source terminal of the sense power MOSFET, and the current detection node of the current detection element is connected to the second MOSF.
The insulated gate semiconductor device with a built-in control circuit according to claim 1, wherein the insulated gate semiconductor device is connected to a gate of ET. 14. A series circuit of a fourth resistor and a sixth diode connected between the gate terminal and the source terminal is further provided, and when the voltage between the anode and the cathode of the sixth diode decreases, 14. A structure in which the gate potential of the second MOSFET is increased.
An insulated gate semiconductor device with a built-in control circuit according to any one of 1. 15. A gate is connected to a gate terminal, a drain is connected to a source terminal, and a source and a body are connected to the first M.
The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a sixth MOSFET connected to the body of the OSFET. 16. A gate is connected to a source terminal, a drain is connected to a gate terminal, and a source and a body are connected to the first M.
The insulated gate semiconductor device with a built-in control circuit according to claim 1, further comprising a seventh MOSFET connected to the body of the OSFET. 17. A p-type well region is provided in the n-type drain region of the power MOSFET, an n-type diffusion layer is provided in the p-type well region, and the p-type well region is provided in the body region of the first MOSFET. The n-type diffusion layer is used as a source and a drain of the first MOSFET.
7. An insulated gate semiconductor device with a built-in control circuit according to any one of 6 above.