JPH06244413A - Insulated gate semiconductor device - Google Patents

Abstract

PURPOSE:To provide a power MOS transistor incorporating a protective circuit with improved allowable gate voltage against positive and negative voltage. CONSTITUTION:The circuit operation of temperature detection, latch and gate shut-off is stabilized by a Zener diode D10, and when an external gate 11 becomes high voltage, an M6 in a high gate voltage shut-off circuit is turned on, for a power MOS to be protected. A resistor R4 for detecting temperature is connected to an external gate terminal side, and diodes D1-4 to a source side. Further to protect from negative voltage, reverse-flow protection diodes D7-9 are inserted. Thus, thanks to the Zener diode D10 and the diodes D1-4 on the external source side, dependency on voltage in temperature detection operation is reduced. The high gate voltage shut-off circuit operates against positive high voltage, and against negative voltage, the reverse-flow protection diodes D7-9 increases its breakdown strength.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single insulated gate semiconductor device that handles a large amount of power, and more particularly to an insulated gate semiconductor device having a built-in protection function against overheat and overcurrent.

[0002]

2. Description of the Related Art Power MOSF incorporating an overheat cutoff circuit
As an example of ET, there is JP-A-63-229758. In this conventional example, temperature detection is detected by the partial pressure fluctuation of the resistance on the external source side and the diode on the external gate side, and the gate-source voltage of the protection circuit n-channel MOSFET is increased by increasing the voltage on the resistance side when the element overheats. A built-in overheat cutoff circuit cuts off the main body power MOSFET by turning on the n-channel MOSFET for the protection circuit. In this conventional overheat cutoff circuit, the n-channel MOSFE for the protection circuit against external gate voltage fluctuations is used.
Since the gate-source voltage fluctuation of T is large, the fluctuation of the gate voltage is likely to be linked to the fluctuation of the overheat cutoff temperature. Therefore, a Zener diode is inserted between the external gate and the external source corresponding to the power supply of the protection circuit unit to suppress the fluctuation of the overheat cutoff temperature due to the fluctuation of the gate voltage.

[0003]

In the circuit example of the conventional power MOSFET with a built-in overheat cutoff circuit, in order to suppress the change of the overheat cutoff temperature due to the change of the external gate, the protection circuit is provided with a constant voltage of about 10V to 4V. The Zener diode is connected. An n-channel MOSFET having a drain-source parasitic diode in the protection circuit is connected between the external gate terminal and the external source terminal. Therefore, the allowable gate voltage of the conventional power MOSFET with built-in overheat cutoff circuit is about 10V to -0.5V, which is narrower than the allowable gate voltage of a normal power MOSFET without an overheat cutoff circuit (about 20V to -20V). There was a problem.

An object of the present invention is to provide a power MOSFET with a built-in protection circuit with an improved allowable gate voltage.

[0005]

To achieve the above object, according to an embodiment of the present invention, an external drain terminal (12), an external gate terminal (11), an external source terminal (10) and a main body power are provided. In an N-channel power MOSFET having a MOSFET, the main body power MOSF
A diode (D5, D5) is provided between a second switching element (M6) different from ET and a gate terminal of the second switching element (M6) and the external gate terminal (11).
6) or a resistor, which turns off the second switching element (M6) when a positive voltage higher than a specified value is applied to the external gate terminal (11), thereby shutting off the main body power MOSFET. It is characterized by having a built-in gate voltage cutoff circuit (see FIG. 2).

Furthermore, according to another preferred embodiment of the present invention, the external drain terminal (12) and the external gate terminal (1
1), external source terminal (10) and main body power MOSFE
A power MOSFET having T is provided with a circuit (a temperature detection circuit, a latch circuit, and a gate cutoff circuit) which operates by being supplied with a voltage between the external gate terminal (11) and the external source terminal (10), and the operation of this circuit A first means (D10) for limiting the voltage range and a second means (D5, D6) for limiting the voltage range between the external gate terminal (11) and the external source terminal (10). It is characterized by having (see FIG. 7).

Furthermore, according to another preferred embodiment of the present invention, the external drain terminal (12) and the external gate terminal (1) are provided.
1), external source terminal (10) and main body power MOSFE
In a power MOSFET having T, temperature detection is detected by a partial pressure fluctuation of a resistor (R4) and a diode (D1 to D4), and when the element is overheated, the voltage fluctuation on the diode side is a fourth value.
And a gate terminal of the second switching element (M6), which lowers the gate-source voltage of the MOSFET (M1) and shuts off the main body power MOSFET by turning off the fourth MOSFET (M1). Between the external gate terminal (11) and the diode (D
5, D6) or a resistor is provided, and the second switching element (M6) is turned on when a positive voltage higher than a specified value is applied to the external gate terminal (11), thereby shutting off the main body power MOSFET. It is characterized by incorporating a high gate voltage cutoff circuit (see FIG. 2).

According to another embodiment of the present invention, a protection circuit (a temperature detection circuit, a latch circuit, a gate cutoff circuit) that operates using a voltage between the external gate terminal (11) and the external source terminal (10) as a power source. ) Built-in power MOSFET
In order to prevent backflow from the external source terminal (10) to the external gate terminal (11) (D7, D8, D
9) is incorporated (see FIG. 2).

[0009]

In a typical embodiment of the present invention (FIG. 2), a high gate voltage cutoff circuit is provided in addition to the Zener diode D10 for limiting the power supply voltage of the temperature detection circuit and the latch circuit. Therefore, when a high gate voltage of, for example, 20 V or more is input to the external gate terminal 11, the power MOSF
ET was blocked and protected so that it could be immediately seen that a high voltage was applied to the gate. For this reason, a high gate voltage is maintained for a long time with a Zener diode or power M
It can be prevented from being applied to the OSFET. Further, when the external gate voltage is in the range of 20V to 10V, the resistance Rg1 and the Zener diode D10 work to make the power supply voltage of the temperature detection circuit and the latch circuit constant at about 10V.
Further, in this embodiment, the polycrystalline silicon resistor R for temperature detection is used.
4 is connected to the external gate terminal side, and the polycrystalline silicon diode strings D1, D2, D3, and D4 having a negative temperature coefficient are connected to the external source terminal side, and the gate-source voltage applied to the polycrystalline silicon diode string is used. The n-channel MOSFET M1 for temperature detection was controlled. For this reason, a polycrystalline silicon diode string having a negative temperature coefficient is connected to the external gate terminal side and a polycrystalline silicon resistor is connected to the external source terminal side as in the conventional case, and a gate-source applied between the polycrystalline silicon resistors is connected. N channel M for temperature detection
The gate voltage dependency of the overheat cutoff temperature can be reduced compared to the case of controlling the OSFET (the voltage fluctuation of the external gate terminal is mainly the voltage fluctuation of the resistor R4 side and the voltage fluctuation amount of the diode string side is small). Therefore, there is an advantage that the change in the overheat cutoff temperature can be suppressed to a relatively small level even when an external gate voltage of 10 V or less is difficult to make a constant voltage by the Zener diode D10. In addition, in order to increase the withstand voltage of the negative external gate voltage, the diodes D7 and D
8 and D9 are provided. The diodes D8 and D9 act to block the current flowing in the parasitic diode between the drain and source of the protection circuit MOSFETs M1 to M9. Other objects and features of the present invention will be apparent from the following examples.

[0010]

1 is a circuit diagram of a first embodiment of the present invention. The present embodiment is a power MOSFET having a built-in over-gate voltage protection circuit and a negative voltage protection circuit. Where D5,
D6, D7 and D9 are polycrystalline silicon crystal silicon diodes having a breakdown voltage of about 10V. External gate terminal 11
When a normal voltage of about 5 V to 10 V is applied to M6, the diodes D5 and D6 are cut off, and M6 is in the off state. Therefore, the voltage applied to the external gate terminal 11 is applied as it is to the gate 13 of the power MOSFET of the main body to perform a normal operation. However, when a gate voltage of about 20 V or more is applied to the external gate terminal 11, D
5, D6 surrenders and M6 turns on. Therefore, the power MOSFET of the main body is cut off. In the conventional gate protection circuit, when a high gate voltage is applied, the built-in polycrystalline silicon diode prevents the high voltage from being applied to the gate oxide film of the power MOSFET of the main body. Therefore, when the gate voltage driving higher than the standard is performed, there is a problem that the gate protection diode or the main body power MOSFET is continuously stressed and the element is deteriorated. On the other hand, in the power MOSFET of this embodiment, when an external gate voltage higher than the standard is applied, the drain current is cut off, so that an abnormality in the driving condition can be immediately recognized. Therefore, there is an advantage that stress can be prevented from being applied to the gate protection diode or the main body power MOSFET for a long time. Further, in this embodiment, polycrystalline silicon diodes D9 and D7 are provided to protect the negative gate voltage. Although a parasitic diode exists between the drain and the source of the protection circuit n-channel MOSFET M6, the addition of D9 makes it possible to eliminate the external gate current component that flows backward in M6. This prevents the current flowing from the external source terminal 10 to the external gate terminal 11 when the external gate voltage drops below the external source voltage. In the present embodiment, Rg0 is provided to improve the rated voltage range of the gate voltage, but it can be omitted. In the drawings of the following Examples, Rg0 is omitted. In this embodiment, the diodes D5 and D6 are used to level shift the voltage to the gate terminal of M6 when a high gate voltage is applied, but instead of this, a high resistance can be used as the level shift element. Is.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. The concept of the embodiment of FIG.
The case where it is applied to an OSFET is shown. The power MOSFET of this embodiment shown in FIG. 2 has a Zener diode D10 and a resistor for suppressing the power supply voltage of the temperature detection circuit, the latch circuit and the gate cutoff circuit to about 10V when the external gate voltage 11 is in the range of about 20V to about 10V. Rg1 is provided, and a high gate voltage cutoff circuit is provided to forcibly cut off the power MOSFET when the external gate voltage 11 becomes about 20 V or more. Furthermore, diodes D7, D8, D9 are provided for protecting the negative gate voltage. Is the first feature. The operation of the overheat cutoff circuit when the external gate voltage 11 is about 20 V or less will be described below for reference. By setting the resistance value of the polycrystalline silicon resistor R1 of the latch circuit of the asymmetrical flip-flop circuit type to be sufficiently higher than R2, M5 is always off when the chip temperature is low when a voltage is applied to the external gate terminal. . As a result, the power MOSFET of the main body is turned on similarly to the conventional power MOSFET having no overheat cutoff circuit. On the other hand, when the power MOSFET is overheated due to an overload condition or a load short circuit, a polycrystalline silicon diode array (D1, D2, D3, D) having negative temperature dependence
The voltage applied to 4) drops and M1 turns off. As a result, M4 is turned on, the latch circuit inverts its state,
M5 of the gate cutoff circuit is turned on and the power MOSFET is cut off. In this embodiment, since the latch circuit is provided, the power MOSFET maintains the cutoff state even after cooling. In order to turn on the power MOSFET again, it is necessary to lower the external gate terminal 11 to zero volt and reset it. In the conventional power MOSFET with a built-in overheat cutoff circuit described in Japanese Patent Laid-Open No. 63-229758, a polycrystalline silicon diode array (D1, D2, D) for temperature detection is used.
(Corresponding to 3, D4) on the external gate terminal side and a resistor (corresponding to R4) on the external source terminal side, and the n-channel MOSFET (M
(Corresponding to 1) is turned on and the power MOSFET is cut off. In the case of this conventional example, the fluctuation of the gate voltage is likely to be the fluctuation of the voltage applied to the resistor,
For example, in a power MOSFET with a built-in overheat cutoff circuit that drives a gate voltage with a 5V power source, it is necessary to make it a constant voltage by a Zener diode having a breakdown voltage of about 5V. Therefore, the rated gate voltage (20V to 30V) of a normal power MOSFET without a built-in overheat cutoff circuit
There was a problem that the allowable range was narrower than that of. Further, in the normal process, in the case of the power MOSFET with a built-in overheat cut-off circuit for driving 5V, it is necessary to use a Zener diode having a withstand voltage level of 5V. There is a problem that the current flowing through the gate terminal becomes large. However, in the case of this conventional example, even if the power supply voltage of the overheat cutoff circuit section increases, the cutoff temperature of the overheat cutoff circuit changes in the direction of decreasing power M.
There is an advantage that there is no malfunction that destroys the OSFET. In this embodiment, the polycrystalline silicon diode array (D1, D2, D3, D4) for temperature detection is arranged on the external source terminal side and the resistor R4 is arranged on the external gate terminal side, and the polycrystalline silicon diode array (D1, D2, The voltage across D3, D4) drops, causing an n-channel MOSFET
The second feature is that M1 is turned off and the power MOSFET is cut off. In the case of the present embodiment, the fluctuation of the power supply voltage of the temperature detection circuit portion is mainly the fluctuation of the voltage applied to the resistor R4, and the fluctuation of the voltage applied to the polycrystalline silicon diode array (D1, D2, D3, D4). It does not easily fluctuate. Therefore, even in a region where the external gate voltage is lowered from about 10 V to about 4 V and the zener diode D10 cannot make a constant voltage, the fluctuation of the overheat cutoff temperature can be kept low for the above reason. However, the temperature detection circuit of the present embodiment has a drawback that the M1 does not turn off and the overheat cutoff circuit does not work when the external gate voltage becomes high and the temperature detection circuit section cannot be made constant voltage by the Zener diode D10. Therefore, in the temperature detection circuit of the present embodiment, a high gate voltage cutoff circuit that works so as to forcibly cut off the power MOSFET when a high external gate voltage (for example, 20 V or more) is applied so that the overheat cutoff circuit does not work. It is especially effective to incorporate it. In the case of this embodiment, it is possible to use an element having a hard breakdown characteristic of a Zener diode having a withstand voltage of 10V even for driving 5V. Therefore, there is an advantage that the gate current of the power MOSFET with a built-in overheat cutoff circuit can be reduced. In summary, in the present embodiment, when a high gate voltage (for example, about 20 V or higher) is applied, the power MOSFET of the main body is forcibly turned off. 20
Regarding the external gate voltage from V to 10V, the power supply voltage of the overheat cutoff circuit is made constant to about 10V by the Zener diode D10, and the operation of the overheat cutoff circuit is enabled. In the region where the external gate voltage is about 10V to 4V, the temperature detection circuit has a small dependency on the external gate voltage, so that the overheat cutoff circuit can operate. Also, the external gate voltage is -10V
It is possible to apply a negative voltage of. Therefore, in the conventional power MOSFET with built-in overheat cutoff circuit, from 7V-
The rated gate voltage, which was about 0.5V, was changed from 25V to -1
It can be as wide as 0V. Therefore, there is an advantage that the gate is less likely to be destroyed as compared with the conventional power MOSFET with a built-in overheat cutoff circuit. Further, even if a high gate voltage of 20 V or higher is applied, the power MOSFET is cut off by the high gate voltage cutoff circuit, so that there is an advantage that it is easy for the user to understand that the high gate voltage is applied by mistake. Therefore, there is an advantage that it is easy to prevent an overload from being applied to the gate for a long time. Further, the gate current of the conventional power MOSFET with built-in overheat cutoff circuit was 100 μA or more, but in the present embodiment, it is 50 μA.
It can be suppressed to about A or less. Therefore, there is an advantage that the power MOSFET with a built-in overheat cutoff circuit can be directly driven even by a drive circuit having a low drive capability such as a microcomputer. MOSFET for overheat cutoff circuit of the present embodiment
The threshold voltages of M1 to M6 may all have the same value,
For example, it is desirable that the threshold voltages of M1 and M6 are set to a high value of about 2.5V, and the threshold voltages of M5, M2, and M3 are set to about 1V. The reason for increasing the threshold voltage of M1 for the temperature detection circuit is to improve the accuracy of the overheat cutoff temperature by the diodes (D1, D2, D3, D) for temperature detection.
This is because the number of 4) can be arranged as much as possible. Further, the reason for increasing the threshold voltage of M6 for the high gate voltage cutoff circuit is to prevent the high gate voltage cutoff circuit from operating due to a malfunction at the time of inputting a normal gate voltage. On the other hand, M5 for the gate cutoff circuit reduces the element area, and thus the current driving capability is increased even at a low gate voltage, so the threshold voltage is lowered. In addition, it is desirable that the threshold voltages of M2 and M3 be low in order to operate the latch circuit even at a low gate voltage. Diode D1,
Since the number of D2, D3, and D4 is determined by the relationship between the level of the external gate voltage and the accuracy of the cutoff temperature, it may be changed to three or five depending on the case. It is desirable that D1, D2, D3, and D4 used in the polycrystalline silicon diode array have a structure in which a high-concentration diffusion layer is in contact, and that series resistance is reduced to reduce external gate voltage dependence.

FIG. 3 is a circuit diagram of the third embodiment of the present invention. In this embodiment, the diode D11 is replaced by the diode D10.
In addition to the resistor R having a positive temperature dependence for temperature detection
4 is connected to the anode side of the diode D8, which is different from the embodiment of FIG. 2 and has the same effect as the previous embodiment.

FIG. 4 is a circuit diagram of the fourth embodiment of the present invention. This embodiment is an embodiment in which the drain of M6 is connected to the temperature detection circuit instead of the latch circuit, and has the same effect as the embodiment shown in FIG.

FIG. 5 is a circuit diagram of the fifth embodiment of the present invention. Although the diodes D1, D2, D3, and D4 are used to obtain the negative temperature coefficient in the above-described embodiments, in the present embodiment, the absolute value of the temperature coefficient is larger than that of the polycrystalline silicon resistor R4 and is negative instead. A polycrystalline silicon resistor R5 having a temperature coefficient was used. This embodiment also has the same effect as in FIG. In this embodiment, an overvoltage protection circuit including polycrystalline silicon diodes D12 to D26 and a resistor Rg3 is added to the external drain terminal 12 side. It goes without saying that an overvoltage protection circuit on the side of the external drain terminal 12 similar to that of this embodiment can be added to the other embodiments.

FIG. 6 is a circuit diagram of a sixth embodiment of the present invention. In this embodiment, MOSFETs each diode-connected to increase the effective threshold voltage of M1, M4, and M6.
This is an example when M7, M8, and M9 are added. As a result, even if the threshold voltages of the MOSFETs used in the overheat cutoff circuit are all the same, the accuracy of the overheat cutoff temperature is improved, the malfunction of the high gate voltage cutoff circuit is prevented, and the protection circuit is protected as described in the embodiment of FIG. There is an advantage that area reduction can be achieved. In this embodiment, a diode-connected MOS is used.
Although one FET (M7, M8, M9) is connected to each, two or more FETs can be arranged if necessary.

FIG. 7 is a circuit diagram of the seventh embodiment of the present invention. In this embodiment, a constant voltage circuit using Zener diodes D5 and D6 is used instead of the high voltage cutoff circuit of the embodiment of FIG. In this embodiment, a power MOS whose external gate voltage is determined by the breakdown voltage of the Zener diodes D5 and D6 and which has an upper limit value (for example, 20 V) or more.
Although there is no FET cutoff function, the rated gate voltage can be widened from 20V to about -10V, and further, the gate current can be suppressed to about 50 μA or less, which is the advantage of the embodiment of FIG. It is the same.

FIG. 8 is a structural sectional view of a semiconductor device according to an eighth embodiment of the present invention. Reference numeral 1001 denotes a high-concentration N-type region which is an external drain region of the power MOSFET of the main body. 1012a
Is the source electrode of the power MOSFET of the main body, 1007a
Is the gate region of the main body power MOSFET. 100
Reference numeral 2 denotes an N-type epitaxial layer which is a drain region of the main body power MOSFET. In this embodiment, as described in the embodiment of FIG. 2, the overheat cutoff circuit has a high threshold voltage MOSFET.
Since a MOSFET having a low threshold voltage is used, the surface concentration of the P-type well region 1005 is set to the P-type well region 1004.
Lower than the surface concentration of the n-channel MOSFET
The threshold voltage of (1) is set to a high value of about 2V to 4V for M1 and M6, and the threshold voltage of the n-channel MOSFET (2) is set to a low value of about 1V to 2V for M2, M4 and M5. The n-channel MOSFET (1) needs to be higher than the breakdown voltage of the Zener diode D10, but since the surface concentration of the P-type well region 1004 is high, the device breakdown voltage may be lower. In this case, it is desirable to provide a low concentration n-type region on the drain side to increase the breakdown voltage. FIG. 9 is a structural sectional view of a semiconductor device according to a ninth embodiment of the present invention. In this embodiment, an n-channel MOSFET
A P-type channel diffusion layer 1008 of the main body was added to the source side as a means for increasing the threshold voltage of (1) by 0.3 V or more than the threshold voltage of the n-channel MOSFET (2).
This enables two types of protection circuit n-channel MOSFE.
There is an advantage that only one type of P well diffusion layer is needed where two types of P well diffusion layers are required to manufacture T as in the embodiment of FIG.

Although the power MOSFETs have been described in the above embodiments, the present technique is generally applicable to power insulated gate semiconductor devices including insulated gate bipolar transistors.

[0019]

According to the present invention, the range of the rated gate voltage of the power MOSFET with a built-in overheat cutoff circuit can be expanded and the reliability can be improved, and the dependence of the overheat cutoff temperature on the gate voltage and the gate current can be reduced. is there.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an insulated gate semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an insulated gate semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an insulated gate semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an insulated gate semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of an insulated gate semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of an insulated gate semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram of an insulated gate semiconductor device according to a seventh embodiment of the present invention.

FIG. 8 is a structural sectional view of an insulated gate semiconductor device according to an eighth embodiment of the present invention.

FIG. 9 is a structural cross-sectional view of an insulated gate semiconductor device according to a ninth embodiment of the present invention.

[Explanation of symbols]

10 ... External source terminal, 11 ... External gate terminal, 12 ...
External drain terminal, 13 ... Internal gate terminal of main body power MOSFET, R1 to R5, Rg0 to Rg3 ... Resistor, D1 to
D27 ... Diode, M1 to M9 ... MOSFET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Otaka 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the semiconductor design and development center, Hitachi, Ltd.

Claims (14)

[Claims] 1. An N-channel insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, wherein a second switching element different from the main body element and an input of the second switching element. A diode or a resistor is provided between the terminal and the external gate terminal, and the main switching element is shut off by turning on the second switching element when a positive voltage higher than a specified value is applied to the external gate terminal. An insulated gate semiconductor device having a built-in high gate voltage cutoff circuit. 2. A P-channel insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, wherein a third switching element different from the main body element and an input of the third switching element. A diode or a resistor is provided between the terminal and the external gate terminal, and the third switching element is turned on when a negative voltage below a specified value is applied to the external gate terminal, thereby shutting off the main body element. An insulated gate type semiconductor device having a built-in gate voltage cutoff circuit. 3. An insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, which is provided with a circuit which is operated by being supplied with a voltage between the external gate terminal and the external source terminal. And a second means for limiting the voltage range between the external gate terminal and the external source terminal. 4. An N-channel insulated gate type semiconductor device having a built-in protection circuit which operates by using a voltage between an external gate terminal and an external source terminal as a power supply, wherein a diode for preventing backflow from the external source terminal to the external gate terminal is built in. An insulated gate semiconductor device characterized by: 5. A P-channel insulated gate semiconductor device having a built-in control circuit that operates by using a voltage between an external gate terminal and an external source terminal as a power supply, having a diode for preventing backflow from the external gate terminal to the external source terminal. An insulated gate semiconductor device characterized by: 6. In an insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, temperature detection is detected by a partial pressure change of a resistor and a diode, and the voltage on the diode side is detected when the element is overheated. 3. An overheat cutoff circuit which cuts off the main body element when the fourth insulated gate type semiconductor element is turned off due to a change in the gate-source voltage of the fourth insulated gate type semiconductor element, and the fourth insulated gate type semiconductor element is turned off. 2. An insulated gate semiconductor device comprising the high gate voltage cutoff circuit described in 1. 7. In an insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, temperature detection is detected by a partial pressure change of a resistor and a diode, and the voltage on the diode side is detected when the element is overheated. A variation has a gate-source voltage of the fourth insulated gate semiconductor element, and has an overheat cutoff circuit that shuts off the main body element by turning off the fourth insulated gate semiconductor element. Operates by a voltage between an external gate terminal and an external source terminal, and first means for limiting an operating voltage range of this circuit; and a voltage range between the external gate terminal and the external source terminal. And an insulating gate type semiconductor device. 8. The insulated gate semiconductor device according to claim 6, wherein a second resistor having a temperature coefficient whose absolute value is larger than that of said resistor for temperature detection is used instead of said diode. . 9. An insulated gate semiconductor device according to claim 6, wherein the backflow prevention diode according to claim 4 or 5 is incorporated. 10. An insulated gate semiconductor device according to claim 7, wherein the backflow prevention diode according to claim 4 or 5 is incorporated. 11. An insulated gate semiconductor device according to claim 8, wherein the backflow prevention diode according to claim 4 or 5 is incorporated. 12. An insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, and a control circuit for the main body element that operates using the voltage between the external gate terminal and the external source terminal as a power source, An insulated gate type semiconductor device, characterized in that two or more types of insulated gate type semiconductor elements having different threshold voltages of 0.3 V or more are used in the control circuit. 13. A channel diffusion layer for an insulated gate semiconductor element of the main body element is provided on a source side in order to provide a threshold voltage difference of the insulated gate semiconductor element for controlling the main body element. The insulated gate semiconductor device according to claim 12. 14. An insulated gate semiconductor device having an external drain terminal, an external gate terminal, an external source terminal and a main body element, and a main body element which operates by using the voltage between the external gate terminal and the external source terminal as a power supply control circuit. The threshold voltage of the second insulated gate semiconductor device used in the temperature detection circuit is set higher than the threshold voltage of the second insulated gate semiconductor device used in the gate cutoff circuit by 0.3 V or more. Insulated gate type semiconductor device.