JP2001044291A - Protection device for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which is sufficiently high in resistance against a high-speed surge such as ESD. SOLUTION: A protection circuit 40 is equipped with a FET 41, a capacitor 42, and a series circuit 43 connected in parallel with the capacitor 42. The capacitor 42 is connected between the gate and drain of the FET 41. The source of the FET 41 is connected to the gate of the FET 10 through the intermediary of a Zener diode 50.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for a semiconductor device having a protection function for protecting the semiconductor device from high-speed surge.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device, for example,
There is one as shown in FIG. In this protection device for a semiconductor device, in order to improve the surge resistance against a surge voltage from the inductive load 1, the series circuit 3 of the plurality of Zener diodes for clamping is formed of a double diffusion MOS type (hereinafter, referred to as a DMOS type). It is arranged between the drain and the gate of the field effect transistor 2.

[0003] When a surge voltage is applied to the semiconductor device from the inductive load 1, each Zener diode of the series circuit 3 breaks at a voltage lower than that of the field effect transistor 2, so that the gate of the transistor 2 is turned off. , The transistor 2 is turned on, and a surge current based on the surge voltage flows through the transistor 2. Hereinafter, in this specification, a field effect transistor is referred to as an FET.

Here, since the operating resistance of the FET 2 has a positive temperature coefficient, current concentration hardly occurs. Therefore, FE
No internal break occurs in T2, and the parasitic transistor 2a of the FET 2 does not operate. Therefore, the surge withstand capability of the semiconductor device can be improved.

[0005]

By the way, in the above semiconductor device, each Zener diode of the series circuit 3 is
It may be a multiple polysilicon Zener diode alternately doped with boron, phosphorus or the like, or a diode having multiple Zener diodes formed by diffusing a base / emitter layer inside a power IC.

For this reason, since the chip size does not become large, the size of the Zener diode is generally
It is very small compared to 2.

Therefore, the internal resistance of all the Zener diodes of the series circuit 3 is usually as large as about 1 kΩ, and a break voltage of each Zener diode (generally, a voltage lower than the withstand voltage of the FET 2 by about 10 V) in order to flow a current. ) Must be maintained, so that a sufficient bias cannot be applied to the gate of FET2. Therefore, the amount of current that can flow when the FET 2 is turned on is small, and the electrostatic discharge (hereinafter, E
However, there is a problem that the resistance to high-speed and large-current surges (such as SD) is not significantly improved.

To cope with this, a semiconductor device as disclosed in Japanese Patent Application Laid-Open No. 8-64812 has been proposed (FIG. 2).
3).

In this semiconductor device, a protection circuit 4, a backflow preventing zener diode 5, and a resistor 6 are connected between the inductive load 1 and the gate of the FET 2 in FIG.

The protection circuit 4 has a DMOS type FET 4a, and the FET 4a has an FE at its drain.
The source is connected to the drain of T2, and the source is connected to the gate of FET2 via the Zener diode 5 and the resistor 6.

The protection circuit 4 includes a capacitor 4b, and the capacitor 4b is connected between the gate and the drain of the FET 4a. Further, a series circuit 4c formed by connecting a plurality of zener diodes for clamping in series is connected in parallel to the capacitor 4b.

In the semiconductor device disclosed in the above publication, the inductive load 1
Is applied to the protection circuit 4, the surge current initially passes through the capacitor 4b and the FET 4a
To turn on the FET 4a.

Accordingly, a surge current based on a surge voltage from the inductive load 1 flows through the FET 4a, the Zener diode 5, and the resistor 6 into the gate of the FET 2, and turns on the FET 2. Therefore, a surge current from the inductive load 1 flows through the FET 2.

However, the surge voltage may be a surge (such as an operation time of about 10 nsec, a peak current of about 160 A, a peak current of about 160 A, 150 Ω, 150 p
F, 25 kV discharge), the FET 4a is turned on,
It is necessary to charge the gate of the FET2 to a high voltage (for example, a voltage 10 times the threshold value of the FET2) instantaneously (for example, within 1 nsec) and to supply a surge current by turning on the FET2.

Therefore, as described above, if the resistor 6 is connected between the Zener diode 5 and the gate of the FET 2, the charging current for the gate of the FET 2 is reduced by the resistor 6, and the gate of the FET 2 is instantaneously connected. And can not be fully charged.

Therefore, the internal diode of the FET 2 causes an avalanche break, and in the worst case, the FET 2
The parasitic bipolar transistor operates to cause permanent destruction due to current concentration. As a result, FET
2, the ESD resistance of the semiconductor device is reduced.

In view of the above, it is an object of the present invention to provide a semiconductor device having a protection function capable of sufficiently withstanding a high-speed surge such as ESD. .

[0018]

In order to solve the above problems, according to the first aspect of the present invention, a protection device for protecting a main transistor (10) formed on a semiconductor substrate from a high-speed surge is provided by a control terminal of the main transistor. Backflow Zener diode (50) whose cathode is directly connected to
A protection transistor (41) having an output terminal and an input terminal connected to the anode of the Zener diode and the input terminal of the main transistor, respectively, between the control terminal of the protection transistor and the input terminal of the main transistor. A protection capacitor (42) that is connected and allows an initial surge current generated based on the high-speed surge to flow into a control terminal of the protection transistor.

When the protection transistor is turned on by the inflow of the initial surge current, the next surge current generated subsequent to the initial surge current based on the high-speed surge flows into the control terminal of the main transistor through the reverse current blocking Zener diode. When the transistor is turned on by the inflow of the next surge current, a final surge current generated subsequent to the next surge current flows based on the high-speed surge.

According to this, no resistor is connected between the protection transistor and the main transistor, and only the backflow preventing Zener diode having an extremely small internal resistance is connected. The next surge current flowing through the transistor flows into the control terminal of the main transistor through the backflow preventing Zener diode without being throttled at all.

As a result, the next surge current instantaneously and sufficiently flows into the control terminal of the main transistor as a charging current. Therefore, the main transistor turns on instantaneously,
The final surge current can flow through the driving transistor without causing an avalanche break of the diode constituting the parasitic element or causing the operation of the transistor constituting the parasitic element. Therefore, the ESD resistance of the semiconductor device can be sufficiently ensured.

According to the second aspect of the present invention, the protection device for protecting the main transistor (10) formed on the semiconductor substrate from high-speed surge has a backflow prevention having a cathode directly connected to a control terminal of the main transistor. And a protection transistor (4) having an output terminal and an input terminal connected to the anode of the zener diode and the input terminal of the main transistor, respectively.
6) and a Zener diode circuit (45a, 45a) connected between the control terminal of the protection transistor and the input terminal of the main transistor to allow the initial surge current generated based on the high-speed surge to flow into the control terminal of the protection transistor.
b, 48).

When the protection transistor is turned on by the initial surge current, the next surge current generated subsequent to the initial surge current based on the high-speed surge flows into the control terminal of the main transistor through the reverse current blocking Zener diode. When the transistor is turned on by the next surge current, a final surge current that follows the next surge current flows based on the high-speed surge.

According to this, when the next surge current flows into the input terminal of the protection transistor, the Zener diode of the Zener diode circuit breaks and the next surge current flows into the control terminal of the protection transistor to be charged. The protection transistor is turned on. Along with this, the main transistor is turned on and a final surge current flows.

According to this, the same operation and effect as the first aspect can be achieved.

According to a third aspect of the present invention, in the protection device for a semiconductor device according to the first or second aspect, the main transistor and the protection transistor are formed of an MO.
It may be an S-type FET.

According to a fourth aspect of the present invention, in the protection device for a semiconductor device according to the first aspect, the protection device is connected between a protection transistor and a protection capacitor.
With the auxiliary protection transistor that amplifies the initial surge current and flows into the control terminal of the protection transistor, the auxiliary protection transistor is connected to the control terminal of the auxiliary protection transistor by the initial surge current flowing through the protection capacitor. While the protection transistor is charged by the protection capacitor, the protection transistor is charged at its control terminal by the auxiliary protection transistor that is turned on. Therefore, the voltage of the control terminal of the auxiliary protection transistor can be boosted to a higher voltage. Therefore, more current can flow to the main transistor.

As a result, since the bias voltage at the control terminal of the main transistor is further increased, the maximum value of the saturation current accompanying the turning on of the main transistor also increases. For this reason,
The ESD resistance can be further improved.

According to a fifth aspect of the present invention, in the protection device for a semiconductor device according to the second aspect, the protection circuit is connected between a protection transistor and the protection capacitor to amplify the initial surge current. And an auxiliary protection transistor flowing into a control terminal of the protection transistor.

According to this, the same operation and effect as the invention described in claim 4 can be achieved.

Here, as in the invention described in claim 6,
In the protection device for a semiconductor device according to claim 4 or 5, the main transistor and the protection and auxiliary protection transistors may be MOS FETs.

According to a seventh aspect of the present invention, in the protection device for a semiconductor device according to the first aspect, the protection transistor includes a Zener diode for a reverse current element. Thereby, the operation and effect of the invention described in claim 1 can be further improved.

In the invention according to claim 8, in the protection device for a semiconductor device according to claim 2, the protection transistor has a built-in Zener diode for a reverse current element. Thereby, the function and effect of the invention described in claim 2 can be further improved.

According to a ninth aspect of the present invention, in the protection device for a semiconductor device according to the first aspect, a protection zener diode connected in parallel to the protection capacitor is provided, and a current flowing through the protection capacitor is provided. Is the first initial surge current, and the current flowing through the protective zener diode is the second initial surge current following the first initial surge current.

Thus, the function and effect of the first aspect can be further improved.

Further, as in the invention according to claim 10,
10. The protection device for a semiconductor device according to claim 7, wherein the main transistor is a MOSFET.
The protection transistor may be a bipolar transistor.

According to the eleventh aspect of the present invention, in the protection device for a semiconductor device according to the fourth aspect, the protection transistor includes a Zener diode for a reverse current element. Thereby, the function and effect of the invention described in claim 4 can be further improved.

According to a twelfth aspect of the present invention, in the protection device for a semiconductor device according to the fifth aspect, the protection transistor has a built-in Zener diode for a reverse current element. The operation and effect of the invention described in claim 5 can be further improved.

Further, as in the invention according to claim 13,
13. The protection device for a semiconductor device according to claim 11, wherein the main transistor is a MOSFET, and the protection and auxiliary protection transistors are bipolar transistors.

Further, according to the present invention, the protection device formed on the semiconductor substrate to protect the main transistor (10) from high-speed surge has a cathode connected to a control terminal of the main transistor for preventing backflow. A zener diode (50), a protection zener diode (61) having an anode and a cathode respectively connected to the anode of the backflow preventing zener diode and the input terminal of the main transistor, and connected in parallel to the protection zener diode. A protection capacitor (62) that allows an initial surge current generated due to the high-speed surge to flow into the control terminal of the main transistor through a Zener diode for backflow prevention.
b).

The protection zener diode causes the next surge current generated following the initial surge current based on the high-speed surge to flow into the control terminal of the main transistor through the backflow prevention zener diode. When it is turned on by the inflow of the next surge current, a final surge current generated subsequent to the next surge current flows based on the high-speed surge.

According to this, the initial surge current flows into the control terminal of the main transistor through the protection capacitor and the backflow preventing zener diode, and then the next surge current flows through the protection zener diode and the backflow preventing zener diode. It flows into the control terminal of the main transistor.

Here, no resistor is connected between the anode of the protective Zener diode and the control terminal of the main transistor, and only a backflow preventing Zener diode having a very small internal resistance is connected. .

Accordingly, the initial surge current and the next surge current pass through the backflow preventing zener diode without any restriction and flow into the control terminal of the main transistor instantaneously and sufficiently as a charging current.

Therefore, the main transistor is turned on instantaneously,
The final surge current can flow without causing the avalanche break of the diode as the parasitic element or the operation of the transistor as the parasitic element. As a result, the ESD resistance of the semiconductor device is improved.

According to the present invention, a protection device for protecting a main transistor (10) formed on a semiconductor substrate from a high-speed surge is provided for preventing a backflow having a cathode connected to a control terminal of the main transistor. A plurality of transistors (71 to 74) each having a Zener diode (50) and an output terminal and an input terminal connected to the anode of the backflow preventing Zener diode and the input terminal of the main transistor, respectively, as first and subsequent stage transistors. A protection transistor circuit (70) connected in Darlington.

The protection transistor circuit is
The subsequent transistor is turned on by the initial surge current generated based on the high-speed surge, and the first transistor is turned on with this on, and the first-stage transistor is turned on and the next transistor generated following the initial surge current based on the high-speed surge The surge current is caused to flow into the control terminal of the main transistor, and when the main transistor is turned on by the inflow of the next surge current, a final surge current that follows the next surge current based on the high-speed surge flows. According to this, the current flowing through the Zener diode for backflow prevention and flowing into the control terminal of the main transistor can be sufficiently amplified by the amplifying action of the plurality of transistors connected in Darlington. Therefore, the main transistor is instantly turned on, and the final surge current can sufficiently flow without causing the operation of the parasitic element. As a result, an improvement in the ESD resistance of the semiconductor device can be ensured.

Further, according to the invention of claim 16,
In the protection device for a semiconductor device according to claim 15, each of the main transistor and each transistor of the protection circuit may be a MOSFET.

According to the seventeenth aspect of the present invention,
2. The protection device for a semiconductor device according to claim 1, wherein the protection transistor is connected in parallel with the protection transistor, wherein an anode is connected to the input terminal of the main transistor, and a cathode is connected to a cathode of the Zener diode. The main transistor controls the current supply to the load connected to the input terminal of the protection zener diode, and the load generates a load surge when the current is cut off. High-speed surges are caused by electrostatic discharge, and load surges have a lower frequency than high-speed surges. Breakdown occurs before turning on the main transistor.

As described above, since the breakdown is caused by the load surge having a smaller frequency than the high-speed surge and the main transistor is turned on, the main transistor can be protected not only by the high-speed surge but also by the load surge.

Further, as in the invention of claim 18,
The protection device for a semiconductor device according to claim 17, wherein the high-speed surge has a frequency in a GHz range,
The load surge may have a frequency in the kHz range.

According to the nineteenth aspect of the present invention,
18. The protection device for a semiconductor device according to claim 1, wherein the operating resistance until the next surge current flows into the control terminal of the main transistor via the Zener diode for backflow prevention is set to Rh, and the main transistor is driven. Rd> Rh, where Rd is the driving resistance arranged on the path from the driving circuit for the driving.

As a result, the main FE is surely applied when ESD is applied.
The voltage drop in the driving resistor required to operate T becomes a voltage sufficiently higher than the threshold voltage of the main FET, and as a result, the operation and effect of the invention according to claim 1 or 17 are further enhanced. Can be improved.

According to the twentieth aspect of the present invention,
18. The protection device for a semiconductor device according to claim 17, wherein the operating resistance until the load surge current flows into the control terminal of the main transistor via the reverse current blocking zener diode is Rh, and the main transistor is driven. Assuming that the driving resistance arranged on the path from the driving circuit is Rd, there is a relation of Rd> Rh.

As a result, the voltage drop at the driving resistor required to reliably operate the main FET when a load surge is applied becomes a voltage sufficiently higher than the threshold voltage of the main FET. The operation and effect of the invention described in Item 17 can be further improved.

According to the twenty-first aspect of the present invention,
2. The protection device for a semiconductor device according to claim 1, wherein the main transistor is formed as a cell region having a plurality of single cells on a semiconductor substrate, and the control terminal of the main transistor has a plurality of unit cells. The signal application electrode is formed as a common terminal for each cell, the terminal is drawn out of the cell region, and a signal application electrode formed on the surface of the semiconductor substrate so as to surround the cell region outside the cell region. The signal application electrode is connected to the cathode of the backflow preventing zener diode, and has a wiring width wider than the wiring width from the cathode to the signal application electrode.

By adopting such a configuration, the function and effect of the first aspect of the present invention can be further improved.

The symbols in parentheses of the above means indicate the correspondence with the specific means described in the embodiments described later.

[0059]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of a semiconductor device to which the present invention is applied.

The semiconductor device is a horizontal type DMOS (hereinafter, referred to as a “DMOS”).
And a load driving FET 10 (referred to as an LDMOS). The FET 10 is connected at its drain to a load 20.

The gate of the FET 10 is connected to the Zener diode 31 and the resistor 3 from the gate drive circuit 30.
2 (having a resistance of about 1 kΩ) and a pulse voltage is applied via a Zener diode series circuit 33 to perform a switching operation. Note that the FET 10
Hereinafter, it is referred to as main FET 10.

Here, the main FET 10 is formed by forming an internal diode 11, an internal resistor 12, and a parasitic transistor 13 as shown in FIG. Note that a surge such as an ESD is applied to the semiconductor device from the terminal of the load 20.

Each zener diode of the zener diode series circuit 33 is constituted by a base and an emitter of an npn-type transistor, and the withstand voltage of these zener diodes is about 8V. Further, the number of the Zener diodes is set to three so as to be equal to or less than the withstand voltage of the gate oxide film of the main FET 10. The Zener diode 31 serves to clamp the pulse voltage of the gate drive circuit 30 to the operating voltage, and the breakdown voltage of the Zener diode 31 is set to the gate drive voltage of the main FET 10 (about 8 V).

Further, the semiconductor device includes a protection circuit 40 connected between the gate and the drain of the main FET 10 and a Zener diode 50 for preventing backflow as a protection device.

The protection circuit 40 includes a protection MOSFET 41
This FET 41 has, at its drain,
It is connected to the drain of the main FET 10. The source of the FET 41 is connected to the gate of the main FET 10 via the Zener diode 50. FE
T41 also forms an internal diode, an internal resistance, and a parasitic transistor similarly to the main FET 10. Also, FET
Reference numeral 41 is hereinafter referred to as an auxiliary FET 41.

The protection circuit 40 includes a capacitor 42 connected between the gate and the drain of the auxiliary FET 41,
A zener diode series circuit 43 (comprising a series circuit of a plurality of zener diodes) connected in parallel to the capacitor 42. Note that the capacitor 42 is formed using an oxide film formed on a silicon substrate.

Here, the capacitor 42 receives the ESD from the load 20 and flows in the initial surge current generated based on the ESD, and the auxiliary FET 41 flows the next surge current generated subsequent to the initial surge current based on the ESD. Then, the zener diode series circuit 43 plays a role of flowing a surge current slower than the ESD included in the surge of the load 20. Note that in FIG.
Indicates a pull-down resistor for turning off the auxiliary FET 41.

The Zener diode 50 is connected at its anode to the source of the auxiliary FET 41, and the cathode of this Zener diode 50 is connected to the gate of the main FET 10. This Zener diode 50
Plays a role of preventing backflow when the main FET 10 is turned on. The withstand voltage of the Zener diode 50 is set to be equal to or higher than the gate drive voltage (about 8 V) of the main FET 10. In FIG. 1, reference numeral 34 denotes a Zener diode (having a withstand voltage of about 100 V) for preventing a surge from the ground line.

In the first embodiment configured as described above, when an ESD is applied from the load 20 to the semiconductor device, an initial surge current based on the ESD is applied to the capacitor 4.
2 and flows into the gate of the auxiliary FET 41. Since the area of the auxiliary FET 41 is smaller than the area of the main FET 10 and the input capacitance of the gate of the auxiliary FET 41 is small, the auxiliary FET 41 is turned on in a short time. Thereby, the drain-source of the auxiliary FET 41 becomes conductive with a low resistance.

Accordingly, the next surge current based on the ESD flows through the auxiliary FET 41 and flows into the gate of the main FET 10 through the Zener diode 50.

Here, in the first embodiment, the auxiliary FET
No resistance is connected between the source of 41 and the gate of the main FET 10, and only the Zener diode 50 is connected. In addition, the internal resistance of the Zener diode 50 is very small.

Therefore, the next surge current flowing through the auxiliary FET 41 flows into the gate of the main FET 10 through the Zener diode 50 without being throttled at all. This means that the next surge current instantaneously and sufficiently flows into the gate of the main FET 10 as a charging current.

As a result, the main FET 10 is turned on instantaneously, without causing an avalanche break of the internal diode 11 or causing the operation of the internal transistor 13, without causing the final surge current following the next surge current based on ESD to occur. Apply current.

As a result, the ESD resistance of the semiconductor device can be sufficiently ensured.

In the first embodiment, the capacitor 42 is connected between the drain and the gate of the auxiliary FET 41 as described above. Therefore, the auxiliary FET 4
When the next surge current flows into the drain of the first FET, a part of the next surge current flows into the gate of the auxiliary FET 41 through the capacitor. Here, in particular, for a high-speed (about several nsec) surge such as ESD, the impedance of the capacitor 42 is reduced, so that more current can flow through the capacitor 42.

When the gate of the auxiliary FET 41 is charged and becomes equal to or higher than the threshold value, the auxiliary FET 41 enters an operation state and can flow more surge current. In general, a capacitor can be designed to have a smaller impedance when viewed at the same size as a conventional Zener diode, so that the ESD surge resistance can be improved as compared with the conventional Zener diode.

When a Zener diode is used in a protection circuit as in the conventional case, the Zener diode breaks faster than the auxiliary FET 41 and the gate voltage of the main FET 10 sufficiently rises when an ESD surge is applied. Since it is necessary to set the withstand voltage of the Zener diode to a value considerably lower than the withstand voltage of the auxiliary FET 41, the main F
Although a substantial decrease in the breakdown voltage of the ET 10 is caused, the protection circuit using the capacitor 42 as in the first embodiment does not cause such a decrease in the breakdown voltage of the auxiliary FET 41.

FIG. 2A shows the ESD waveform and the operation timing of the protection circuit shown in FIG. 1 in the semiconductor device according to the first embodiment. According to this, the ESD waveform rises at several nsec to 10 nsec, and the peak rises to about 200A. In response to such a surge, the capacitor 42 operates at the time Ta, and an initial surge is injected into the gate of the auxiliary FET 41.
At the time Tb, the auxiliary FET 41 operates to inject the next surge into the gate of the main FET 10. At the time Tc, the main FET 10 operates to absorb the final surge in the main FET operation range shown in FIG.

Further, in the semiconductor device according to the first embodiment, when a resistor is connected in series to the Zener diode 50 and how the ESD breakdown voltage changes according to the resistance value of the resistor is examined. FIG. 2 (b)
The graph as shown by was obtained.

According to this, as the resistance value of the resistor increases, the ESD breakdown voltage decreases. For example, when the resistance value of the resistor is set to 50Ω as in the conventional example,
The ESD breakdown voltage is reduced by half as compared with the case where the resistor is not connected as in the first embodiment, and increases as the resistance value of the resistor decreases.

Therefore, if the above-described resistors are not connected as in the first embodiment, the ESD breakdown voltage can be maintained at a maximum, and
Accordingly, the maximum ESD resistance can be maintained.

The surge that is slower than the ESD is applied to the load 20.
Applied to the semiconductor device, the Zener diode of the Zener diode series circuit 43 breaks, and the surge current based on the slow surge flows into the gate of the auxiliary FET 41 through the Zener diode series circuit 43 to turn on the auxiliary FET 41. Accordingly, the main FET 10
Is turned on to flow through the main FET 10. This gives E
The semiconductor device can be protected from a surge that is slower than SD.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS.

In the second embodiment, the protection circuit 60
It is connected between the Zener diode 50 and the load 20 instead of the protection circuit 40 described in the first embodiment.

The protection circuit 60 includes a Zener diode 61
And the parasitic resistance 62a of the capacitor 62b and the capacitor 6
2b and a series circuit 62. The Zener diode 61 has its cathode connected to the drain of the main FET 10. The anode of the Zener diode 61 is connected via the Zener diode 50 to the main FET 10.
Connected to the gate. The other configuration is the same as that of the first embodiment.

In the second embodiment configured as described above,
When ESD is applied to the semiconductor device from the load 20, the initial surge current flows through the series circuit 62, flows into the gate of the main FET 10 via the Zener diode 50, and then the next surge current flows through the Zener diode 61. It flows into the gate of the main FET 10 through the Zener diode 50.

Here, in the second embodiment, no resistance is connected between the anode of the Zener diode 61 and the gate of the main FET 10, and the Zener diode 5
Only 0 is connected. Moreover, the internal resistance value of the Zener diode 50 is very small as described above.

Therefore, the initial surge current flowing through the series circuit 62 including the capacitor 62b and the next surge current flowing through the Zener diode 61 are both passed through the Zener diode 50 without being reduced at all and are not reduced.
Flows into gate 10 This means that the initial surge current and the next surge current flow instantaneously and sufficiently into the gate of the main FET 10 as a charging current.

As a result, the main FET 10 is turned on instantaneously, causing the final surge current based on ESD to flow without causing an avalanche break of the internal diode 11 or causing the operation of the internal transistor 13.

As a result, even if the auxiliary FET 41 described in the first embodiment is not provided, a synergistic action between the series circuit 62 including the capacitor 62b and the Zener diode 61 as in the second embodiment causes the semiconductor device to operate. ES
D tolerance can be sufficiently secured.

In the semiconductor device according to the second embodiment, the relationship between the ESD breakdown voltage and the capacitance of the capacitor 62b depends on the presence or absence of the Zener diode 61, the Zener voltage V _ZD of the Zener diode 61, and the resistance of the resistor 62a. When the value R was examined as a parameter, graphs as shown by reference numerals L1 to L4 in FIG. 4 were obtained. Here, the graph L4 shows the case without the Zener diode 61, the graph L3 shows the case with the Zener voltage V _ZD = 51 (V) and the resistance value R = 10 (Ω), and the graph L2 shows the Zener voltage V _{The case where ZD} = 43 (V) and the resistance value R = 10 (Ω) is shown, and the graph L1 shows the case where the Zener voltage V _ZD = 34 (V) and the resistance value R = 10 (Ω).

According to this, the graph L1 to the graph L4
, The ESD breakdown voltage gradually decreases, and the larger the capacitance of the capacitor 62b, the higher the ESD breakdown voltage.

The capacitance of the capacitor 62b = 20
(PF), resistance value R = 5 (Ω), and Zener voltage V _ZD =
The initial surge current at the time of 34 (V) changes as shown by a symbol G1 in FIG. 5, and the next surge current changes as shown by a symbol G2 in FIG.

Thus, it can be seen that the above-described operation and effect of the second embodiment can be achieved by using a substantially parallel circuit of the capacitor 62b and the Zener diode 61.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.

In the third embodiment, the protection circuit 60A
However, this is adopted in place of the protection circuit 40 described in the first embodiment.

The protection circuit 60A has a configuration in which a bipolar transistor 63 is used instead of the MOSFET 41 in the protection circuit 40 and the Zener diode 50 is eliminated. The bipolar transistor 63 has its collector connected to the drain of the main FET 10, and the emitter of the bipolar transistor 63 has the main F
It is connected to the gate of ET10. The base of the bipolar transistor 63 is a Zener diode 61.
Is connected to the collector of the bipolar transistor 63 through a parallel circuit of Other configurations are the same as those in the first embodiment.

In the third embodiment thus configured, when ESD is applied from the load 20 to the semiconductor device,
The initial surge current flows through the series circuit 62 into the base of the bipolar transistor 63, and then the next surge current flows through the Zener diode 61 into the base of the bipolar transistor 63. The bipolar transistor 63 is turned on with these inflow currents.

Therefore, the next surge current passes through the bipolar transistor 63 and becomes the main FET as a charging current.
It flows directly into the ten gates.

In this case, since the bipolar transistor 63 has a current amplifying function, the gate of the main FET 10 is quickly charged.

As a result, the main FET 10 is turned on quickly and instantaneously, so that the final surge current flows without causing an avalanche break of the internal diode 11 or causing the operation of the internal transistor 13.

As a result, even without the auxiliary FET 41 as described in the first embodiment, the synergistic action of the series circuit 62 and the Zener diode 61 and the employment of the bipolar transistor 63 as in the third embodiment do. ,
The ESD tolerance of the semiconductor device can be sufficiently ensured.

Here, the portion between the emitter and the base of the bipolar transistor 63 plays a role similar to that of the backflow preventing zener diode 50. In other words, the bipolar transistor 63 inevitably has a built-in backflow preventing zener diode similar to the zener diode 50. Therefore, the backflow preventing zener diode 50 described in each of the above embodiments is employed. No need to do. Therefore, the above-described effects can be achieved while ensuring the reduction in the number of constituent elements of the semiconductor device.

The operation and effect of the third embodiment are described in comparison with the operation and effect of the protection device (see FIG. 23) described in Japanese Patent Application Laid-Open No. 8-64812. In the protection device described, its F
ET4a is connected between the gate and drain of FET2. Therefore, when the gate of the FET2 is biased by the gate drive circuit to turn on the FET2,
In order to prevent a current from flowing backward from the gate drive circuit to the drain side of the FET 2 through the FET 4a, the Zener diode 5 is necessarily connected between the gate of the FET 2 and the source of the FET 4a.

However, the backflow preventing Zener diode 5 always includes a parasitic resistance inside. For this reason, when the parasitic resistance is reduced, the size of the Zener diode 5 increases, which causes an increase in cost. Conversely, when the size of the Zener diode is reduced, the parasitic resistance increases, and the gate charging current of the FET 2 at the time of applying the ESD is reduced.
This causes a problem of lowering the SD tolerance.

Therefore, if the bipolar transistor 63 is employed as in the third embodiment, the above-described effects can be achieved while ensuring the reduction of the number of components such as the backflow preventing Zener diode.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.

In the fourth embodiment, the protection circuit 70
The protection circuit 40 described in the first embodiment (see FIG. 1)
Has been adopted instead.

The protection circuit 70 has a Darlington-connected 4
It has two LDMOS type FETs 71 to 74. F
The ET 71 has a drain connected to the drain of the main FET 10 described in the first embodiment, and a source connected to the gate of the main FET 10 through the Zener diode 50.

The drains of the remaining FETs 72 to 74 are all connected to the drain of the FET 71.
The source of ET72 is connected to the gate of FET71,
The source of ET73 is connected to the gate of FET72, and the source of FET74 is connected to the gate of FET73.

The resistor 75 is connected to the gate of the FET 71.
The resistor 76 is connected between the source and the gate of the FET 72, the resistor 77 is connected between the gate and the source of the FET 73, and the resistor 78 is connected between the gate and the source of the FET 74. Other configurations are the same as those of the first embodiment.

In the fourth embodiment configured as described above, when ESD is applied from the load 20 to the semiconductor device,
The initial surge current flows into the gate of the FET 74 of the protection circuit 70 via the series circuit 79. Accordingly, when the FET 74 is turned on, the initial surge current is
74 flows into the gate of the FET 73 through the
Turn on 3. Then, the initial surge current is
73, flows into the gate of the FET 72,
Turn on 2. Accordingly, the initial surge current becomes F
After flowing into the gate of the FET 71 through the ET 72, the FE
T71 is turned on.

When FET 71 is turned on in this way,
The next surge current flows into the gate of the main FET 10 through the FET 71 and the Zener diode 50.

Here, since the FETs 71 to 74 are Darlington-connected in four stages, the amplifying effect is large. Further, similarly to the first embodiment, no resistor is connected between the source of the FET 71 and the gate of the main FET 10, and only the Zener diode 50 is connected. Moreover, the internal resistance value of the Zener diode 50 is very small as described above.

Accordingly, the next surge current flowing through the FET 71 quickly flows into the gate of the main FET 10 through the Zener diode 50 without being throttled at all. This means that the next surge current instantaneously and sufficiently flows into the gate of the main FET 10 as a charging current.

As a result, the main FET 10 is turned on instantaneously, causing the avalanche break of the internal diode 11 and causing the operation of the internal transistor 13 without causing the final surge current following the next surge current of the ESD to flow. Let it.

As a result, it is possible to sufficiently secure the ESD resistance of the semiconductor device.

The slow surge current described in the first embodiment flows through each of the FETs 74 to 71 and the main FET 10.

As described above, as in the fourth embodiment, the first
Instead of the zener diode series circuit 43 and the capacitor 42 described in the embodiment and the series circuit 62 and the zener diode 61 described in the third embodiment, a three-stage F
Even when the ETs 74 to 72 are employed, the above-described functions and effects can be achieved in the same manner as in the first or second embodiment.

When the relationship between the number of FETs and the ESD breakdown voltage in the protection circuit 70 in the fourth embodiment was examined, the result shown in FIG. 8 was obtained. According to this, it is understood that the larger the number of FETs, the higher the ESD breakdown voltage, and therefore, the higher the ESD resistance of the semiconductor device. In particular, it can be understood that the effect rapidly increases at two or more stages and begins to saturate. (Fifth Embodiment) FIG. 9 shows a fifth embodiment of the present invention. In the fifth embodiment, the Zener diode series circuit 43 is different from the circuit described in the first embodiment.
, And a protection zener diode circuit 81 is newly added between the source and the drain of the auxiliary FET 41 to form a protection circuit 80. The same elements as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

As described above, the protection circuit 80 is a circuit composed of the capacitor 42 and the auxiliary FET 41 for protecting the ESD. The ESD speed is about several tens of ns
It is a very fast surge on the order of c and its frequency is on the order of GHz. The main F
In order to absorb the ET10, it is necessary to operate the auxiliary FET 41 at a high speed. For this reason, it is necessary to quickly inject a high-frequency surge into the gate of the auxiliary FET 41 using a capacitor of, for example, about 20 pF. However, in the case of such a capacitance value, in the case of a low-speed and low-frequency (for example, on the order of μsec, kHz) with respect to ESD, such as a load surge (for example, an L load surge due to inductive load interruption or the like), Before the auxiliary FET 41 is operated via the capacitor 42, a surge rises, and there is a possibility that the main FET 10 is destroyed by a transistor which is parasitic inside. In other words, the capacitor works disadvantageously for a low frequency surge.

Therefore, in the protection circuit 80, the protection zener diode circuit 81 is connected in parallel with the auxiliary FET 41, so that the protection zener diode circuit 81 performs an L load surge instead of the auxiliary FET 41.
The main FET 10 is operated before the L load surge rises to absorb the L load surge. Note that the ESD referred to in the present invention is a discharge condition of 150Ω and 150 pF.
Level, which lasts for several tens of nsec.
The load surge is assumed to be several A (for example, 3 A), 60 V, and a frequency of about 100 kHz.

The conditions under which the L load surge can be sufficiently absorbed by the main FET 10 will be described below.

The protection circuit 8 viewed from the gate of the main FET 10
0, the operating resistance of the protection unit including the Zener diode 50 is Rh, and the gate driving resistance 32 is Rd.
The condition d> Rh is preferred. This is because, when the Zener diode breaks down due to the L load surge and a current also flows into the gate drive resistor Rd, the voltage drop at the gate drive resistor can drive the main FET 10 sufficiently (for example, the threshold voltage Vth (3 times).

Similarly, in order to absorb the ESD, the main FE
In order to operate T10, the main F
It is preferable that the above-mentioned condition of Rd> Rh is satisfied, because the voltage drop generated in the drive resistor 32 by the next surge flowing to the control terminal of the ET 10 becomes sufficiently larger than the threshold value of the main FET 10.

FIG. 10 shows a sixth embodiment of the present invention.

In the sixth embodiment, the capacitor 42 described in the first embodiment is formed by a layout as shown in FIG.

FIG. 10 shows the plane of the capacitor 42 in the sixth embodiment. One electrode (consisting of a deep n ⁺ -type diffusion layer) forming the capacitor 42 is
Between the other electrode (made of polysilicon)
As shown in FIG. 10, the number of contacts 42a of one electrode and the number of contacts 42b of the other electrode are increased as compared with the conventional configuration (see FIG. 11).

As a result, the parasitic resistance of capacitor 42 can be reduced as much as possible, and as a result, the effect of capacitor 42 in FIG. 1 can be further improved. (Seventh Embodiment) FIG. 12A shows a seventh embodiment of the present invention.

In the seventh embodiment, the resistor 44 described in the first embodiment is different from the first embodiment,
It is connected between the gates of both FETs 10 and 46. The FET 46 is the same as the FET 4 described in the first embodiment.
Equivalent to 1.

According to this, the initial surge current is FE
When trying to flow into the drain of T46, the initial surge current flows into the gate of the FET 46 via the capacitor 42 and charges the gate. Accordingly, when the potential of this gate is charged to a value equal to or higher than the threshold value, the FET 46
Is turned on. Next, the FET connected to the source of the FET 46 through the Zener diode 50
A current is injected into the gate of No. 10.

When the gate potential of the FET 10 is charged to a value equal to or higher than the threshold value, the FET 10 enters an ON operation state, and more surge current flows. That is, FET1
Since a surge current can flow through the ON operation of 0, the operation of the parasitic bipolar transistor can be prevented, and the ESD surge resistance can be improved.

However, the resistor 44 functions as a pull-down resistor of the FET 46, discharges the gate charge of the FET 46, and turns off the FET 46.

Incidentally, the two Fs described in the seventh embodiment are used.
The ETs 10 and 46 have a planar structure and a cross-sectional structure as shown in FIGS.

As a result, both FETs 10 and 46 can be manufactured in the same step, so that there is no increase in steps. In addition, since such a structure is common, description is abbreviate | omitted.

FIG. 12B shows a modification of the seventh embodiment.

In this modification, both Zener diodes 45a, 45b connected in series with opposite polarities are
In the above-described seventh embodiment, F
It is connected between the gate and drain of ET46. The anode of the Zener diode 45b is connected to the FET 46.
Connected to the gate.

According to this modification, when the initial surge current flows into the drain of the FET 46, the two Zener diodes 45a and 45b first break, causing the initial surge current to flow into the gate of the FET 46 and charge. I do. Accordingly, the FET 46 enters an ON operation. Therefore, the gate of the main FET 10 is charged, and the main FET 10 is charged.
Under the ON operation of No. 10, the final surge current is
10 can flow through. This also achieves substantially the same functions and effects as in the seventh embodiment. (Eighth Embodiment) FIG. 14 shows an eighth embodiment of the present invention. The eighth embodiment uses a main FE formed on a semiconductor substrate.
The pattern diagram of T10 is shown. This is drain 6
A gate lead-out Al wiring 62 is formed so as to surround this cell region 65 with respect to a cell region 65 composed of a plurality of single cells composed of 0 and source 61.

The gate lead-out Al wiring 62 is insulated from the polysilicon layer as a gate electrode via an insulating film, and is connected to the polysilicon layer by a gate poly-Si contact 66. The width of the gate lead-out Al wiring 62 is larger than that of the wiring 63 connected to the Zener diode 50 and the wiring 64 connected to the source electrode of the auxiliary FET 41. This configuration is preferable because the main FET 10 can be driven instantaneously even when an ESD or L load surge is applied.

FIG. 15A shows a ninth embodiment of the present invention.

In the ninth embodiment, the bipolar transistor 46A is the same as the FET 46 and the Zener diode 50 in the seventh embodiment (see FIG. 12A).
Has been adopted instead.

The bipolar transistor 46A has its emitter connected to the gate of the main FET 10, and the collector of the bipolar transistor 46A is connected to the drain of the main FET 10. The base of the bipolar transistor 46A is connected via the capacitor 42 to the collector of the bipolar transistor 46A.

According to the ninth embodiment configured as described above, the next surge current is supplied to the bipolar transistor 46.
When flowing into the collector of A, this next surge current flows through the capacitor 42 and the bipolar transistor 46
A flows into the base of A. Thereby, the base-emitter junction capacitance of the bipolar transistor 46A is charged. When the base potential of the bipolar transistor 46A becomes equal to or higher than the diffusion potential (about 0.6 V), the bipolar transistor 46A enters an ON operation state. Then
The next surge current is injected into the gate of the main FET 10 connected to the emitter of the bipolar transistor 46A.

Here, when the gate potential of the main FET 10 becomes higher than the threshold value, the main FET 10 enters an on-operation state, and the final surge current flows through the main FET 10 more.

That is, since the final surge current flows through the main FET 10 when the main FET 10 is turned on, the operation of the parasitic bipolar transistor of the main FET 10 can be prevented, and the ESD tolerance can be improved.

FIG. 15B shows a modification of the ninth embodiment.

In this modification, the Zener diodes 47a and 47b connected in series with opposite polarities are connected between the base and the capacitor of the bipolar transistor 46A instead of the capacitor 42 in the ninth embodiment. . The anode of the Zener diode 47b is connected to the base of the bipolar transistor 46A.

In this modified example, when the next surge current flows into the collector of the bipolar transistor 46A, the next surge current flows into both Zener diodes 47a and 47b to break the Zener diode 47b. Therefore, the next surge current charges the base-emitter junction capacitance of the bipolar transistor 46A. Accordingly, the bipolar transistor 46A enters an ON operation state. Then, Lord F
ET10 is charged at its gate and enters the ON state,
Therefore, the final surge current can flow through the main FET 10. This also achieves the same effects as the ninth embodiment. (Tenth Embodiment) FIG. 16A shows a tenth embodiment of the present invention.

In the tenth embodiment, the MOSFET 4
7 and the resistor 47a are additionally employed in the protection circuit (see FIG. 12A) described in the seventh embodiment.

The FET 47 has the drain connected to the FET 4
The source of the FET 47 is connected to the gate of the FET 46. Also, FE
The gate of T47 is connected to the FET through the capacitor 42.
It is connected to the drain of the FET 47 and to the gate of the FET 46 via the resistor 47a. Other configurations are the same as those in the seventh embodiment.

In the tenth embodiment thus configured, the FET 47 is charged at its gate by the capacitor 42, whereas the FET 46 is charged at its gate by the FET 47 that has been turned on. Therefore, the gate voltage of the FET 46 can be increased to a higher voltage.

Therefore, more current can flow through the main FET 10. As a result, the bias voltage of the gate of the main FET 10 is further increased.
The maximum value of the drain saturation current accompanying the ON operation of 0 also becomes larger. Thereby, according to the eighth embodiment, the ES
D tolerance can be further improved. Note that the ESD resistance can be further improved by further increasing the number of FETs in the protection circuit.

FIG. 16B shows a modification of the tenth embodiment.

In this modification, the Zener diode 48 is connected to the capacitor 4 described in the tenth embodiment.
2 is connected between the gate and the drain of the FET 47.

As a result, in this modification, the FET 47
However, unlike the eighth embodiment, the gate is charged by the Zener diode 48.
Since the FET 46 is still charged by the FET 47 that has been turned on at its gate, similarly to the eighth embodiment, the same operation and effect as those of the tenth embodiment can be achieved by this modification. it can. (Eleventh Embodiment) FIG. 17A shows an eleventh embodiment of the present invention.

In the eleventh embodiment, the bipolar transistors 47A and 46B are used in place of the FETs 47 and 46 in the tenth embodiment (see FIG. 16A).

Bipolar transistor 47A has its collector connected to the gate of main FET 10 via the collector and emitter of bipolar transistor 46B. The base of the bipolar transistor 47A is connected to the bipolar transistor 47 via the capacitor 42.
Connected to A collector. Note that the zener diode 50 has been eliminated. Other configurations are the same as in the tenth embodiment.

In the eleventh embodiment configured as above, since the bipolar transistors 47A and 46B are so-called Darlington-connected, it is possible to sufficiently amplify the initial surge current flowing through the capacitor.
Therefore, the gate potential of the main FET 10 can be further increased. Therefore, since the drain saturation current of the main FET 10 can be further increased, according to the eleventh embodiment, the ESD resistance can be further improved. If the number of bipolar transistors is further increased,
The ESD resistance can be further improved. Also, the combination of a bipolar transistor and an LDMOS-type FET can similarly improve the ESD resistance.

In the eleventh embodiment, the Zener diode 50 is eliminated in consideration of the diode between the base and the emitter of the bipolar transistor, which is utilized.

FIG. 17B shows a modification of the eleventh embodiment.

In this modification, the Zener diode 48 described in the modification of the tenth embodiment (see FIG. 16B) is different from the eleventh embodiment in that the bipolar transistor 47A is used instead of the capacitor 42 in the eleventh embodiment. Is connected between the base and the collector.

As a result, in this modification, the bipolar transistor 47A is charged at its base by the Zener diode 48, unlike the eleventh embodiment, but the bipolar transistor 46B is
As in the eleventh embodiment, the base is charged by the bipolar transistor 47A that has been turned on, so that the same operation and effect as in the eleventh embodiment can be achieved by this modification. it can. (Twelfth Embodiment) FIG. 18A shows a twelfth embodiment of the present invention.

In the twelfth embodiment, the Zener diode 50 described in the first embodiment is improved in its structure for the following reasons.

Conventionally, a Zener diode has an npn emitter-base breakdown voltage (about 8
V). That is, by short-circuiting the collector and base of the transistor, the base is used as the anode, the emitter is used as the cathode, and the n-type region and the p-type element isolation region of the collector are used in a reverse-biased state (FIG. 18B )reference).

Therefore, according to such a configuration, an unnecessary collector region is originally required in the Zener diode for isolation between elements, and there is a problem that an extra space is devoted to the collector region.

For this reason, in the twelfth embodiment, the collector region, which is an extra component in the conventional Zener diode, is utilized by utilizing the feature of the insulation separation method that the potential of the n-type substrate can be used in a floating state. From FIG.
As shown in FIG. 3A, the Zener diode 50 is provided after being abolished. This means that a Zener diode having a higher area efficiency is provided as the Zener diode 50 in achieving the operation and effect of the first embodiment.

FIG. 19 shows a modification of the twelfth embodiment.

In this modification, as shown in FIG. 19, in the Zener diode 50 described in the twelfth embodiment, in order to reduce the parasitic series resistance, the layout in which the base-emitter facing length is extended is used. In particular, there is provided a configuration in which the cathode and the anode are formed of both the first layer and the second layer of aluminum wiring to reduce the resistance.

In this modification, the emitter-base contact of the Zener diode 50 is
As shown in FIG. 20A, the layout may be alternately arranged vertically and horizontally like a checkered pattern, or as shown in FIG. .

When the ESD tolerance of the protection circuit described in each of the above embodiments was examined, the result shown in FIG. 21 was obtained.

However, in FIG. 21, ZD indicates the case where a Zener diode is used in the protection circuit,
p. Shows a case where a capacitor is used in the protection circuit, and ZD / LD shows a case where a Zener diode and an auxiliary MOSFET (FET 41) are used in the protection circuit.

Cap. / LD indicates the case where a capacitor and an auxiliary MOSFET (FET 41) are used in the protection circuit, and ZD / Bip. Shows a case where a Zener diode and a bipolar transistor are used in the protection circuit, and cap / Bip. Shows a case where a capacitor and a bipolar transistor are used in the protection circuit, and ZD / LD / LD shows a case where a Zener diode and auxiliary MOSFETs (FETs 46 and 47) are used in the protection circuit.

In addition, cap. / LD / LD is a capacitor, an auxiliary MOSFET (FET46,
47) is shown, and ZD / Bip. / Bip.
Shows a case where a Zener diode and a bipolar transistor (46, 47A) are used in the protection circuit.
cap / Bip. / Bip. Shows a case where a capacitor and a bipolar transistor (46B, 47A) are used in the protection circuit. “None” indicates a case where the above element is not used in the protection circuit. That is, the main FET1
0 alone.

According to this, each ESD tolerance is shown by each bar graph.

In implementing the present invention, the MOSFET described in each of the above embodiments is not limited to an LDMOS.
VDMOS may be used. Further, the MOSFET may be of an isolation type (SOI / trench isolation type) or a junction isolation type.

In implementing the present invention, the aforementioned M
The OSFET may be a so-called IGBT.

Although the above description has been made in the form of a so-called low-side switch in which the load is arranged on the drain side,
Similar effects can be expected in the case of a high-side switch in which a load is arranged on the source side.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

2A is a timing chart showing an ESD waveform and an operation timing of the protection circuit of FIG. 1, and FIG. 2B is a timing chart of an ESD breakdown voltage and a resistance for explaining the operation and effect of the first embodiment. It is a graph which shows a relationship.

FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a graph showing a relationship between an ESD breakdown voltage and a capacitance of a capacitor 62b according to the second embodiment.

FIG. 5 is a graph showing a change in a gate charging current in the second embodiment.

FIG. 6 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing a fourth embodiment of the present invention.

FIG. 8 shows an ESD breakdown voltage and F in the fourth embodiment.
It is a graph which shows the relationship with the number of ET.

FIG. 9 is a circuit configuration diagram showing a fifth embodiment of the present invention.

FIG. 10 is a plan view showing an improved configuration of the capacitor of FIG. 1 showing a sixth embodiment of the present invention.

FIG. 11 is a plan view showing a conventional configuration of a capacitor 42.

FIG. 12A is a circuit diagram showing a seventh embodiment of the present invention, and FIG. 12B is a circuit diagram showing a modification of the seventh embodiment.

FIG. 13A is a diagram showing a seventh embodiment of the present invention;
FIG. 2A is a partial plan view, and FIG.
FIG. 13 is a sectional view taken along line 13b-13b.

FIG. 14 is a pattern diagram of a main FET formed on a semiconductor substrate according to an eighth embodiment of the present invention.

FIG. 15A is a circuit diagram showing a ninth embodiment of the present invention, and FIG. 15B is a circuit diagram showing a modification of the ninth embodiment.

FIG. 16A is a circuit diagram showing a tenth embodiment of the present invention, and FIG. 16B is a circuit diagram showing a modification of the tenth embodiment.

FIG. 17A is a circuit diagram showing an eleventh embodiment of the present invention, and FIG. 17B is a circuit diagram showing a modification of the eleventh embodiment.

FIG. 18A is a plan view of a Zener diode 50 showing a twelfth embodiment of the present invention, and FIG. 18B is a plan view of a conventional Zener diode.

FIG. 19 is a plan view showing a modification of the twelfth embodiment.

FIG. 20 (a) is a plan view showing another modification of the twelfth embodiment, and FIG. 20 (b) is a plan view showing another modification of the twelfth embodiment.

FIG. 21 is a graph showing the relationship between the components of the protection circuit described in any one of the embodiments and the modifications and the ESD tolerance.

FIG. 22 is a circuit configuration diagram of a conventional semiconductor device.

FIG. 23 is a circuit configuration diagram of another conventional semiconductor device.

[Explanation of symbols]

10, 41, 46, 71 to 74 ... FET, 40, 6
0, 60A, 70, 80: protection circuit, 42, 62b: capacitor, 45a, 45b, 47a, 47b, 48, 5
0, 61 ... Zener diode, 46A, 46B, 47
A, 63: Bipolar transistor.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AC05 AR09 BH02 BH03 BH04 BH06 BH07 BH12 BH13 EZ01 EZ20 5F040 DA19 DB01 DB06 DB07 DB09 DC01 EK01 EK05 5F048 AA02 AB06 AC08 AC10 BA16 BE03 BG12 BG14 CC01 CC05 CC06 CC06

Claims (21)

[Claims] 1. A protection device for protecting a main transistor (10) formed on a semiconductor substrate from high-speed surge, comprising: a backflow preventing Zener diode (50) having a cathode directly connected to a control terminal of the main transistor; A protection transistor (41) having an output terminal and an input terminal connected to the anode of the zener diode and the input terminal of the main transistor, respectively, between a control terminal of the protection transistor and an input terminal of the main transistor; And a protection capacitor (42) connected to allow an initial surge current generated based on the high-speed surge to flow into a control terminal of the protection transistor, wherein the protection transistor is turned on by the flow of the initial surge current. Generated following the initial surge current based on the high-speed surge. The next surge current flows into the control terminal of the main transistor through the reverse current blocking Zener diode.When the main transistor is turned on by the inflow of the next surge current, the main transistor follows the next surge current based on the high-speed surge. A protective device for a semiconductor device, characterized in that a final surge current generated by the flow is caused to flow. 2. A protection device for protecting a main transistor (10) formed on a semiconductor substrate from high-speed surge, comprising: a backflow preventing Zener diode (50) having a cathode directly connected to a control terminal of the main transistor; A protection transistor (46) having an output terminal and an input terminal connected to the anode of the Zener diode and the input terminal of the main transistor, respectively, between a control terminal of the protection transistor and an input terminal of the main transistor; A Zener diode circuit (45a, 45a, which is connected to allow an initial surge current generated based on the high-speed surge to flow into a control terminal of the protection transistor.
45b, 48), the protection transistor, when turned on by the initial surge current, passes the next surge current generated subsequent to the initial surge current based on the high-speed surge through the reverse current blocking Zener diode. The main transistor is caused to flow into a control terminal of the main transistor, and the main transistor, when turned on by the next surge current, flows a final surge current generated subsequent to the next surge current based on the high-speed surge. Protection device for semiconductor devices. 3. The protection device for a semiconductor device according to claim 1, wherein the main transistor and the protection transistor are MOS FETs. 4. An auxiliary protection transistor connected between the protection transistor and the protection capacitor and amplifying the initial surge current and flowing into a control terminal of the protection transistor. Claim 1
3. A protection device for a semiconductor device according to claim 1. 5. An auxiliary protection transistor connected between the protection transistor and the Zener diode circuit and amplifying the initial surge current and flowing to a control terminal of the protection transistor. A protection device for the semiconductor device according to claim 2. 6. The protection device for a semiconductor device according to claim 4, wherein the main transistor and the protection and auxiliary protection transistors are MOS FETs. 7. The protection device for a semiconductor device according to claim 1, wherein the protection transistor has a built-in Zener diode for a reverse current element. 8. The protection device for a semiconductor device according to claim 2, wherein the protection transistor has a built-in Zener diode for a reverse current element. 9. A protection zener diode connected in parallel with the protection capacitor, wherein a current flowing through the protection capacitor is a first initial surge current, and a current flowing through the protection zener diode is a first initial surge current. The protection device for a semiconductor device according to claim 1, wherein the protection device is a second initial surge current subsequent to the initial surge current. 10. The protection device for a semiconductor device according to claim 7, wherein said main transistor is a MOSFET, and said protection transistor is a bipolar transistor. 11. The protection device for a semiconductor device according to claim 4, wherein the protection transistor has a built-in Zener diode for a reverse current element. 12. The protection device for a semiconductor device according to claim 5, wherein said protection transistor has a built-in Zener diode for a reverse current element. 13. The protection device for a semiconductor device according to claim 11, wherein the main transistor is a MOSFET, and the protection and auxiliary protection transistors are bipolar transistors. 14. A protection device formed on a semiconductor substrate to protect a main transistor (10) from high-speed surge, comprising: a backflow preventing Zener diode (50) having a cathode connected to a control terminal of the main transistor; A protective Zener diode (6) having an anode and a cathode respectively connected to the anode of the backflow preventing Zener diode and the input terminal of the main transistor.
1); and a protection capacitor (62b) connected in parallel with the protection zener diode and allowing an initial surge current generated based on the high-speed surge to flow into the control terminal of the main transistor through the backflow prevention zener diode. The protection zener diode causes the next surge current generated subsequent to the initial surge current based on the high-speed surge to flow into the control terminal of the main transistor through the backflow prevention zener diode; A protection device for a semiconductor device, characterized in that when turned on due to inflow of a surge current and a next surge current, a final surge current generated subsequent to the next surge current flows based on the high-speed surge. 15. A protection device for protecting a main transistor (10) formed on a semiconductor substrate from high-speed surge, comprising: a backflow preventing Zener diode (50) having a cathode connected to a control terminal of the main transistor; A protection transistor in which a plurality of transistors (71 to 74) having an output terminal and an input terminal respectively connected to the anode of the backflow preventing Zener diode and the input terminal of the main transistor are Darlington-connected as first and subsequent stage transistors. The protection transistor circuit, wherein the protection transistor circuit turns on the subsequent-stage transistor by an initial surge current generated based on a high-speed surge, and turns on the first-stage transistor with the turning-on of the first-stage transistor; Turns on the high-speed server The next surge current generated subsequent to the initial surge current flows into the control terminal of the main transistor based on the following. When the main transistor is turned on by the inflow of the next surge current, the next surge current is generated based on the high-speed surge. A protection device for a semiconductor device, characterized in that a final surge current generated following the current flows. 16. The protection device for a semiconductor device according to claim 15, wherein each of said main transistor and each transistor of said protection circuit is a MOSFET. 17. A protection circuit connected in parallel to the protection transistor, wherein a current lead is connected to the input terminal of the main transistor, and an anode is connected to an anode of the backflow preventing zener diode. A main transistor for controlling a current supply to a load connected to an input terminal of the main transistor, and the load generates a load surge when the current is cut off. The high-speed surge is caused by electrostatic discharge, and the load surge has a smaller frequency than the high-speed surge. A breakdown occurs before a transistor is turned on by the protection capacitor, and the main transistor is turned off. Protection apparatus for a semiconductor device according to claim 1, characterized in that for. 18. The high-speed surge has a frequency of GHz.
The frequency of the load surge is kHz.
The protection device for a semiconductor device according to claim 17, wherein: 19. An operating resistance until the next surge current flows into the control terminal of the main transistor via the reverse current blocking Zener diode is set to Rh, and a path from a drive circuit for driving the main transistor is set to Rh. 18. The protection device for a semiconductor device according to claim 1, wherein Rd> Rh is satisfied, where Rd is the arranged driving resistance. 20. The operating resistance until the load surge current flows into the control terminal of the main transistor through the reverse current blocking Zener diode is Rh, and the operating resistance is a path from a drive circuit for driving the main transistor. 18. The protection device for a semiconductor device according to claim 17, wherein, when the disposed driving resistance is Rd, there is a relationship of Rd> Rh. 21. The main transistor is formed as a cell region having a plurality of single cells on the semiconductor substrate, and the control terminal of the main transistor is provided with a common terminal for each of the plurality of single cells. The terminal is drawn out of the cell region,
Outside the cell region, the cell region is connected to a signal application electrode formed on the surface of the semiconductor substrate so as to surround the cell region, and the signal application electrode has a cathode of the backflow preventing zener diode. 2. The protection device for a semiconductor device according to claim 1, wherein the connection width is wider than a wiring width from the cathode to the signal application electrode. 3.