JP2002135973A - Overvoltage protective circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect the main switching element from excessive surge voltage and excessive voltage change. SOLUTION: In parallel with the main switching element, this overvoltage protective circuit has an insulated gate semiconductor which changes its gate voltage following the voltage change across the main switching element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overvoltage protection technique for a power semiconductor device, and more particularly to an insulated gate semiconductor element such as a MOSFET, an insulated gate transistor (IGBT), and an electron injection promoting gate transistor (IEGT). The present invention relates to an overvoltage protection circuit and a protection method used.

[0002]

2. Description of the Related Art Power converters such as inverters using power semiconductor elements have been widely used for effective use of power energy. In recent years, their application fields have been further expanded.

[0003] In the flow, devices for controlling a higher voltage and a larger current by using a power semiconductor element to switch a current at a higher speed have been increasing. In these devices, a large current change (hereinafter, the degree of the current change is expressed by using a current change rate: dI / dt) occurs at the time of switching of the semiconductor element, so that a large surge voltage caused by a stray inductance of the circuit is generated. Applied to the device. If the current / voltage locus at the time of switching exceeds the safe operation area (SOA) of the semiconductor device due to the surge voltage, device breakdown occurs. It is also known that a large voltage change at the time of high-speed switching (hereinafter, the degree of the voltage change is expressed by using a voltage change rate: dV / dt) easily causes element destruction.

Conventionally, snubber circuits have been widely used to suppress element destruction due to surge voltage. In particular, I
A clamp-type snubber circuit (charge-type RCD snubber circuit) is used for a semiconductor element having a wide RBSOA such as a GBT. This has a capacitor charged to a power supply voltage, and absorbs energy stored in a floating inductance of a circuit by a snubber circuit when a voltage equal to or higher than the power supply voltage is applied to a semiconductor element. However, since a high-voltage capacitor is required, there is a problem that the volume and cost of the apparatus increase. In addition, because of the cross-shaped configuration, there is a problem that it cannot be connected to each semiconductor element connected in series. As techniques for solving this, JP-A-2000-12780, JP-A-20
The technology disclosed in 00-92817 is exemplified.
These clamp a surge voltage to a predetermined voltage and, at the same time, connect a semiconductor snubber circuit that absorbs energy stored in the floating inductance of the circuit in parallel with the main switching element. These semiconductor snubber circuits are small in size, can be inserted into the same package as the main switching element, and can protect each of the semiconductor elements connected in series from overvoltage.

However, these devices bypass the energy stored in the floating inductance only when performing the overvoltage clamping operation, and do not perform any protection operation before the voltage reaches a predetermined clamp voltage.
That is, the main switching element cannot be protected from destruction due to a large voltage change (rate) (= dV / dt) during switching of the semiconductor element.

[0006]

As described above, the conventional overvoltage protection circuit has a problem that it is impossible to prevent both destruction due to an excessive surge voltage and destruction due to an excessive voltage change (rate). SUMMARY OF THE INVENTION An object of the present invention is to provide an overvoltage protection circuit that is effective for destruction due to an excessive voltage change (rate) (= dV / dt).

[0007]

According to the present invention, there is provided an insulated gate semiconductor device in which a gate voltage changes according to a voltage change of a main switching element, in parallel with the main switching element. When an overvoltage or an excessive voltage change (rate) (= dV / dt) occurs, the main switching element can be protected by making the insulated gate semiconductor element bypass the current.

That is, the overvoltage protection circuit according to the present invention comprises:
An overvoltage protection circuit comprising an insulated gate semiconductor element having a high voltage side main electrode, a low voltage side main electrode, and a gate electrode, connected in parallel with a main switching element, wherein the gate electrode and the low voltage side main electrode And a gate resistor.

Further, a DC power supply for applying a negative bias to the gate electrode is connected in series with the gate resistor.

In addition, the gate resistor or the gate resistor connected in series and the DC power supply are connected in series between the gate electrode and the low-voltage side main electrode of the insulated gate semiconductor device with the polarities reversed. Wherein the Zener diode is connected.

At least one of the main switching element and a control circuit for supplying an input signal to a control electrode thereof has a device current detecting function, and the gate resistance in the protection circuit is determined based on the detected device current value. A protection circuit control circuit for controlling at least one of the negative bias is provided.

A second insulated gate semiconductor element having a high voltage side main electrode and a low voltage side main electrode connected to the high voltage side main electrode and the gate electrode of the insulated gate type semiconductor element, respectively; A second gate resistor is connected between the gate electrode and the low-voltage-side main electrode of the second insulated gate semiconductor device.

A DC power supply for applying a negative bias to a gate electrode of the second insulated gate semiconductor device is connected in series with the second gate resistor.

At least one of the main switching element and a control circuit for supplying an input signal to a control electrode thereof has a device current detecting function, and the first circuit in the protection circuit based on the detected device current value. A protection circuit control circuit controls at least one of a gate resistance and a negative bias of the insulated gate semiconductor element, and a gate resistance and a negative bias of the second insulated gate semiconductor element.

Further, the present invention is characterized in that the area of the current-carrying part of the first insulated gate semiconductor element is larger than the area of the current-carrying part of the second insulated gate semiconductor element.

Further, the first and second insulated gate semiconductor elements are formed in the same substrate.

Further, the gate electrode structure of the first insulated gate semiconductor device is different from the gate electrode structure of the second insulated gate semiconductor device.

The value of the ratio of the parasitic capacitance (capacitance) between the high-voltage side main electrode and the gate electrode to the low-voltage side main electrode and the gate electrode of the first insulated gate semiconductor device is the same as that of the first insulated gate semiconductor device. 2 is characterized in that the ratio of the parasitic capacitance between the high voltage side main electrode and the gate electrode to the parasitic capacitance between the low voltage side main electrode and the gate electrode of the insulated gate type semiconductor element is larger than the value of the ratio.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows an example of an embodiment of the present invention. IG which is the main switching element 1
The BT performs a switching operation by the control circuit 2 connected between the gate electrode terminal G and the emitter electrode terminal E (hereinafter, the main switching element 1 is referred to as IGBT1). An overvoltage protection circuit 100 including an insulated gate semiconductor element 10 is connected between two main electrodes (C (collector electrode terminal) and E) of the IGBT 1. The insulated gate semiconductor element 10 has a withstand voltage equivalent to that of the main switching element 1 and uses an IGBT here (hereinafter, referred to as an IGBT).
The insulated gate semiconductor element 10 is referred to as IGBT 10).
The collector electrode and the emitter electrode of the IGBT 10 are connected to the collector electrode terminal C and the emitter electrode terminal E of the IGBT 1, respectively, and the gate electrode of the IGBT 10 is connected to the emitter electrode via a gate resistor 11 and a DC power supply 12. However, the DC power supply 12 is in the direction of reversely biasing the gate electrode. Further, zener diodes 13 and 14 connected in series with opposite polarities are connected between the gate electrode and the emitter electrode of the IGBT 10.

Next, the operation of the overvoltage protection circuit 100 according to the present embodiment will be described with reference to FIGS. FIG.
1 schematically shows a unit cell cross-sectional view of the IGBT 10 used in the overvoltage protection circuit 100. Low concentration of n
A high concentration p-type emitter layer 22 and a collector electrode 23 are formed on one surface of the mold base layer 21. Low concentration of n
A p-type base layer 24 is selectively formed on the other surface of the mold base layer 21, and a high-concentration n-type source layer 25 is selectively formed on the surface of the p-type base layer 24. The surface of the p-type base layer 24 sandwiched between the low-concentration n-type base layer 21 and the high-concentration n-type source layer 25 and the low-concentration n-type base layer 2
The gate electrode 27 is provided on the surface of
Are formed, and an emitter electrode 28 is formed so as to be in contact with both the p-type base layer 24 and the high-concentration n-type source layer 25.

In the IGBT 10, when a positive voltage is applied to the collector electrode 23 and the emitter electrode 28,
A depletion layer expands from the junction between the p-type base layer 24 and the low-concentration n-type base layer 21, but with this and the gate insulating film 26 interposed between the collector electrode 23 and the gate electrode 27, the gate electrode 27 and the emitter electrode. 28, there are parasitic capacitances Ccg and Cge, respectively.

When the IGBT 10 in the energized state interrupts the collector current Ic by a zero or negative control signal, the induced electromotive force Ls · dI in the floating inductance Ls of the circuit.
c / dt occurs. If there is no overvoltage protection circuit 100,
This induced electromotive force is applied to the IGBT 1 as a surge voltage, and the current / voltage trajectory has a reverse bias safe operation area (RB
If SOA) is exceeded, device destruction occurs. If the voltage change (rate) (= dV / dt) exceeds the allowable value of the element, the element is destroyed.

However, in the present embodiment, as shown in FIG. 2, a displacement current is generated in Ccg of the IGBT 10 due to the value of the voltage change rate (= dV / dt) in the voltage rise, and the gate resistance 11 and the parasitic capacitance are generated. Flow into Cge. As a result, the gate voltage Vge increases, and when the gate voltage Vge reaches the threshold value Vth, the IGBT 10 is turned on. For this reason, a part of the current flowing through the IGBT 1 is bypassed to the IGBT 10. Therefore, by making the gate resistance 11 sufficiently large, the cutoff operation (voltage) at a low voltage change (rate) (= dV / dt) is performed. Clamp operation)
And the current can be cut off with a small surge voltage.

However, the gate resistance 11 is, for example, several k
Ω and may exceed the gate breakdown voltage of the IGBT 10 due to the displacement current of the parasitic capacitance Ccg.
Therefore, by connecting a Zener diode 13 having a Zener voltage of several volts to several tens of volts between the gate and the emitter, unnecessary displacement current is bypassed. Further, the zener diode 14 in the anti-series has a zener voltage slightly larger than the reverse bias value by the DC power supply 12, and the IGBT 1 is turned on when the IGBT 1 is turned on.
This is for preventing the overvoltage in the reverse direction from being applied to the ten gate electrodes.

The DC power supply 12 controls the time until the gate voltage Vge reaches the threshold value Vth. This is because, by reverse biasing the gate, a p-type inversion layer is formed in the low-concentration n-type base layer 21 immediately below the gate insulating film 26 immediately after the turn-off when the collector voltage is small, and the gate electrode 27 This is because it can be shielded from change.

FIG. 4 is a waveform example when this embodiment is applied. Since the overvoltage is suppressed and the current is bypassed to the (overvoltage) protection circuit 100, the current can be interrupted in the RBSOA of the main switching element 1 (= IGBT1). Further, it was confirmed that the overvoltage protection operation was more reliably performed when the surge voltage at the time of turn-off was larger and when the voltage change (rate) (= dV / dt) was larger.

(Second Embodiment) FIG. 5 is a circuit diagram showing a second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals. The difference from the first embodiment is that the DC power supply 12 is not provided, and therefore, the Zener diode 14 is not required. However,
In the insulated gate semiconductor element 10 (= IGBT 10), as shown in FIG. 6, a low-concentration p-type shield layer 29 may be formed in a low-concentration n-type base layer 21 immediately below a gate insulating film 26. desirable.

(Third Embodiment) FIG. 7 is a circuit diagram showing a third embodiment. In the present embodiment, control for the overvoltage protection circuit that can control at least one of the gate resistance 11 in the overvoltage protection circuit 100 and the reverse bias value of the DC power supply 12 according to the cutoff current of the IGBT 1 that is the main switching element 1 The circuit 200 is provided. The breaking current value is given from a program of the control circuit 2. If the breaking current value is small and overvoltage protection is not required, the DC power supply 1
IGBT by increasing the reverse bias due to
It is possible to control so that the gate voltage of No. 10 does not reach the threshold value Vth so that the voltage clamping operation does not occur. Alternatively, the gate resistance 11 is reduced and the IGB
Even if the current is bypassed at T10, the voltage change (rate) (=
dV / dt) can be controlled so as not to decrease.

(Fourth Embodiment) FIG. 8 is a circuit diagram showing a fourth embodiment. In the present embodiment, the third
Is a modification of the embodiment, wherein the overvoltage protection circuit 1 is switched in accordance with the breaking current of the IGBT 1 which is the main switching element 1.
00, a control circuit 200 for an overvoltage protection circuit capable of controlling at least one of a reverse bias value of the DC power supply 12 and a gate resistance 11 in the DC power supply 00, and a control circuit 2 for the overvoltage protection circuit.
The control method by 00 is the same. However, it is characterized in that the main switching element 1 (= IGBT1) has the emitter sense electrode terminal ES, and the cutoff current value is given to the overvoltage protection circuit control circuit 200 by the voltage drop of the current detection resistor 3.

(Fifth Embodiment) FIG. 9 is a circuit diagram showing a fifth embodiment. The overvoltage protection circuit 100 is 2
Two insulated gate semiconductor devices, ie, IGBTs 10a, I
It is composed of a GBT 10b. The collector electrode and the emitter electrode of the IGBT 10a are connected to the collector electrode and the emitter electrode of the IGBT 1 as the main switching element 1, respectively, and the gate resistor 11a is connected between the gate electrode and the emitter electrode of the IGBT 10a. The collector electrode and the emitter electrode of the IGBT 10b are
Each is connected to a collector electrode and a gate electrode of the IGBT 10a, and between a gate electrode and an emitter electrode of the IGBT 10b, a series-connected gate resistor 11b and a DC power supply 12b, and zener diodes 13b and 14b connected in series with opposite polarities. And are connected in parallel. However,
The DC power supply 12b is in the direction of reverse biasing the gate electrode of the IGBT 10b, the Zener voltage of the Zener diode 13b is slightly larger than the gate threshold voltage Vth of the IGBT 10b, and the Zener voltage of the Zener diode 14b is smaller than the reverse bias value of the DC power supply 12b. Set to a slightly larger value. Further, the gate resistance 11b has a resistance value several orders of magnitude larger than the gate resistance 11a.

The operation of the circuit used in this embodiment will be described below.

When the IGBT 1 as the main switching element 1 turns off the current Ic, the collector voltage rises (=
dV / dt), the IGBT 10a and the IGBT 10
A displacement current is generated in the collector-gate parasitic capacitance Ccg of b, and the respective gate-emitter parasitic capacitances Cge are charged. Which of the gate voltages of the IGBT 10a and the IGBT 10b first reaches the threshold value Vth depends on the gate resistance 11
a, 11b, reverse bias by the DC power supply 12b, and furthermore, the element structure of the gate resistors 10a, 10b. Assuming that the gate voltage of the IGBT 10a first reaches the threshold value Vth, a part of the current of the IGBT 1
Is bypassed. However, since the gate resistance 11a is not a large value, the collector voltage continues to rise without being clamped. Under conditions in which a large surge voltage occurs, such as when the cutoff current Ic is large, the gate voltage of the IGBT 10b also reaches the threshold Vth, and the presence of the large gate resistance 11b causes
A cutoff operation (voltage clamp operation) with a low voltage change (rate) (= dV / dt) can be obtained. At this time, IGBT1 is Ccg
Does not generate a sufficient displacement current, the IGBT 10a is kept off because the emitter current of the IGBT 10b is supplied as the gate current, and the IGBT 10a bypasses most of the current. That is, in the present embodiment, the IGBT 10a plays a role of bypassing the current of the IGBT1, and the IGBT 10b plays a role of clamping the voltage.

Further, the clamp voltage can be set by the DC power supply 12b independently of the bypass operation of the IGBT 10a.

(Sixth Embodiment) FIG. 10 is a circuit diagram showing a sixth embodiment. This embodiment is a modification of the fifth embodiment, and the overvoltage protection circuit 100 includes two insulated gate semiconductor devices IGBT10a and IGBT1.
0b is the same. The difference is
The point is that there is no DC power supply 12b for reverse-biasing the gate electrode of the IGBT 10b, and there are no two Zener diodes connected between the gate and the emitter of the IGBT 10b. Since the clamp voltage cannot be set by the DC power supply 12b, the IGBT 10b forms the low-concentration p-type shield layer 29 in the low-concentration n-type base layer 21 immediately below the gate insulating film 26, as shown in FIG. It is desirable to do. p
The clamp voltage can be set by the acceptor concentration of the shield layer 29. Also, as mentioned earlier,
The current capacity of the IGBT 10b may be sufficient to supply the gate current of the IGBT 10a. That is, the area of the IGBT 10b may be much smaller than the area of the IGBT 10a.
Accordingly, since the displacement current of the IGBT 10b is also small, the Zener diodes 13b, 14b
Can be eliminated. This is the same in the previous embodiment, and the zener diodes 13b and 14b shown in FIG. 9 need not be used.

(Seventh Embodiment) FIG. 11 is a circuit diagram showing a seventh embodiment. In the present embodiment,
The gate resistances 11a, 11a, 1
1b, a control circuit 200 for an overvoltage protection circuit capable of controlling at least one of the reverse bias values of the DC power supply 12b. The cutoff current value is given from a program of the control circuit 2. When the cutoff current value is small and overvoltage protection is not necessary, the reverse bias by the DC power supply 12b is increased so that the gate voltage of the IGBT 10a reaches the threshold value Vth. Therefore, control can be performed so that the voltage clamp operation does not occur. Alternatively, the gate resistors 11a, 11
By making b small, it is possible to control so that the voltage change (rate) (= dV / dt) does not decrease even when the current is bypassed to the IGBT 10a.

(Eighth Embodiment) FIG. 12 is a circuit diagram showing an eighth embodiment. This embodiment is a modification of the seventh embodiment. The gate resistor 11 in the overvoltage protection circuit 100 is changed according to the cutoff current of the IGBT 1.
a, 11b and the control circuit 200 for the overvoltage protection circuit capable of controlling at least one of the reverse bias values of the DC power supply 12b, and the control method by the control circuit 200 for the overvoltage protection circuit is the same. However, the IGBT 1 serving as the main switching element 1 has an emitter sense electrode terminal ES, and a cutoff current value is given to the overvoltage protection circuit control circuit 200 by a voltage drop of the current detection resistor 3.

Ninth Embodiment FIG. 13 is a schematic sectional view of an insulated gate semiconductor device used in a ninth embodiment, and corresponds to the overvoltage protection circuit 100 in FIG. I
The GBT 10a and the IGBT 10b are formed on the same semiconductor substrate, and the right side of the center dotted line in FIG. 13 constitutes 10a and the left side constitutes 10b. Each gate resistance 11
a and 11b may be connected by an external circuit, or may be formed of polycrystalline silicon or the like on a semiconductor substrate. As described above, the current capacity of the IGBT 10b is I
It only needs to supply the gate current of the GBT 10a,
The IGBT 10b is formed only on a part of the semiconductor substrate.

(Tenth Embodiment) FIG. 14 shows a tenth embodiment.
FIG. 11 is a schematic cross-sectional view of an insulated gate semiconductor element used in the embodiment, and corresponds to, for example, the overvoltage protection circuit 100 in FIG. This embodiment is characterized in that the IGBTs 10a and 10b formed on the same semiconductor substrate have different gate widths Lg1 and Lg2. When the gate width is increased, the parasitic capacitance Ccg between the collector and the gate, that is, the displacement current generated by an increase in the collector voltage (= dV / dt) is increased. Gate-emitter parasitic capacitance Cge
The charging speed depends on the gate resistance, but it can be said that the larger the ratio Ccg / Cge of the parasitic capacitance, the higher the speed. Therefore, by designing the gate widths of the IGBTs 10a and 10b to different values, the overvoltage protection circuit can be designed. Can be set in detail.

In particular, when protecting the main switching element from an excessive voltage change (rate) (= dV / dt) at the time of turn-off, the current flowing through the main switching element before the voltage clamping operation is started. Part of IGBT10
a. For this, I
Ccg / Cge of the GBT 10a may be made larger than Ccg / Cge of the IGBT 10b. However, this is the case where the area of the IGBT 10b is negligible compared to the area of the IGBT 10a, and if it cannot be ignored, the Ccg of the IGBT 10a is
It is necessary to add Ccg and Cce of GBT 10b.

When the IGBT 10b is turned on first,
As a result, the IGBT 1
0a is also instantly turned on. At this time, a large current change (rate) between the main switching element and the IGBT 10a (= dI / d
t) occurs, but there is a problem that noise is apt to occur with the occurrence of C), and Ccg / Cge of the IGBT 10a is changed to IGB.
Making it larger than Ccg / Cge of T10b is also effective for noise reduction. To do this, as shown in FIG.
Gate width Lg of each of IGBT 10a and IGBT 10b
1. Lg2 may be formed such that Lg1> Lg2.

(Eleventh Embodiment) FIG.
FIG. 11 is a schematic cross-sectional view of an insulated gate semiconductor device illustrating the embodiment, and corresponds to, for example, the overvoltage protection circuit 100 in FIG. 10. Further, it has the same effect as the tenth embodiment shown in FIG. IG on the left side of the center dotted line in FIG.
Regarding the gate insulating film (= gate oxide film) of the BT 10b,
A thick oxide film is formed in a portion on the surface of the low-concentration n-type base layer 21 that does not contribute to channel formation. As a result, the Ccg of the IGBT 10b, and consequently, the ratio Ccg / Cge of the parasitic capacitance is reduced.

By using a buried trench gate structure for these IGBTs, it is possible to design Ccg / Cge within a wider range.

In each of the embodiments described above, the IGBT has been described as the main switching element and the insulated gate semiconductor element in the overvoltage protection circuit. However, for example, even when a high withstand voltage element such as a high withstand voltage IGBT or an electron injection promoting gate transistor (IEGT) is used as the main switching element, as shown in FIG. 16 as an insulated gate semiconductor element in the overvoltage protection circuit. Alternatively, a high breakdown voltage power MOSFET 10c may be used. In general, the power MOSFET 10c with a high withstand voltage has a saturation voltage much larger than that of the IGBT and is hardly used in a withstand voltage region exceeding 1 kV. However, in the present invention, since the insulated gate semiconductor device 10 is used not in the saturation region but in the active region, the power MOSFET 10c having a high saturation voltage can be used. Thereby, cost can be reduced.

In each of the embodiments of the present invention, the overvoltage protection circuit uses a current-driven element such as a GTO thyristor as the main switching element 1 as shown in FIG. The present invention is also applicable to a case where a composite element such as the above is used.

(Twelfth Embodiment) FIG.
FIG. 3 is a circuit configuration diagram illustrating the embodiment. A freewheeling diode (hereinafter referred to as FWD) 4 is connected in parallel with the main switching element 1 whose control terminal is connected to a control circuit. Further, an overvoltage protection circuit 100 similar to that shown in the above embodiment is connected in parallel with the main switching element 1 and the FWD 4.

When the main switching element of another arm (not shown) is turned on while the FWD 4 is circulating the load current, the FWD 4 performs a reverse recovery operation. At this time, a surge voltage caused by the stray inductance Ls of the circuit is applied to the FWD 4, and the voltage rise (= dV / dt generation) causes the overvoltage protection circuit 100.
The insulated gate type semiconductor element in the inside operates, and the FWD 4 can be protected from overvoltage similarly to the protection of the main switching element 1. FIG. 19 schematically shows voltage and current waveforms at the time of reverse recovery of the FWD 4. However, the current waveform with (overvoltage) protection circuit is FW
This is the sum of the current of D4 and the current of the (overvoltage) protection circuit 100. As described above, by performing the voltage clamping operation after the reverse recovery current of the FWD 4 exceeds the peak value, a stable protection operation can be obtained.

(Thirteenth Embodiment) FIG. 20 shows a first embodiment in which the overvoltage protection circuit of the present invention is applied to a three-layer inverter circuit.
FIG. 14 is a circuit diagram illustrating a third embodiment. When the main switching element 1 is turned off and when the FWD 4 is subjected to reverse recovery, the overvoltage protection circuits 100 connected in parallel to each other.
Operates, excessive surge voltage and excessive voltage change (rate)
(= DV / dt).

[0049]

As described above, according to the present invention,
An overvoltage protection circuit capable of protecting the main switching element, the freewheeling diode, and the like from an excessive surge voltage and an excessive voltage change (rate) generated at the time of switching of the main switching element can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining the operation of the overvoltage protection circuit of the present invention.

FIG. 3 is an element cross-sectional view for explaining the operation of the overvoltage protection circuit of the present invention.

FIG. 4 is a waveform example when the overvoltage protection circuit of the present invention is applied.

FIG. 5 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 6 is an element cross-sectional view illustrating an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 12 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 13 is a cross-sectional view of an element showing an embodiment of the present invention.

FIG. 14 is an element cross-sectional view illustrating an embodiment of the present invention.

FIG. 15 is an element cross-sectional view illustrating an embodiment of the present invention.

FIG. 16 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 17 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 18 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 19 is a waveform example when the overvoltage protection circuit of the present invention is applied.

FIG. 20 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 21 is a circuit diagram showing a conventional clamp-type snubber circuit.

FIG. 22 is a circuit diagram illustrating a conventional overvoltage protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Main switching element 2 ... Control circuit 3 ... Current detection resistance 4 ... Reflux diode 10, 10a, 10b ... Insulated gate semiconductor element 10c ... Power MOSFET 11, 11a, 11b ... Gate resistance 12, 12b ... DC power supply 13, 13b , 14, 14b Zener diode 21 n-type base layer 22 p-type emitter layer 23 collector electrode 24 p-type base layer 25 n-type source layer 26 gate insulating film 27 gate electrode 28 emitter electrode 29 p-type shield layer 100: overvoltage protection circuit 200: control circuit for overvoltage protection circuit C: collector electrode terminal E: emitter electrode terminal ES: emitter sense electrode terminal G: gate electrode terminal

Continuing from the front page (72) Inventor Tsuneo Ogura 1-term, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Microelectronics Center Co., Ltd. 5G013 AA02 AA16 BA02 CB02 DA05 DA10 DA11 5G053 AA09 BA04 CA05 EA09 EB02 EC03 5H007 CA01 CB02 CB05 CB06 FA01 FA13 FA20 5H740 BA11 BA16 BB01 BB05 BB07 BB08 BB10 MM01

Claims (12)

[Claims] 1. An overvoltage protection circuit comprising an insulated gate semiconductor element having a high voltage side main electrode, a low voltage side main electrode and a gate electrode, connected in parallel with a main switching element. An overvoltage protection circuit, wherein a gate resistor is connected between the overvoltage protection circuit and a voltage side main electrode. 2. The overvoltage protection circuit according to claim 1, wherein a DC power supply for applying a negative bias to said gate electrode is connected in series with said gate resistor. 3. A zener diode connected in series with a reverse polarity is connected between a gate electrode of the insulated gate semiconductor device and the low voltage side main electrode. 3. The overvoltage protection circuit according to 2. 4. At least one of the main switching element and a control circuit for supplying an input signal to a control electrode thereof has a device current detection function, and the gate resistance in the protection circuit is determined based on the detected device current value. 4. The overvoltage protection circuit according to claim 1, further comprising a protection circuit control circuit for controlling at least one of the negative bias. 5. A second insulated gate semiconductor device having a high voltage side main electrode and a low voltage side main electrode connected to a high voltage side main electrode and a gate electrode of the insulated gate semiconductor device, respectively. 3. The overvoltage protection circuit according to claim 1, wherein a second gate resistor is connected between the gate electrode of the second insulated gate semiconductor device and the low voltage side main electrode. 6. The overvoltage protection according to claim 5, wherein a DC power supply for applying a negative bias to a gate electrode of the second insulated gate semiconductor device is connected in series with the second gate resistor. circuit. 7. At least one of the main switching element and a control circuit for supplying an input signal to a control electrode thereof has a device current detecting function, and the first switching device in the protection circuit is provided based on a detected device current value. 6. A protection circuit control circuit for controlling at least one of a gate resistance and a negative bias of the insulated gate semiconductor device and a gate resistance and a negative bias of the second insulated gate semiconductor device.
Or the overvoltage protection circuit according to claim 6. 8. The semiconductor device according to claim 5, wherein a current-carrying area of the first insulated gate semiconductor element is larger than a current-carrying area of the second insulated gate semiconductor element. The overvoltage protection circuit as described. 9. The overvoltage protection circuit according to claim 5, wherein said first and second insulated gate semiconductor devices are formed in the same substrate. 10. The semiconductor device according to claim 5, wherein a gate electrode structure of said first insulated gate semiconductor device is different from a gate electrode structure of said second insulated gate semiconductor device. An overvoltage protection circuit according to any of the above. 11. The first insulated gate semiconductor device,
The value of the ratio of the capacitance between the high-voltage side main electrode and the gate electrode to the capacitance between the low-voltage side main electrode and the gate electrode is higher than the high voltage of the second insulated gate semiconductor device. The overvoltage protection according to claim 10, wherein a value of a ratio of a capacitance between the side main electrode and the gate electrode to a capacitance between the low voltage side main electrode and the gate electrode is larger. circuit. 12. The overvoltage according to claim 1, wherein a diode capable of flowing a current in a direction opposite to the main switching element is connected in parallel with said main switching element. Protection circuit.