JPH0669080B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0669080B2 JPH0669080B2 JP60016775A JP1677585A JPH0669080B2 JP H0669080 B2 JPH0669080 B2 JP H0669080B2 JP 60016775 A JP60016775 A JP 60016775A JP 1677585 A JP1677585 A JP 1677585A JP H0669080 B2 JPH0669080 B2 JP H0669080B2
- Authority
- JP
- Japan
- Prior art keywords
- input protection
- protection circuit
- circuit
- integrated circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体集積回路装置に係り、特に入力保護回路
部の改良に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of an input protection circuit section.
近年、半導体メモリなどのMOS型集積回路においては、
高集積化に伴い素子の微細化が進み、またチップ外部か
らの入力信号に対して高速動作可能なアクセスタイムの
速いものの需要が大きくなっている。例えば、1Mビット
dRAM等に用いられるMOSFETは、実効ゲート長が１μｍ、
ゲート酸化膜厚が200Å、ドレイン，ソースの拡散層深
さが0.2μｍと小さくなっている。このような微細素子
をもつデバイスにチップ外部から静電気等によるサージ
電圧や電源ノイズが加わると、ゲート酸化膜やソース，
ドレインのpn接合に瞬間的に高電圧が印加され、静電破
壊によりデバイスが破壊される。ゲート酸化膜にシリコ
ン酸化膜を用いた場合、その耐圧は10MV/cm程度であ
り、上記のようなゲート酸化膜厚200ÅのMOSFETは20V以
上の電圧がゲートに印加されると破壊されてしまう。こ
のため通常、MOS集積回路では、チップのボンディング
・パッドに入力保護回路が接続され、チップ内部の素子
に直接高電圧が印加されるのを防止するようにしてい
る。パッケージされた集積回路のピンの静電耐圧は200V
以上ないと通常の使用に耐えられず、そのためには入力
保護回路の保護抵抗として1KΩ以上が必要とされる。In recent years, in MOS type integrated circuits such as semiconductor memories,
As the degree of integration increases, the devices are becoming finer, and the demand for high-speed operation and fast access time for input signals from outside the chip is increasing. For example, 1 Mbit
MOSFET used for dRAM etc. has an effective gate length of 1 μm,
The gate oxide film thickness is 200Å, and the diffusion layer depth of drain and source is as small as 0.2 μm. When surge voltage or power supply noise due to static electricity is applied to the device with such fine elements from the outside of the chip, gate oxide film, source,
A high voltage is momentarily applied to the drain pn junction, and the device is destroyed by electrostatic breakdown. When a silicon oxide film is used as the gate oxide film, the breakdown voltage is about 10 MV / cm, and the above MOSFET having a gate oxide film thickness of 200 Å is destroyed when a voltage of 20 V or more is applied to the gate. Therefore, in a MOS integrated circuit, an input protection circuit is usually connected to a bonding pad of a chip to prevent a high voltage from being directly applied to an element inside the chip. Electrostatic breakdown voltage of packaged integrated circuit pins is 200V
If it is not above, normal use cannot be endured, and for that purpose, 1KΩ or more is required as the protection resistance of the input protection circuit.
ところで、入力保護回路の存在によりこれが設けられた
ボンディング・パッドに入る信号に遅延が生じる。その
遅延時間は入力保護抵抗と負荷容量との積により決ま
る。即ち入力保護回路に接続された配線の配線容量及び
MOSトランジスタのゲート容量が大きい程入力保護回路
による遅延は大きくなる。負荷容量が大きい場合、その
分入力抵抗を小さくすれば遅延時間は長くならないが、
これは入力保護回路自体の静電耐圧を低下させてしま
う。By the way, the presence of the input protection circuit causes a delay in the signal entering the bonding pad provided therewith. The delay time is determined by the product of the input protection resistance and the load capacitance. That is, the wiring capacitance of the wiring connected to the input protection circuit and
The larger the gate capacitance of the MOS transistor, the larger the delay due to the input protection circuit. If the load capacitance is large, the delay time will not increase if the input resistance is reduced accordingly, but
This lowers the electrostatic breakdown voltage of the input protection circuit itself.
従って従来のMOS集積回路では、最低1KΩの入力保護抵
抗が用いられ、配線容量やMOSトランジスタのゲート容
量が大きくなる程入力保護回路による遅延時間が長くな
る、という問題があった。Therefore, in the conventional MOS integrated circuit, the input protection resistor of at least 1 KΩ is used, and there is a problem that the delay time due to the input protection circuit becomes longer as the wiring capacitance and the gate capacitance of the MOS transistor increase.
本発明は上記した点に鑑みなされたもので、入力保護回
路による遅延時間を短くした半導体集積回路装置を提供
することを目的とする。The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit device in which a delay time due to an input protection circuit is shortened.
本発明にかかる半導体集積回路装置は、一個のボンディ
ング・パッドに対して二個以上の入力保護回路を接続
し、入力保護回路の一部を集積回路チップ内部の回路の
MOSトランジスタのゲートに接続し、一部を集積回路チ
ップ内部の回路のMOSトランジスタのソース，ドレイン
に接続したことを特徴とする。In the semiconductor integrated circuit device according to the present invention, two or more input protection circuits are connected to one bonding pad, and a part of the input protection circuit is connected to a circuit inside the integrated circuit chip.
It is characterized in that it is connected to the gate of the MOS transistor, and part of it is connected to the source and drain of the MOS transistor in the circuit inside the integrated circuit chip.
本発明によれば、入力保護回路自体の静電耐圧を低下さ
せることなく、入力保護回路により遅延時間を従来より
著しく短縮することができる。According to the present invention, the delay time can be significantly shortened by the input protection circuit without lowering the electrostatic breakdown voltage of the input protection circuit itself.
回路シュミレーション結果を用いて本発明の効果をより
具体的に説明する。一個のボンディング・パッドに一個
の入力保護回路が接続され、入力保護抵抗を1.3KΩ、入
力の負荷容量を2.5pFとした時、入力保護回路による遅
延時間は3.3nSであった。これに対して一個のボンディ
ング・パッドに二個の入力保護回路を接続し、入力の負
荷容量を1.5pFと1.0pFに分けると、各入力保護回路によ
る遅延2.2nSと1.8nSとなる。なおここでは、入力保護回
路が一個の場合の入力の負荷容量2.5pFは、幅２μm,長
さ2000μｍのAl配線の容量0.7pFとMOSトランジスタのゲ
ート容量1.8pFの合計であり、入力保護回路が二個の場
合、配線の容量は0.2pFと0.5pFに分けられ、ゲート容量
も1.3pFと0.5pFに分けられ、結局各入力保護回路に接続
された負荷容量は1.5pFと1.0pFになると想定している。The effects of the present invention will be described more specifically using the circuit simulation results. When one input protection circuit was connected to one bonding pad, the input protection resistance was 1.3KΩ, and the input load capacitance was 2.5pF, the delay time by the input protection circuit was 3.3nS. On the other hand, if two input protection circuits are connected to one bonding pad and the load capacitance of the input is divided into 1.5pF and 1.0pF, the delay due to each input protection circuit becomes 2.2nS and 1.8nS. Note that here, the input load capacitance of 2.5 pF when there is one input protection circuit is the sum of the Al wiring capacitance of 0.7 μF for the width of 2 μm and the length of 2000 μm and the gate capacitance of the MOS transistor of 1.8 pF. In the case of two, wiring capacitance is divided into 0.2pF and 0.5pF, gate capacitance is also divided into 1.3pF and 0.5pF, and the load capacitance connected to each input protection circuit is supposed to be 1.5pF and 1.0pF. is doing.
このように、入力保護回路を一個から二個に増やしただ
けで、その入力の負荷容量の分割次第で入力保護回路に
よる遅延時間を約1/2に短縮することができる。Thus, only by increasing the number of input protection circuits from one to two, the delay time by the input protection circuit can be reduced to about 1/2 depending on the division of the load capacitance of the input.
次に、1MビットdRAMのニブルモードのアクセス時間の実
測結果を例にとって説明する。入力保護回路が一個の場
合、CASが立ち下がってから出力Doutが得られるまでの
ニブル・アクセスタイムは18nSであり、そのうちCASの
入力保護回路による遅延時間が約7nS（アクセスタイム
の40％）もある。これに対し、CASの入力保護回路を二
個にすると、入力保護回路による遅延時間は3.5nSとな
り、その結果アクセスタイムは13.5nSと大幅に短縮する
ことができた。しかもCASの入力保護回路による遅延時
間が1/2に短縮されたことによって、回路の動作マージ
ンも大幅に向上することができた。Next, an actual measurement result of the access time in the nibble mode of the 1 Mbit dRAM will be described as an example. With one input protection circuit, the nibble access time from the fall of CAS to the output Dout is 18nS, of which the delay time by the input protection circuit of CAS is about 7nS (40% of the access time). is there. On the other hand, if the CAS had two input protection circuits, the delay time due to the input protection circuit was 3.5 nS, and as a result, the access time could be greatly reduced to 13.5 nS. Moreover, the delay time of the input protection circuit of CAS has been reduced by half, and the operating margin of the circuit has been greatly improved.
また、入力保護回路の一部を内部回路のソース，ドレイ
ンを接続しているので、入力保護回路で保証されない高
電圧が印加された場合、この高電圧印加時の過渡電流を
ソース，ドレインを介して流すことができる。このた
め、入力保護回路で保証されない高電圧が印加された場
合にも、入力保護回路に接続された内部回路のゲート破
壊を防止することができる。Also, since a part of the input protection circuit is connected to the source and drain of the internal circuit, when a high voltage that is not guaranteed by the input protection circuit is applied, the transient current at the time of applying this high voltage is passed through the source and drain. Can be washed away. Therefore, even when a high voltage that is not guaranteed by the input protection circuit is applied, it is possible to prevent the gate breakdown of the internal circuit connected to the input protection circuit.
本発明の実施例を図面を参照して次に説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は一実施例のMOS集積回路の要部構成を示す。図
において、11はボンディング・パッドであり、これに３
個の入力保護回路12a,12b,12cが接続され、各入力保護
回路にはそれぞれ配線13a,13b,13cが接続され、かつ各
配線先端には負荷MOSトランジスタQ2a,Q2b,Q2cが接続さ
れている。入力保護抵抗R1a,R2a,R1b,R2b,R1c,R2cは例
えば、n+拡散層や多結晶シリコン膜により形成されたも
のである。またMOSトランジスタQ1a,Q1b,Q1cは、サージ
電圧により過渡電流を流すもので、ゲートとソースは共
通にソース電源電圧Vssに接続されている。FIG. 1 shows the essential structure of a MOS integrated circuit according to an embodiment. In the figure, 11 is a bonding pad, to which 3
Input protection circuits 12a, 12b, 12c are connected, wirings 13a, 13b, 13c are connected to each input protection circuit, and load MOS transistors Q2a, Q2b, Q2c are connected to the tip of each wiring. . The input protection resistors R1a, R2a, R1b, R2b, R1c, R2c are formed of, for example, an n + diffusion layer or a polycrystalline silicon film. The MOS transistors Q1a, Q1b, Q1c flow a transient current due to a surge voltage, and their gates and sources are commonly connected to the source power supply voltage Vss.
このように構成することにより、ボンディング・パッド
11と３本の配線13a,13b,13cの間に一個の入力保護回路
を設けた場合に比べて、入力保護回路による遅延時間を
大きく短縮することができる。With this configuration, the bonding pad
As compared with the case where one input protection circuit is provided between 11 and the three wirings 13a, 13b, 13c, the delay time due to the input protection circuit can be greatly reduced.
入力保護回路の構成は第１図のものに限られない。例え
ば、いずれも公知であるが第２図あるいは第３図のよう
な入力保護回路を用いた場合にも本発明は有効である。The configuration of the input protection circuit is not limited to that shown in FIG. For example, the present invention is effective when an input protection circuit as shown in FIG. 2 or FIG.
第１図は本発明の一実施例の要部構成を示す図、第２図
及び第３図は入力保護回路の他の構成例を示す図であ
る。 11……ボンディング・パッド 12a,12b,12c……入力保護回路 13a,13b,13c……配線 Q2a,Q2b,Q2c……負荷MOSトランジスタFIG. 1 is a diagram showing a configuration of a main part of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing another configuration example of an input protection circuit. 11 …… Bonding pad 12a, 12b, 12c …… Input protection circuit 13a, 13b, 13c …… Wiring Q2a, Q2b, Q2c …… Load MOS transistor
───────────────────────────────────────────────────── フロントページの続き (72)発明者 熊埜御堂 高毅 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 (72)発明者 岩田 佳久 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝総合研究所内 (72)発明者 中川 薫 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 (56)参考文献 特開 昭58−141567（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Kumano Mido Takaki, Komukai-shishiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture, Tamagawa factory, Toshiba Corporation Town No. 1 Incorporated Toshiba Corporation Research Institute (72) Inventor Kaoru Nakagawa Komukai Toshiba Town No. 1 Komukai-shi, Kawasaki-shi, Kanagawa Kanagawa Factory (56) Reference company JP-A-58-141567 (JP, Sho 58-141567) A)
Claims (1)
力保護回路が接続され、各々の入力保護回路の一部はそ
れぞれ集積回路チップ内部の回路のMOSトランジスタの
ゲートに接続され、一部は集積回路チップ内部の回路の
MOSトランジスタのソース，ドレインに接続されている
ことを特徴とする半導体集積回路装置。1. A plurality of input protection circuits are connected to one bonding pad, a part of each input protection circuit is connected to a gate of a MOS transistor of a circuit inside an integrated circuit chip, and a part of the input protection circuit is integrated. Of the circuit inside the circuit chip
A semiconductor integrated circuit device characterized by being connected to the source and drain of a MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016775A JPH0669080B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016775A JPH0669080B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61176146A JPS61176146A (en) | 1986-08-07 |
| JPH0669080B2 true JPH0669080B2 (en) | 1994-08-31 |
Family
ID=11925575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60016775A Expired - Lifetime JPH0669080B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669080B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62154665A (en) * | 1985-12-26 | 1987-07-09 | Nec Corp | Semiconductor device |
| JPH06101560B2 (en) * | 1986-02-17 | 1994-12-12 | 日本電気株式会社 | Semiconductor device |
| JPH0616558B2 (en) * | 1987-01-28 | 1994-03-02 | 三菱電機株式会社 | Input protection device for semiconductor device |
| JPH0376263A (en) * | 1989-08-18 | 1991-04-02 | Fujitsu Ltd | Wafer scale integrated circuit device |
| EP1299932A4 (en) * | 2000-06-15 | 2006-04-26 | Sarnoff Corp | Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits |
| JP5752657B2 (en) * | 2012-09-10 | 2015-07-22 | 株式会社東芝 | Semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5763861A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
| JPS58141567A (en) * | 1982-02-17 | 1983-08-22 | Nec Corp | Protective device for input from semiconductor integrated circuit |
| JPS58159363A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Input/output protecting device for semiconductor integrated circuit |
| JPS59107493A (en) * | 1982-12-09 | 1984-06-21 | Ricoh Co Ltd | Eprom memory device with test circuit |
| JPS59182567A (en) * | 1983-04-01 | 1984-10-17 | Hitachi Ltd | Metal oxide semiconductor integrated circuit device |
| JPS59224162A (en) * | 1983-06-03 | 1984-12-17 | Ricoh Co Ltd | Semiconductor protecting device |
-
1985
- 1985-01-31 JP JP60016775A patent/JPH0669080B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61176146A (en) | 1986-08-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4876584A (en) | Electrostatic discharge protection circuit | |
| KR100296567B1 (en) | Cmos circuit esd protection using well resistor | |
| JPH06163824A (en) | Semiconductor integrated circuit | |
| JPH07240678A (en) | Semiconductor integrated circuit | |
| JPH0669080B2 (en) | Semiconductor integrated circuit device | |
| JP2570610B2 (en) | Semiconductor device | |
| JP3450909B2 (en) | Semiconductor device | |
| JP3267479B2 (en) | Semiconductor integrated circuit device | |
| JPH0653497A (en) | Semiconductor device equipped with i/o protective circuit | |
| JP2003347921A (en) | Semiconductor device and system | |
| KR920005357B1 (en) | Input protection circuit | |
| Masuda et al. | Single 5-V, 64K RAM with scaled-down MOS structure | |
| KR100528777B1 (en) | Electrostatic Discharge Circuit_ | |
| US6429469B1 (en) | Optical Proximity Correction Structures Having Decoupling Capacitors | |
| JPS58222573A (en) | Semiconductor integrated circuit device | |
| JPH0532908B2 (en) | ||
| JPH0494167A (en) | Semiconductor device | |
| KR20040099154A (en) | Semiconductor device | |
| JPH058584B2 (en) | ||
| JPH05267586A (en) | Output protection network | |
| JPH0685422B2 (en) | Semiconductor integrated circuit | |
| JPS58141567A (en) | Protective device for input from semiconductor integrated circuit | |
| JPH05175519A (en) | Semiconductor device | |
| JPH04271142A (en) | Semiconductor integrated circuit device | |
| JPH04239763A (en) | Output buffer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |