JPH058584B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and in particular to an LSI that is optimal for an LSI consisting of miniaturized MOS transistors.
Regarding the configuration of

[Prior art]

Conventionally, in a semiconductor integrated circuit, a circuit portion 1 consisting of a memory circuit, a logic circuit, an analog circuit, etc. has been connected between an external power supply terminal 2 and a ground terminal 3 as shown in FIG. In recent years, these ICs and LSIs have placed emphasis on interfacing with peripheral ICs, and have used an external power supply voltage of 5V for ease of use.

On the other hand, the dimensions of insulated gate field effect transistors (hereinafter abbreviated as MOS transistors) that make up internal circuits are becoming smaller year by year due to proportional shrinkage, and the high integration and high performance of LSIs are increasing. has made it possible to However, as the dimensions of devices are reduced, high-energy electrons are injected into the gate insulating film, and changes in threshold voltage cause a decrease in mutual conductance. For example, when a predetermined voltage is applied to the gate and drain and the threshold voltage of the element is measured 30 seconds later, the absolute value changes. The results of measurements under these conditions, provided that the drain and source were reversed from when voltage was applied, are shown in FIGS. 2A and 2B. Figure 2A
shows the change in threshold voltage of an n-channel MOS transistor, and it can be seen that the change in threshold voltage tends to occur at a lower voltage than that of the p-channel MOS transistor shown in FIG. 2B. Furthermore, especially in the case of n-channel MOS transistors, a power supply voltage of 5V is approaching a region where it can no longer be used in terms of reliability. Naturally, as devices become further miniaturized, the voltage at which the above phenomenon occurs becomes lower and lower.
If the LSI is used with a power supply voltage of 5 volts, the operating speed of the LSI will slow down, or in the worst case, it will be destroyed.

[Purpose of the invention]

An object of the present invention is to realize an integrated circuit device that can realize a highly integrated, high-performance LSI without causing the above characteristic fluctuations in a complementary MOS (hereinafter abbreviated as CMOS) integrated circuit using miniaturized MOS transistors. Our goal is to provide the following.

[Summary of the invention]

The principle concept of the present invention will be explained with reference to FIG. 3A. Third
In Figure A, 2 is an external power supply voltage terminal (voltage
V _c1 ) 5 is lower than V _c1 based on V _c1 , and is refined
A power supply circuit section 7 generates a voltage V _c2 that does not cause characteristic fluctuations of the main circuit section 6 composed of MOS transistors, and 7 is a terminal of V _c2 . In the present invention, _the region 4 indicated by the broken line in FIG. 3 _is integrated on the same substrate, and the voltage supplied from the outside is V _c1 , but it is The purpose is to operate the main circuits.

FIG. 3B shows the relationship between V _c1 and V _c2 . In the present invention, the external power supply voltage is set to a certain value (V _c1 ′)
If the voltage exceeds that level, a power supply circuit 5 is used in which V _c2 is clamped at a constant value.

By adopting the above configuration, (1) an externally supplied power supply voltage of 5V can be used as before;
Easy-to-use LSI with easy interface with peripheral ICs
(2) Even if the internal circuit is configured with miniaturized MOS transistors, this power supply voltage is lower than the voltage supplied from the outside, so there will be no adverse effects such as characteristic fluctuations. (3) Miniaturized MOS Large capacity, high speed, low power consumption memory using transistors
LSI and large-scale logic LSI can be realized with high reliability. Furthermore, it is highly resistant to the so-called latch-up phenomenon, in which the parasitic pnpn type elements inside the conventional CMOS structure enter a low-resistance state and an abnormally large current flows between the power supply and ground terminals. This is because V _c1 can be applied to the n-type substrate, V _c2 to the p ⁺ layer which becomes the drain of the p-channel MOS transistor, and the ground voltage to the p-type well, and the conventional V _c1 = V _c2 . This is because lateral PNP bipolar transistors are less likely to operate against external noise currents than conventional structures.

〔Example〕

First, Figure 4 shows the CMOS described in the previous section.
An embodiment in which the present invention is applied to a semiconductor circuit having a structure will be described. Voltage V _c1 applied from external power supply voltage terminal 2 is applied to n-type substrate 202 via n ⁺ region 226 . Further, this voltage V _c1 is converted into a voltage V _c2 via the power supply circuit section 5, and is applied to each section of the main circuit. In the figure, for convenience, the power supply circuit section 5 is replaced by the board 20.
Although it is described separately from 2, it is actually the board 202.
Form this circuit on top. P-type wells 204 and 206 are grounded via p ⁺ regions 208 and 210, respectively. Also, the surface of the substrate 202
A p-type MOS transistor formed by p ⁺ regions 216 and 218 and an n ⁺ region 21 in the p-type well 204
A CMOS inverter is configured with an n-type MOS transistor formed by transistors 2 and 214, and a voltage V _c2 is supplied to the drain 216 of the p-type transistor from the power supply circuit section. On the other hand, a circuit is formed in the p-type well 206 by nMOS transistors formed of n ⁺ regions 220, 222, 224, etc.
A voltage V _c2 is supplied via a resistor 228 .

FIG. 5A is a circuit configuration diagram of an embodiment that realizes the configuration of FIG. 3, and FIG. 5B is a circuit configuration diagram for generating a reference voltage V _R for obtaining a predetermined voltage V _c2 . In Figure 5, 401, 402, 403 are p channels
MOS transistor, 404, 405, 406,
407, 408, 423, 424 are n channels
It is a MOS transistor. The part 5 is the power supply circuit in Figure 3 and is 401, 402, 404, 47.
5, a constant current source 407, and 41 for generating the gate voltage of 407.
The circuit is divided into circuit parts each consisting of a resistor of 5 and a MOS diode 406, which drives the final p-channel MOS transistor 403.

Therefore, the differential amplifier of the power supply circuit 5 includes differentially connected MOS transistors 404 and 405, and a current mirror connected load MOS transistor 401 whose drain is connected to the drains of the differentially connected MOS transistors 404 and 405. ,402
and a constant current source MOS transistor 407, and the gate of the MOS transistor 405 and the MOS
The gate of the transistor 404 becomes the inverting input terminal 412 and the non-inverting input terminal 411 of this differential amplifier, the drains of the MOS transistors 402 and 405 become the output of this differential amplifier, and this output becomes the gate of the p-channel output MOS transistor 403. is applied to. When a reference voltage V _R is set to the gate 412 (inverting input terminal of the differential amplifier) of the p-channel output MOS transistor 40
The drain output 413 of 3 is the gate terminal 4 of 404
11, a feedback is applied, and a voltage V _c2 approximately the same as V _R appears at the output 413.

Further, it is preferable to add a large capacitance to the terminal 7 so that the value of the output voltage does not change suddenly when there is a sudden change in current in the main circuit 6.

As shown in FIG. 5B, the reference voltage V _R generation circuit consists of a resistor 421 and a diode-connected n
It is composed of channel MOS transistors 423, 424, etc. Therefore, if the threshold voltage of an n-channel MOS transistor is V _To , then V _R n×
It becomes V _To . Note that n is vertically connected n channels.
This is the number of MOS transistors, and this value may be set arbitrarily as desired. In addition, in this example,
The explanation has been made using n-channel MOS transistors and resistors, but p-channel and n-channel MOS transistors and resistors, or all p-channel MOS transistors and resistors are used.
It can also be easily realized using MOS transistors.

Therefore, according to the embodiments shown in FIGS. 5A and 5B, the differentially connected MOS transistors 404 and 405 and the current mirror connected load MOS transistor 401,
402 and the p-channel output MOS transistor 403 are connected to a reference voltage V _R
is input and operates as a voltage follower that extracts the same reference voltage V _R from its output with low output impedance. The power supply voltage V _c2 can be obtained.

Further, according to the embodiment of the power supply circuit shown in FIG. 5A, the first power supply voltage V _c1 from the outside is the reference voltage V _R ≒n×V _To generated from the reference voltage generation circuit shown in FIG. 5B.
When the voltage decreases to below, the diode-connected n-channel MOS transistors 423 and ₄₂₄ of the reference voltage generation circuit shown in FIG. V _c1 , and in this case as well, the output 413 is caused by feedback from the drain output 413 of the p-channel output MOS transistor 403 to the non-inverting input terminal 411 of the differential amplifier.
The second power supply voltage V _c2 obtained from the second power supply voltage V c2 also tends to be approximately equal to the first power supply voltage V _c1 from the outside. At this time, the MOS as the output 413 of the differential amplifier
Since the common drains of transistors 402 and 405 can be varied towards a low level ground potential, p-channel output MOS transistor 40
3 is driven to a sufficiently conductive state, and the first power supply voltage V _c1 from the outside is obtained as the second power supply voltage V _c2 from the output 413 via the source-drain path of the p-channel output MOS transistor 403 in the conductive state. be able to. In this way, the first
When the power supply voltage _Vc1 drops below the reference voltage _VR , the power supply circuits shown in FIGS. 5A and B can supply the second power supply voltage _Vc2 almost unchanged to the internal circuits with almost no voltage loss. It is possible.

Although the semiconductor integrated circuit described above is integrated on the same chip as the main circuit section 6, the power supply circuit section itself must not cause characteristic fluctuations. Therefore, Figure 5A
The MOS transistors other than circuit block 6 are as follows:
It is desirable that the channel length be longer than that of the MOS transistor of circuit block 6. In particular, n-channel
Since MOS transistors are sensitive to high voltages as described above, it is necessary to use ones with long channel lengths. For example, when operating V _c1 at 5V, if an n-channel MOS transistor with a channel length of 1 to 1.5 microns or less is used in the main circuit section 6, the n-channel MOS transistor in the power supply circuit section 5
A channel length of 2 microns or more is sufficient for a MOS transistor. Depending on its characteristics, the p-channel MOS transistor may have the same channel length as the main circuit section 6, or may have the same channel length as the above-mentioned n-channel MOS transistor.
It is desirable to take the same measures as in the case of MOS transistors.

FIG. 6 shows a reference example of the present invention. In FIG. 6, reference numeral 5 denotes a power supply circuit section, 413 an output terminal section of 5, and 411 a feedback terminal to the power supply circuit, which is connected to the power supply terminal 7 of the main circuit section 6. Further, between 413 and 7, npn type bipolar transistors 501 and 502 are connected in Darlington. The feature of this reference example is that the main circuit section 6 is composed of miniaturized MOS transistors.
The above-mentioned bipolar transistor is used as a current supply device so that a large current can be easily supplied to the circuit 413, and the load on the circuit 413 can be reduced so that the power supply circuit 5 shown in FIG. 4 can operate at high speed. In this reference example, a Darlington connection of two stages of bipolar transistors has been described, but if high-performance bipolar transistors are used, only one stage is sufficient, or a Darlington connection or parallel connection of a plurality of bipolar transistors may be used. 413 and 411
Even if the above-mentioned bipolar transistor is provided between (7), it goes without saying that the characteristics of V _R V _c2 , which is the object of the present invention, can be obtained, and there is no potential drop in V _c2 even in the large current region, which is good. These characteristics have been obtained from experimental results. The capacitor 503 is provided in order to prevent the voltage at the terminal 7 from changing rapidly even if there is a sudden change in current in the main circuit section 6, and to prevent the electrical characteristics of the main circuit section 6 from being adversely affected.

The npn bipolar transistor mentioned above is
This can be easily realized using a normal CMOS structure. That is, the n-type substrate is the collector, the p-type well is the base,
The n-type high concentration layer may be used as an emitter. The collectors are common on the same board, making Darlington connections easy.

In this reference example shown in Fig. 6, the first power supply voltage
When V _{c1 is} higher than the reference voltage _VR , the second power supply voltage V _c2 ≒ V _R and normal operation can be achieved. When the voltage drops below V _R , the second power supply voltage V _c2 ≒ the first power supply voltage V _c1 due to the following reason.
Therefore, voltage loss will occur.

That is, in order for the second power supply voltage V _c2 obtained from the output 7 to become equal to the first power supply voltage V _c1 due to the feedback 411 from the output 413 of the power supply circuit 5, the Darlington-connected npn bipolar transistor 501 must be ,502 base・
The output 413 of the power supply circuit 5 must output a voltage higher than the output 7 by the emitter voltage 2V _BE to drive the base of the transistor 501.

The base drive voltage required for this is V _c1 +2V _BE , whereas the maximum output of the output 413 of the power supply circuit 5 to which the first power supply voltage V _c1 is supplied is V _c1 , and it is impossible to exceed V _c1 +2V _BE . Voltage cannot be output.

Therefore, in this reference example shown in FIG. 6, the second power supply voltage V _c2 obtained from the output 7 becomes V _c1 −2V _BE ,
When the first power supply voltage V _c1 from the outside falls below the reference voltage _VR , it becomes impossible to directly supply it to the internal circuit as the second power supply voltage V _c2 without voltage loss.

Such voltage loss is caused by the Darlington-connected npn bipolar transistors 501 and 50 in FIG.
This also occurs when 2 is replaced with an n-channel output MOS transistor, and it can be understood that the voltage loss at the time of such replacement becomes the threshold voltage V _th between the gate and source of the n-channel output MOS transistor.

FIG. 7 shows another embodiment of the invention. In FIG. 7, 601 and 602 are power supply circuit sections, and 603 and 604 are main circuit sections composed of miniaturized MOS transistors. The feature of this embodiment is that the main circuit section is divided into a plurality of parts, and the respective power supplies 605 and 606 are supplied from individual power supply circuits. With this configuration, the current flowing to the main circuits can be distributed and supplied, and even sudden changes in current or large currents can be adequately coped with within the same chip.

〔Effect of the invention〕

As described above, according to the present invention, even if the elements of the main circuit are miniaturized, there is no adverse effect such as characteristic fluctuations due to this, and moreover, the present invention is a highly integrated circuit that can be used with the same power supply as a conventional integrated circuit. A highly reliable integrated circuit can be obtained, and it can also be made highly resistant to the latch-up phenomenon of a CMOS structure.

[Brief explanation of the drawing]

Figure 1 shows the configuration of a conventional integrated circuit, Figure 2 A and B
3A and 3B are block diagrams showing the basic configuration of the present invention and their characteristic diagrams. FIG. 4 is a sectional view of an embodiment of the present invention. 7 are block diagrams showing embodiments of the present invention, and FIG. 6 is a block diagram showing a reference example of the present invention. 2... External power supply voltage terminal, 5... Power supply circuit, 6... Main circuit, 401, 402, 403... p channel
MOS transistor, 404, 405, 406,
407, 408, 423, 424...n channel
MOS transistor.

Claims (1)

[Scope of Claims] 1. A power supply circuit that operates with a first power supply voltage supplied from the outside and outputs a second power supply voltage lower than the first power supply voltage is provided on the substrate of the semiconductor integrated circuit device, 1 micron to 1 micron while being formed on the substrate.
Channel lengths of 1.5 microns or less
An internal circuit having a MOS transistor is operated by the second power supply voltage outputted from the power supply circuit, and the power supply circuit is a reference voltage generation circuit that generates a reference voltage by being supplied with the first power supply voltage. and a differential amplifier whose inverting input terminal is supplied with the reference voltage generated from the reference voltage generation circuit, the gate of which is connected to the output of the differential amplifier,
A p-channel output MOS whose source is connected to the first power supply voltage and whose drain output is fed back to the non-inverting input terminal of the differential amplifier.
A semiconductor integrated circuit device comprising a transistor, wherein the second power supply voltage is obtained from the drain output of the p-channel output MOS transistor. 2 The differential amplifier of the power supply circuit includes a differentially connected MOS transistor whose gate is connected to the inverting input terminal and the non-inverting input terminal, and whose drain is connected to the drain of the differentially connected MOS transistor. 2. The semiconductor integrated circuit device according to claim 1, further comprising a current mirror connected load MOS transistor. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the reference voltage generation circuit of the power supply circuit includes a plurality of cascaded diode-connected MOS transistors. 4. The power supply circuit is characterized in that it is composed of elements whose basic configuration is p-channel and n-channel MOS transistors having channel lengths longer than those of the p-channel and n-channel MOS transistors used in the internal circuit. A semiconductor integrated circuit device according to any one of claims 1 to 3. 5. The semiconductor integrated circuit device according to claim 4, wherein a capacitor integrated on the substrate is added to the second power supply voltage. 6. A plurality of the power supply circuits are provided on the substrate, and a plurality of second power supplies outputted from the power supply circuit operate internal circuits divided into a plurality of parts. The semiconductor integrated circuit device according to item 4 or 5. 7. Claim 1, characterized in that a change in the threshold voltage of the MOS transistor having the channel length is prevented by operating the internal circuit with the second power supply voltage output from the power supply circuit. 7. The semiconductor integrated circuit device according to any one of items 6 to 6.