JPS59105369A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the strength to the breakdown of an MOSIC due to static electricity or a high voltage over the rating by a method wherein the ratio of the width of a small crystal Si, rectangular to the direction of electric signal transmission, to the length along the direction of electric signal transmission of a polycrystalline Si is set less than a specific value on a mask. CONSTITUTION:While latch-up phenomenon is avoided by setting at 6 or less the ratio L/W of the length L and the width W of the polycrystalline Si 105 which connects a bonding pad 1 and a clamp protection diode 3, the breakdown of a field oxide film due to an excess input voltage is prevented. As compared with a conventional device whose ratio L/W is taken large, for example, when the ratio L/W of the polycrystalline Si is 10, a voltage of 400-500V is just applied instantaneously between an input terminal and a semiconductor substrate, and the field oxide film is easily broken down at a contact part 107 between a connection aluminum wiring 104 from the bonding pad 1 and the polycrystalline Si 105; on the other hand, under the same condition at the ratio L/W=5, the breakdown of the field oxide film does not at all appear, and the latch-up withstand strength turns to the same level as that at the ratio L/W=10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an MO8O8 type field effect transistor multilayer device (hereinafter abbreviated as "MO8C"), and a signal output terminal and a protection element for preventing destruction of the MO8C. are electrically connected using polycrystalline silicon, and the ratio of the length L of the polycrystalline silicon in the signal propagation direction to the width W in the direction orthogonal to the polycrystalline silicon length, L, /v
The purpose is to set it to 6 or less on the ff mask to improve the resistance to destruction of the MO8IC due to static electricity or high voltage exceeding the rating.

The destruction phenomenon caused by excessive surge of static electricity etc. of MO8IC is as follows.
Since this has been a problem since the beginning of its development, various countermeasures have been proposed and improvements have been made. However, as the current integration density of VcMOS technology C continues to increase, it is no longer possible to use the conventional countermeasures as they are for the above-mentioned MOS technology. )
This results in electrostatic damage and a turn-on phenomenon (hereinafter referred to as latch-up phenomenon) of the parasitic thyristor that inevitably exists in the MO8IC.

The present invention takes the above-mentioned situation into consideration and improves the ratio of the length and width W of the polycrystalline silicon layer connecting the input/output terminal of MO8 C and the protection element for preventing destruction.

Conventional complementary insulated gate semiconductor integrated device C or below rc-M
A typical breakdown protection circuit at the input/output terminal of a
The input signal applies a potential to the protection resistor 2 and the clamp protection diode 3, and then to the input gate 4 of the C-MO8 C.
The protective resistor 2 is provided in an N-type semiconductor 101 as shown in FIG. 2 α.

A conductivity type different from that of the semiconductor substrate 101, that is, a P-type diffusion/J is formed by 102 or 811
! As shown in FIG. 2, the protective resistor 2 is obtained by forming field oxide M103'lr on the surface of the semiconductor substrate 101 and then providing a polycrystalline 71737 layer 105 on the surface of the field oxide film 103. . Such a structure has improved breakdown resistance against static electricity, etc., but as explained above, as MO8C becomes highly integrated, the formation of the protective resistor 2 by the P-type diffusion layer 102 becomes more difficult.
It has the disadvantage of easily causing the latch-up phenomenon peculiar to MO8-C. By the way, this latch-up phenomenon occurs in conventional semiconductor devices, for example,
As shown in the specification of Publication No. 139, by eliminating the potential gradient of the semiconductor substrate with a structure in which a highly concentrated diffusion layer is provided in the semiconductor substrate, and by changing the layout on the MO8O8 type field effect transistor screen. , it is possible to deteriorate the parasitic thyristor characteristics and make it less likely to occur, but in MO8 process C with a cylindrical integration degree, the above P''
? It is preferable to use a polycrystalline silicon layer 105 as a protective resistor instead of the A diffusion layer 102. However, if a protective resistor with a high resistance value, that is, a large value of polycrystalline silicon length/polycrystalline silicon width W, is provided by the polycrystalline silicon layer, excessive voltage due to static electricity applied to the bonding pad l, etc. The time required for neutralization through the protection diode 2 becomes longer, resulting in destruction of the field oxide film 103.

Therefore, as shown in FIG. 3, the present invention prevents latch-up by reducing the ratio L/W -ii of the length L and width W of the polycrystalline silicon 105 connecting the bonding pad 1 and the clamp protection diode 3 to 5 or less. This eliminates the drawback of field oxide film destruction due to excessive input voltage while avoiding this phenomenon. Compared to the conventional method where LAW-(H is set large), for example, when the ψ of polycrystalline silicon is used as a river, only a voltage of 400 to 500 volts is applied between the input terminal and the semiconductor substrate. Then, aluminum wiring 104 for connection from bonding pad 1 and polycrystalline silicon 1
At the contact part 107 with IO5, the field oxide film was easily destroyed, whereas under the same conditions at I=5, no field oxide film breakdown appeared at all, and the latch-up resistance was as low as ψ=IO. It was at the same level.

In FIGS. 2 and 3, 106 is a field oxide film, and 108 is a contact hole.

As described above, the present invention has a sufficient effect to prevent destruction of the field oxide film due to unrated high voltage and static electricity, which are encountered when thinning the field oxide film as MO8IC miniaturization progresses. Demonstrated.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing destruction protection at the input terminal of a conventional C-MO8 design. FIG. 2 is a cross-sectional view for explaining the structure of a conventional protective resistor. FIG. 3 is a pattern diagram showing the destruction protection mechanism according to the present invention. 101...Semiconductor substrate 103...Field oxide film] 05@...Polycrystalline silicon or more Applicant Suwa Seikosha Co., Ltd.

Claims (1)

[Claims] In a semiconductor device having a circuit in which an MO8O8 type field effect transistor output terminal formed on a semiconductor substrate and a breakdown prevention element such as a clamp diode are electrically connected, the signal input/output terminal and the breakdown prevention element such as a clamp diode are electrically connected. Polycrystalline silicon is used to connect the prevention element, and the ratio of the width of the polycrystalline silicon perpendicular to the electrical signal propagation direction to the length of the polycrystalline silicon along the electrical signal propagation direction is determined on the mask. 6 or less.