JPH0454978B2 - - Google Patents
Info
- Publication number
- JPH0454978B2 JPH0454978B2 JP57214468A JP21446882A JPH0454978B2 JP H0454978 B2 JPH0454978 B2 JP H0454978B2 JP 57214468 A JP57214468 A JP 57214468A JP 21446882 A JP21446882 A JP 21446882A JP H0454978 B2 JPH0454978 B2 JP H0454978B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- input
- protection resistor
- diffusion layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 230000005611 electricity Effects 0.000 description 7
- 230000003068 static effect Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 208000019901 Anxiety disease Diseases 0.000 description 1
- 230000036506 anxiety Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Description
【発明の詳細な説明】
本発明は半導体装置、特に内部回路としての
MOS型電界効果トランジスタの集積装置（以下
「MOSIC」と略記する）に関する。本発明の目的
は、MOSICの、静電気や、定格以上の高電圧に
よる破壊に対する耐量を改善すること及び寄生サ
イリスタのターンオン現象（以下ラツチアツプ現
象と呼ぶ）を誘起することを防止することにあ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly as an internal circuit.
The present invention relates to a MOS field effect transistor integrated device (hereinafter abbreviated as "MOSIC"). The purpose of the present invention is to improve the resistance of MOSICs to destruction caused by static electricity and high voltages exceeding the rated voltage, and to prevent the turn-on phenomenon of a parasitic thyristor (hereinafter referred to as latch-up phenomenon) from being induced.
MOSICの静電気等の過大サージによる破壊現
象は、その開発当初からの問題であつたため、こ
れまでに各種の対策が提案され、改良の手が加え
られてきた。ところが、現在の様にMOSICの集
積密度が一段と高まると、従来の対策をそのまま
上記MOSICに用いることは、MOS型電界効果ト
ランジスタのゲート絶縁膜以外の絶縁皮膜（以下
「フイールド絶縁膜」と呼ぶ）の静電気破壊や、
相補型絶縁ゲート半導体集積装置（以下「Ｃ−
MOSIC」と略す）内に必然的に存在してしまう、
ラツチアツプ現象を誘起する結果となる。 The phenomenon of destruction of MOSICs due to excessive surges of static electricity, etc. has been a problem since the beginning of their development, so various countermeasures have been proposed and improvements have been made. However, as the integration density of MOSICs continues to increase as it does today, it is difficult to use conventional measures for the MOSICs as they are, which means that the insulating film other than the gate insulating film of the MOS field effect transistor (hereinafter referred to as "field insulating film") static electricity damage,
Complementary insulated gate semiconductor integrated device (hereinafter referred to as “C-
(abbreviated as "MOSIC"),
This results in a latch-up phenomenon.
本発明は、上記状況と、各種の静電気による破
壊現象に関する実験結果を検討しなされたもので
ある。 The present invention was developed by considering the above-mentioned situation and experimental results regarding various types of breakdown phenomena caused by static electricity.
従来のＣ−MOSICの入出力端子における代表
的な破壊保護回路は、第１図に示す如く、入力パ
ツドとしてのボンデイングパツド１に入つた信号
が、保護抵抗２、クランプ保護ダイオード３に電
位を与えたのち、Ｃ−MOSICの入力部としての
入力ゲート４に伝えられる回路になつており、そ
の保護抵抗２は、第２図ａに示す如く、Ｎ型半導
体１０１中に設けられたＰ型拡散層１０２によつ
て形成されるか、第２図ｂに示す如く、半導体基
板１０１の表面上にフイールド絶縁膜１０３を形
成させ、次いでフイールド絶縁膜１０３上に多結
晶シリコン層１０５を設けることによつて、上記
保護抵抗２が得られている。 A typical breakdown protection circuit for the input/output terminals of a conventional C-MOSIC, as shown in Fig. 1, is such that a signal input to a bonding pad 1 serving as an input pad causes a potential to be applied to a protective resistor 2 and a clamp protection diode 3. After this, the circuit is transmitted to the input gate 4 as the input part of the C-MOSIC, and the protective resistor 2 is a P-type diffusion provided in the N-type semiconductor 101, as shown in FIG. 2a. 2b, or by forming a field insulating film 103 on the surface of the semiconductor substrate 101 and then providing a polycrystalline silicon layer 105 on the field insulating film 103. Thus, the above-mentioned protective resistor 2 was obtained.
尚第２図において、１０４は、保護抵抗２とボ
ンデイングパツド１、あるいはクランプ保護ダイ
オードとを接続するメタル配線層、１０６はフイ
ールド絶縁皮膜である。 In FIG. 2, 104 is a metal wiring layer connecting the protective resistor 2 and the bonding pad 1 or the clamp protective diode, and 106 is a field insulating film.
この様な構造によつて、静電気等の破壊耐量は
向上してきたが、上記でも説明した様に、
MOSICが高集積化されると、Ｐ型拡散層１０２
による保護抵抗２の形成は、Ｃ−MOSIC特有の
ラツチアツプ現象を引き起し易くするという欠点
を有している。従つて、保護抵抗としては、多結
晶シリコン層１０５を採用するのが望ましい。し
かるに、該多結晶シリコン層による高抵抗値の保
護抵抗を設けると、ボンデイングパツド１に加わ
つた静電気等による過大電圧が、保護ダイオード
３を通じて中和されるに要する時間は長くなり、
フイールド絶縁膜１０３の破壊をもたらす。 This structure has improved the breakdown resistance against static electricity, but as explained above,
As MOSICs become highly integrated, the P-type diffusion layer 102
The formation of the protective resistor 2 in this manner has the disadvantage that it tends to cause the latch-up phenomenon peculiar to C-MOSIC. Therefore, it is desirable to use the polycrystalline silicon layer 105 as the protective resistor. However, if a high-resistance protection resistor made of the polycrystalline silicon layer is provided, the time required for the excessive voltage due to static electricity, etc. applied to the bonding pad 1 to be neutralized through the protection diode 3 becomes longer.
This results in destruction of the field insulating film 103.
従つて、本発明は、第３図に示す如く、ボンデ
イングパツド１とクランプダイオード３と接続す
る多結晶シリコン層１０５の直下の半導体基板１
０１中に、該半導体基板の導電型とは異なる導電
型の拡散層を設け、過大入力電圧によるフイール
ド絶縁膜１０３の破壊耐量を向上させたものであ
る。以下にその原理を説明する。 Therefore, as shown in FIG.
A diffusion layer of a conductivity type different from that of the semiconductor substrate is provided in the semiconductor substrate 01 to improve breakdown resistance of the field insulating film 103 due to excessive input voltage. The principle will be explained below.
第４図は、Ｎ型半導体基板１０１に対し、ボン
デイングパツド１が負になる様な静電気的パルス
電圧が加わつて、フイールド絶縁膜１０３が破壊
に至る場合の等価回路図である。すなわち、ボン
デイングパツド１とＮ型半導体基板１０１との間
には、絶縁膜容量５と、Ｎ型半導体基板１０１と
Ｐ型拡散層１０７の間で形成される接合容量６が
直列に存在している。これに上記のパルス電圧が
加わると、該絶縁膜容量５に加わる電圧は、瞬間
的には、絶縁膜容量値C1と接合容量値C2との容
量分割比C2／（C1＋C2）に、上記パルス電圧値
を乗じた値に相当する電圧となるため、絶縁膜１
０３の破壊電圧は、従来の接合容量６が存在しな
い場合と比べ、みかけ上、上昇することになる。
この結果、従来例えば、フイールド絶縁膜厚がお
よそ7000Åの場合、半導体基板に対して400〜
500Vの負電圧が入力端子に加わると、ボンデイ
ングパツド１からの接続用メタル配線層１０４と
多結晶シリコン層１０５とのコンタクト部１０８
において、容易にフイールド絶縁膜が破壊したの
に対し、Ｐ型拡散層１０７を多結晶シリコン下に
設けたものでは、破壊電圧は600〜700Vに改善さ
れた。また、このＰ型拡散層１０７は、他の拡散
層、メタル配線層とは電気信号的に完全に独立し
ているため、該Ｐ型拡散層が存在する由に、ラツ
チアツプ現象が生じ易くなるという不安は全くな
い。 FIG. 4 is an equivalent circuit diagram when an electrostatic pulse voltage is applied to the N-type semiconductor substrate 101 so that the bonding pad 1 becomes negative, and the field insulating film 103 is destroyed. That is, an insulating film capacitor 5 and a junction capacitor 6 formed between the N-type semiconductor substrate 101 and the P-type diffusion layer 107 exist in series between the bonding pad 1 and the N-type semiconductor substrate 101. There is. When the above pulse voltage is applied to this, the voltage applied to the insulating film capacitor 5 momentarily becomes equal to the capacitance division ratio C2/(C1+C2) between the insulating film capacitance value C1 and the junction capacitance value C2, and the voltage applied to the above pulse voltage Since the voltage corresponds to the value multiplied by the value, the insulating film 1
The breakdown voltage of 03 appears to be higher than that in the case where the conventional junction capacitance 6 does not exist.
As a result, conventionally, for example, when the field insulating film thickness was approximately 7000 Å, the
When a negative voltage of 500V is applied to the input terminal, the contact portion 108 between the connection metal wiring layer 104 from the bonding pad 1 and the polycrystalline silicon layer 105
In contrast to the case where the field insulating film was easily destroyed, in the case where the P-type diffusion layer 107 was provided under the polycrystalline silicon, the breakdown voltage was improved to 600 to 700V. Furthermore, since this P-type diffusion layer 107 is completely independent from other diffusion layers and metal wiring layers in terms of electrical signals, the existence of this P-type diffusion layer tends to cause latch-up phenomenon. I have no anxiety at all.
以上述べた様に、本発明は、MOSICの微細化
を進める上でフイールド絶縁膜厚を薄くする際遭
遇する、定格外の高電圧や、静電気によるフイー
ルド絶縁膜の破壊耐量を改善するとともにラツチ
アツプ現象を防止する上で十分な効果が発揮され
る。 As described above, the present invention improves the breakdown resistance of the field insulating film due to unrated high voltages and static electricity, which are encountered when reducing the thickness of the field insulating film to advance the miniaturization of MOSICs, and also reduces the latch-up phenomenon. It is sufficiently effective in preventing this.
第１図は、従来のＣ−MOSICの入力端子にお
ける破壊保護を示す回路図。第２図は従来の保護
抵抗の構造を説明するための断面図。第３図は本
発明による破壊保護機構を示す断面図。第４図は
フイールド絶縁膜に静電気的パルスが加わり絶縁
膜破壊を起すことを説明するため等価回路図であ
る。
１０１……Ｎ型半導体基板、１０３……フイー
ルド絶縁膜、１０５……多結晶シリコン層、１０
７……Ｐ型拡散層、５……絶縁膜容量、６……接
合容量。
FIG. 1 is a circuit diagram showing destruction protection at the input terminal of a conventional C-MOSIC. FIG. 2 is a cross-sectional view for explaining the structure of a conventional protective resistor. FIG. 3 is a sectional view showing the destruction protection mechanism according to the present invention. FIG. 4 is an equivalent circuit diagram for explaining that an electrostatic pulse is applied to a field insulating film, causing breakdown of the insulating film. 101... N-type semiconductor substrate, 103... Field insulating film, 105... Polycrystalline silicon layer, 10
7... P-type diffusion layer, 5... Insulating film capacitance, 6... Junction capacitance.
Claims (1)
ジスタを有する半導体装置において、第１導電型
の半導体基板中に設けられ、かつ電気的に独立し
ている第２導電型の拡散層、前記拡散層上に絶縁
膜を介して設けられた入力保護抵抗体、前記入力
保護抵抗体と入力パツドとを電気的に接続する第
１導電配線、前記入力保護抵抗体と前記内部回路
の入力部とを電気的に接続する第２導電配線を有
することを特徴とする半導体装置。 ２ 前記入力保護抵抗体が多結晶シリコンからな
るものであることを特徴とする特許請求の範囲第
１項記載の半導体装置。[Claims] 1. In a semiconductor device having a complementary MOS field effect transistor as an internal circuit, a second conductivity type diffusion layer provided in a first conductivity type semiconductor substrate and electrically independent; an input protection resistor provided on the diffusion layer via an insulating film, a first conductive wire electrically connecting the input protection resistor and the input pad, and an input section of the input protection resistor and the internal circuit. A semiconductor device characterized by having a second conductive wiring that electrically connects the two. 2. The semiconductor device according to claim 1, wherein the input protection resistor is made of polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57214468A JPS59104171A (en) | 1982-12-06 | 1982-12-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57214468A JPS59104171A (en) | 1982-12-06 | 1982-12-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59104171A JPS59104171A (en) | 1984-06-15 |
| JPH0454978B2 true JPH0454978B2 (en) | 1992-09-01 |
Family
ID=16656217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57214468A Granted JPS59104171A (en) | 1982-12-06 | 1982-12-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104171A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144454A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Semiconductor device |
| US4893212A (en) * | 1988-12-20 | 1990-01-09 | North American Philips Corp. | Protection of power integrated circuits against load voltage surges |
| JP2843393B2 (en) * | 1989-12-29 | 1999-01-06 | 沖電気工業株式会社 | Multi-level output circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51886A (en) * | 1974-06-20 | 1976-01-07 | Sony Corp | TEIKOSOSHI |
| JPS55110069A (en) * | 1979-02-16 | 1980-08-25 | Hitachi Ltd | Semiconductor memory device |
| JPS55141748A (en) * | 1979-04-20 | 1980-11-05 | Sony Corp | Thin film resistor for mos field effect transistor |
| JPS56146277A (en) * | 1980-04-15 | 1981-11-13 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-12-06 JP JP57214468A patent/JPS59104171A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51886A (en) * | 1974-06-20 | 1976-01-07 | Sony Corp | TEIKOSOSHI |
| JPS55110069A (en) * | 1979-02-16 | 1980-08-25 | Hitachi Ltd | Semiconductor memory device |
| JPS55141748A (en) * | 1979-04-20 | 1980-11-05 | Sony Corp | Thin film resistor for mos field effect transistor |
| JPS56146277A (en) * | 1980-04-15 | 1981-11-13 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59104171A (en) | 1984-06-15 |
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