JPS6355871B2 - - Google Patents
Info
- Publication number
- JPS6355871B2 JPS6355871B2 JP57086012A JP8601282A JPS6355871B2 JP S6355871 B2 JPS6355871 B2 JP S6355871B2 JP 57086012 A JP57086012 A JP 57086012A JP 8601282 A JP8601282 A JP 8601282A JP S6355871 B2 JPS6355871 B2 JP S6355871B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- input
- pad electrode
- electrode
- input pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 41
- 239000012535 impurity Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000010408 film Substances 0.000 description 18
- 239000005360 phosphosilicate glass Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体集積回路装置の構造に係り、特
に半導体集積回路装置の静電耐量を増す構造に関
する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor integrated circuit device, and particularly to a structure that increases the electrostatic withstand capacity of a semiconductor integrated circuit device.
(b) 技術の背景
MOS LSI等のMOS型半導体集積回路（IC）の
入力端子は、通常MOSトランジスタのゲート電
極に接続されているが、該ゲート電極は極めて絶
縁抵抗の高い酸化膜等により絶縁されているの
で、衣服、プラスチツク容器、その他LSIの保
存、取扱い中に発生する静電気によつて高い電圧
が加わり易い。この場合ゲート電極と半導体基板
間に形成されているゲート酸化膜が数100〔Å〕程
度の薄い膜であるために、数10〔Ｖ〕程度の低い
電圧で絶縁破壊を起しMOSトランジスタの機能
が失われる。(b) Background of the technology The input terminal of a MOS type semiconductor integrated circuit (IC) such as MOS LSI is usually connected to the gate electrode of a MOS transistor, but the gate electrode is insulated with an oxide film or the like with extremely high insulation resistance. Because of this, high voltages are likely to be applied due to static electricity generated during storage and handling of clothing, plastic containers, and other LSIs. In this case, since the gate oxide film formed between the gate electrode and the semiconductor substrate is a thin film of several hundred angstroms, dielectric breakdown occurs at a voltage as low as several tens of volts, causing the MOS transistor to function. is lost.
そのためMOS LSIに於ては、静電気やその他
の誤つて加えられる過電圧から特に容量の小さい
入力MOSトランジスタを保護するために入力保
護回路が配設される。 Therefore, in MOS LSIs, input protection circuits are provided to protect input MOS transistors with particularly small capacitance from static electricity and other accidentally applied overvoltages.
(c) 従来技術と問題点
入力保護回路に必要な特性は、LSIの正常な動
作範囲に於ては電流を流さず、異常電圧に対して
はゲートの破壊電圧よりも充分低い電圧で電流を
流して入力回路をクランプし、更にサージ電圧に
対して速やかに応答することである。(c) Prior art and problems The required characteristics of an input protection circuit are that no current flows within the normal operating range of the LSI, and that current flows at a voltage sufficiently lower than the breakdown voltage of the gate in response to abnormal voltages. The purpose of this is to clamp the input circuit by applying a current to the input circuit, and to quickly respond to surge voltage.
これらの条件を満たすものとして従来から用い
られている回路は、例えばｎチヤネルMOSに於
ては第１図に示すように、入力端子と入力MOS
トランジスタTRのゲート電極Ｇ間にPn接合ダイ
オード（Di）や直列抵抗Ｒが挿入された構造を
有しており基板Ｓに対して負電圧が入力端子に加
わつた時にはPn接合ダイオード（Di）の順方向
特性によつてこれをクランプし、正電圧が加わつ
た時にはダイオードDiの回復可能なブレークダ
ウンによつてこれをクランプし、更に直列抵抗の
分圧効果を利用してそのクランプ効果を更に向上
せしめる機能を有してなつていた。 A conventionally used circuit that satisfies these conditions is, for example, an n-channel MOS, as shown in Figure 1, which has an input terminal and an input MOS.
It has a structure in which a Pn junction diode (Di) and a series resistor R are inserted between the gate electrode G of the transistor T R , and when a negative voltage is applied to the input terminal with respect to the substrate S, the Pn junction diode (Di) This is clamped by the forward characteristic, and when a positive voltage is applied, it is clamped by the recoverable breakdown of the diode Di, and the clamping effect is further improved by using the voltage dividing effect of the series resistor. It has grown to have the function of encouraging people.
第２図は上記従来の入力保護回路の構造を示し
たもので、同図に於けるイはその透視平面図、ロ
はそのＡ−A′矢視断面図である。 FIG. 2 shows the structure of the conventional input protection circuit, in which ``A'' is a perspective plan view thereof, and ``B'' is a sectional view taken along the line A-A'.
即ち従来の入力保護回路に於て、入力MOSト
ランジスタTRのゲート電極Ｇは、例えばＰ型半
導体基板１に形成したn+型拡散領域２の一端部
に、電極コンタクト窓３ａおよび３ｃと上層配線
Ｌを介して接続され、入力端子即ち入力パツド電
極５は電極コンタクト窓３ｂを介してn+型拡散
領域２の他端部に接続されてなつていた。なお第
２図イに於ては、絶縁膜を省略して図示してあ
り、又第２図イに於て６及び７はn+型ドレイン
領域、第２図ロに於て８はフイールド酸化膜、９
はりん珪酸ガラス（PSG）絶縁膜を示す。 That is, in the conventional input protection circuit, the gate electrode G of the input MOS transistor T R is connected to the electrode contact windows 3a and 3c and the upper layer wiring at one end of the n + -type diffusion region 2 formed in the P-type semiconductor substrate 1, for example. The input terminal or input pad electrode 5 was connected to the other end of the n + -type diffusion region 2 via the electrode contact window 3b. Note that the insulating film is omitted in Figure 2A, and in Figure 2A, 6 and 7 are n + type drain regions, and in Figure 2B, 8 is a field oxidation region. membrane, 9
Shows a phosphosilicate glass (PSG) insulating film.
そして該構造に於ては、n+型拡散領域２とｐ
型半導体基板１の接合部に前記クランプ用のpn
接合ダイオード（Di）が形成され、更にn+型拡
散領域２が前記分圧効果を有する直列抵抗および
接合容量を構成する。 In this structure, the n + type diffusion region 2 and the p
The PN for the clamp is attached to the joint part of the type semiconductor substrate 1.
A junction diode (Di) is formed, and furthermore, the n + type diffusion region 2 constitutes a series resistance and a junction capacitance having the voltage dividing effect.
このような従来構造に於ては、n+型拡散領域
２が微小であり、入力パツド電極５及び入力
MOSトランジスタTRのゲート電極Ｇと該n+拡散
領域２との接続が電極コンタクト窓３ａ，３ｂ，
３ｃを介してなされる。そのため入力パツド電極
５に静電気等の高電圧が印加された際に、前記コ
ンタクト窓部に電界が集中するので接続破壊や接
合破壊を起し、回路が切断される場合がある。 In such a conventional structure, the n + type diffusion region 2 is minute, and the input pad electrode 5 and the input
The gate electrode G of the MOS transistor TR and the n + diffusion region 2 are connected through electrode contact windows 3a, 3b,
3c. Therefore, when a high voltage such as static electricity is applied to the input pad electrode 5, the electric field concentrates on the contact window, causing connection breakdown or junction breakdown, and the circuit may be disconnected.
(d) 発明の目的
本発明の目的は、上記入力トランジスタ保護用
の直列抵抗及びクランプ・ダイオードとなる第１
の不純物拡散領域と入力パツド電極の間に、所望
の接合容量を有し、且つ多数の電極コンタクト部
を有する第２の不純物拡散領域を並列に接続する
ことにより、前記第１の不純物拡散領域と入力パ
ツド電極の接続部に高パワーのサージ電圧が短時
間に印加されるのを防止せしめることにより、上
記問題点を除去することにある。(d) Object of the invention The object of the invention is to provide a first
A second impurity diffusion region having a desired junction capacitance and a large number of electrode contacts is connected in parallel between the impurity diffusion region and the input pad electrode. The object of the present invention is to eliminate the above-mentioned problems by preventing a high power surge voltage from being applied to the connection portion of the input pad electrode for a short period of time.
(e) 発明の構成
即ち本発明は、入力トランジスタに第１の不純
物拡散領域の一端部が接続され、該第１の不純物
拡散領域の他端部に入力パツド電極が接続される
半導体集積回路装置に於て、入力パツド電極の近
傍に前記第１の不純物拡散領域と同導電型の第２
の不純物拡散領域を設け、該第２の不純物拡散領
域を、該第２の不純物拡散領域上の絶縁膜に設け
た複数の電極コンタクト窓を介して該第２の不純
物拡散領域に前記入力パツド電極を接続してなる
ことを特徴とする。(e) Structure of the Invention In other words, the present invention provides a semiconductor integrated circuit device in which one end of a first impurity diffusion region is connected to an input transistor, and an input pad electrode is connected to the other end of the first impurity diffusion region. A second impurity diffusion region of the same conductivity type as the first impurity diffusion region is provided near the input pad electrode.
an impurity diffusion region is provided, and the second impurity diffusion region is connected to the input pad electrode through a plurality of electrode contact windows provided in the insulating film on the second impurity diffusion region. It is characterized by being connected.
(f) 発明の実施例
以下本発明を一実施例について、第３図に示す
透視平面図イ及びそのＡ−A′矢視断面図ロを用
いて詳細に説明する。(f) Embodiment of the Invention Hereinafter, one embodiment of the present invention will be described in detail with reference to a perspective plan view A and a sectional view B taken along the line A-A' of FIG.
なお透視平面図イに於ては、下層の絶縁膜及び
カバー絶縁膜は省略されている。 Note that in the perspective plan view A, the lower layer insulating film and the cover insulating film are omitted.
本発明の構造に於ては、例えば第３図イ及びロ
に示すように、フイールド酸化膜１１の上部領域
に下層PSG絶縁膜１２を介してアルミニウム
（Al）等からなる入力パツド電極１３が配設され
る。この入力パツド電極１３はその延出部１３′
の端部に於て、下層PSG絶縁膜１２の電極コン
タクト窓１４ａを介してｐ型シリコン（Si）基板
１５面に形成された第１のN+型拡散領域１６の
一端部に接続される。なお該第１のN+型拡散領
域１６は入力MOSトランジスタTRの保護抵抗及
びクランプ・ダイオードの機能を有しており、従
つて別の一端部は下層PSG絶縁膜１２の電極コ
ンタクト窓１４ｂ，１４ｃ及び上層配線Ｌを介し
て入力トランジスタTRのゲート電極Ｇに接続さ
れる。 In the structure of the present invention, as shown in FIGS. 3A and 3B, for example, an input pad electrode 13 made of aluminum (Al) or the like is disposed in the upper region of the field oxide film 11 with a lower PSG insulating film 12 interposed therebetween. will be established. This input pad electrode 13 has an extended portion 13'.
is connected to one end of a first N + -type diffusion region 16 formed on the surface of a p-type silicon (Si) substrate 15 through an electrode contact window 14 a of the lower PSG insulating film 12 . Note that the first N + type diffusion region 16 has the function of a protection resistor and a clamp diode for the input MOS transistor TR , and therefore, the other end portion is connected to the electrode contact window 14b of the lower PSG insulating film 12, 14c and the upper layer wiring L to the gate electrode G of the input transistor TR .
そして入力パツド電極１３近傍周辺部のｐ型Si
基板１５面に、該入力パツド電極１３を囲むよう
に第２のN+型拡散領域１７が配設されている。
そして該第２のN+型拡散領域１７は前記入力パ
ツド電極１３と第１のN+型拡散領域１６の間、
即ち入力パツド電極延出部１３′から入力バツド
電極１３と並列に入力パツド電極１３を囲む状態
に延出された環状電極１８によつて、第２のN+
型拡散領域１７上の下層PSG絶縁膜１２に形成
した多数個の電極コンタクト窓１４ｄ〜１４ｓを
介して、入力パツド電極１３に接続されてなつて
いる。 And the p-type Si in the vicinity of the input pad electrode 13
A second N + type diffusion region 17 is provided on the surface of the substrate 15 so as to surround the input pad electrode 13 .
The second N + type diffusion region 17 is located between the input pad electrode 13 and the first N + type diffusion region 16;
That is, the second N +
It is connected to the input pad electrode 13 through a large number of electrode contact windows 14d to 14s formed in the lower PSG insulating film 12 on the type diffusion region 17.
上記構造に於ては、入力パツド電極１３に印加
された静電気等の瞬時的高電圧は入力パツド電極
１３に接続している環状電極１８を経て、多数個
の電極コンタクト窓１４ｄ〜１４ｓに分散されこ
れら電極窓１４ｄ〜１４ｓを介して第２のN+型
拡散領域１７とｐ型Si基板１５間に形成される接
合容量に一時的に蓄積され、該容量と第１のN+
型拡散領域１６の抵抗とで構成される遅延特性に
沿つて徐々にクランプ・ダイオード（Di）を経
て放出されるので、入力MOSトランジスタTRの
ゲートＧ保護機能を持つ第１のN+型拡散領域１
６と入力パツド電極１３を接続するコンタクト窓
１４ａ部、及び第１のN+型拡散領域１６とゲー
ト電極Ｇを接続するコンタクト窓１４ｂ及び１４
ｃ部に高電圧が短時間に集中印加されることがな
くなる。 In the above structure, instantaneous high voltage such as static electricity applied to the input pad electrode 13 is distributed to a large number of electrode contact windows 14d to 14s via the annular electrode 18 connected to the input pad electrode 13. It is temporarily accumulated in the junction capacitance formed between the second N + type diffusion region 17 and the p-type Si substrate 15 through these electrode windows 14d to 14s, and the capacitance and the first N +
It is gradually discharged through the clamp diode (Di) according to the delay characteristic formed by the resistance of the type diffusion region 16, so that the first N + type diffusion which has the gate G protection function of the input MOS transistor TR Area 1
6 and the input pad electrode 13, and contact windows 14b and 14 that connect the first N + type diffusion region 16 and the gate electrode G.
High voltage is no longer intensively applied to portion c in a short period of time.
上記実施例に於ては、第２のN+型拡散領域１
７を入力パツド電極１３を囲む環状に形成した
が、該第２のN+型拡散領域は上記環状に限らな
い。即ち一部が欠けた不完全環状でも良く、又入
力パツド電極の近傍に１箇所又は数箇所に分けて
形成してもよい。そしてその容量はいずれの場合
も、該ICの動作速度を考慮して適切な値に選ば
ねばならない。 In the above embodiment, the second N + type diffusion region 1
7 is formed in an annular shape surrounding the input pad electrode 13, but the second N + type diffusion region is not limited to the above-mentioned annular shape. That is, it may have an incomplete annular shape with a portion missing, or it may be formed in one or several locations near the input pad electrode. In any case, the capacitance must be selected at an appropriate value in consideration of the operating speed of the IC.
なお上記実施例の構造を形成する際に、通常の
MOS ICを形成する工程以外に別な工程が追加さ
れ製造工程が複雑化することはない。 Note that when forming the structure of the above example, the usual
The manufacturing process does not become complicated by adding another process other than the process of forming the MOS IC.
即ち第３図に於けるMOSトランジスタTRのN+
型ソース領域１９、N+型ドレイン領域２０、第
１のN+型拡散領域１６、及び本発明の第２のN+
型拡散領域１７は選択酸化法によつて形成したフ
イールド酸化膜１１をマスクにして選択イオン注
入により同時に形成でき、又下層PSG絶縁膜１
２の各電極窓１４ａ〜１４ｓの形成も同時になさ
れる。そして又入力パツド電極１３、同延出部１
３′及び本発明の環状電極１８は同一電極材料層
から同時にパターンニングされる。（図中２１は
カバー絶縁膜）
(g) 発明の効果
以上説明したように本発明の構造に於ては、入
力パツド電極に印加された静電気等の高電圧は、
入力パツド電極と入力トランジスタの保護抵抗及
びクランプ・ダイオードとなる第１の不純物拡散
領域の間に配置された第２の不純物拡散領域に、
多数の電極コンタクト窓を介して分散供給され、
該第２の不純物拡散領域のpn接合容量に一時的
に蓄積される。従つて前記第１の不純物拡散領域
と入力パツド電極の接続部及び入力トランジスタ
のゲート電極との接続部に急激に高電圧が印加さ
れることがなくなり、これら接続部の破壊が防止
されるので、ICの静電耐量は増加する。 That is, N + of the MOS transistor T R in Fig. 3
type source region 19, N + type drain region 20, first N + type diffusion region 16, and second N + type of the present invention.
The type diffusion region 17 can be simultaneously formed by selective ion implantation using the field oxide film 11 formed by the selective oxidation method as a mask, and the lower PSG insulating film 1
The two electrode windows 14a to 14s are also formed at the same time. Also, the input pad electrode 13 and the extension part 1
3' and the annular electrode 18 of the present invention are simultaneously patterned from the same layer of electrode material. (21 in the figure is a cover insulating film) (g) Effects of the Invention As explained above, in the structure of the present invention, high voltage such as static electricity applied to the input pad electrode,
In a second impurity diffusion region disposed between the input pad electrode and the first impurity diffusion region serving as a protection resistor and a clamp diode for the input transistor,
distributed via a large number of electrode contact windows,
It is temporarily accumulated in the pn junction capacitance of the second impurity diffusion region. Therefore, a high voltage is not suddenly applied to the connection portion between the first impurity diffusion region and the input pad electrode and the connection portion to the gate electrode of the input transistor, and destruction of these connection portions is prevented. The electrostatic capacity of IC increases.
又本発明の構造に於ては、入力パツド電極はフ
イールド酸化膜の上部領域に設けられるので、ワ
イヤ・ボンデイングに対する耐性も極めて大き
い。 Also, in the structure of the present invention, since the input pad electrode is provided in the upper region of the field oxide film, resistance to wire bonding is also extremely high.
なお本発明の構造はいずれの導電型にも適用す
ることができ、更に出力パツド電極側に適用する
こともできる。 Note that the structure of the present invention can be applied to any conductivity type, and can also be applied to the output pad electrode side.
第１図は従来の入力保護回路図、第２図は従来
の入力保護回路の透視平面図イ及びＡ−A′矢視
断面図ロで、第３図は本発明の入力保護回路の透
視平面図イ及びＡ−A′矢視断面図ロである。
図に於て、１１はフイールド酸化膜、１２は下
層りん珪酸ガラス絶縁膜、１３は入力パツド電
極、１３′は入力パツド電極延出部、１４ａ〜１
４ｓは電極コンタクト窓、１５はｐ型シリコン基
板、１６は第１のN+型拡散領域、１７は第２の
N+型拡散領域、１８は環状電極、１９はN+型ソ
ース領域、２０はN+型ドレイン領域、TRは入力
MOSトランジスタ、Ｇはゲート電極、Ｌは上層
配線を示す。
Fig. 1 is a diagram of a conventional input protection circuit, Fig. 2 is a perspective plan view A and a sectional view B taken along the line A-A' of the conventional input protection circuit, and Fig. 3 is a perspective plane diagram of the input protection circuit of the present invention. Figure A and A-A' cross-sectional view B. In the figure, 11 is a field oxide film, 12 is a lower phosphosilicate glass insulating film, 13 is an input pad electrode, 13' is an input pad electrode extension, and 14a to 1
4s is an electrode contact window, 15 is a p-type silicon substrate, 16 is a first N + type diffusion region, and 17 is a second
N + type diffusion region, 18 is annular electrode, 19 is N + type source region, 20 is N + type drain region, T R is input
In the MOS transistor, G is a gate electrode, and L is an upper layer wiring.
Claims (1)
一端部が接続され、該第１の不純物拡散領域の他
端部に入力パツド電極が接続される構造に於て、
入力パツド電極の近傍に前記第１の不純物拡散領
域と同導電型の第２の不純物拡散領域を設け、該
第２の不純物拡散領域上の絶縁膜に設けた複数の
電極コンタクト窓を介して該第２の不純物拡散領
域に前記入力パツド電極を接続してなることを特
徴とする半導体集積回路装置。1. In a structure in which one end of a first impurity diffusion region is connected to the input transistor, and an input pad electrode is connected to the other end of the first impurity diffusion region,
A second impurity diffusion region of the same conductivity type as the first impurity diffusion region is provided near the input pad electrode, and a second impurity diffusion region is provided in the vicinity of the input pad electrode. A semiconductor integrated circuit device, characterized in that the input pad electrode is connected to a second impurity diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57086012A JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57086012A JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58202573A JPS58202573A (en) | 1983-11-25 |
| JPS6355871B2 true JPS6355871B2 (en) | 1988-11-04 |
Family
ID=13874765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57086012A Granted JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58202573A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0746717B2 (en) * | 1985-05-17 | 1995-05-17 | 日本電気株式会社 | Semiconductor device |
| US4806999A (en) * | 1985-09-30 | 1989-02-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Area efficient input protection |
| JPH0828426B2 (en) * | 1985-10-15 | 1996-03-21 | エイ・ティ・アンド・ティ・コーポレーション | Protection of IGFET integrated circuits from electrostatic discharge |
-
1982
- 1982-05-21 JP JP57086012A patent/JPS58202573A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58202573A (en) | 1983-11-25 |
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