JPS6290963A - Mos semiconductor circuit - Google Patents

Mos semiconductor circuit

Info

Publication number
JPS6290963A
JPS6290963A JP23170485A JP23170485A JPS6290963A JP S6290963 A JPS6290963 A JP S6290963A JP 23170485 A JP23170485 A JP 23170485A JP 23170485 A JP23170485 A JP 23170485A JP S6290963 A JPS6290963 A JP S6290963A
Authority
JP
Japan
Prior art keywords
region
conductivity type
protection circuit
surge voltage
input protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23170485A
Other languages
Japanese (ja)
Inventor
Shozo Shirota
城田　省三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23170485A priority Critical patent/JPS6290963A/en
Publication of JPS6290963A publication Critical patent/JPS6290963A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make an MOS semiconductor circuit withstand an excess surge voltage by forming the first conductivity first diffused region in high impurity density and the first conductivity type first diffused region in lower density than the first diffused region through the first conductivity type second diffused region on the second conductivity type semiconductor substrate. CONSTITUTION:An N<+> type region 10 of the first conductivity type first diffused region in high impurity density and an N<-> type region 11 of the first conductivity type second diffused region of lower impurity density than the region 10 are formed on a P-type semiconductor substrate 12. In this input protecting circuit, N<+>-N<->-P structure is formed to increase the insulating withstand of the junction formed between the region 10, the region 11 and the substrate 12, and even if an excess surge voltage is applied, a junction damage does not occur but the function of the input projecting circuit is achieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、破壊防止用の入力保護回路を有するＭＯＳ
半導体回路に関するものであ・る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS device having an input protection circuit for preventing destruction.
It is related to semiconductor circuits.

〔従来の技術〕[Conventional technology]

ＭＯ８半導体回路においては、一般にゲート絶縁膜が非
常に薄い酸化膜（数百人オーダ）で形成されているため
、外部より過大なサージ電圧が加わった場合にこの酸化
膜が絶縁破壊を起こし、致命価となる恐れがある。その
ため、はとんどのＭＯ８半導体回路の入力端子にサージ
電圧による破壊を防止するための入力保護回路が設けら
れている。In MO8 semiconductor circuits, the gate insulating film is generally formed of a very thin oxide film (on the order of several hundred layers), so if an excessive surge voltage is applied from the outside, this oxide film will cause dielectric breakdown, which can be fatal. There is a risk that it will become expensive. Therefore, most MO8 semiconductor circuits are provided with an input protection circuit at their input terminals to prevent damage caused by surge voltage.

従来の破壊防止用の入力保護回路としては、例えば第３
図（ａ）　、　（ｂ）　、　（ｅ）に示すようなものが
ある。As a conventional input protection circuit for preventing damage, for example,
There are those shown in Figures (a), (b), and (e).

これらの図においてｉａ、ｌｂ、ｉｃはＭＯ８半導体回
路の入力端子、２ａ、２ｂ、２ｃは不純物拡散あるいは
ポリシリコンによって形成された抵抗領域、３ａ、３ｂ
はサージ電圧吸収用のダイオード、４ａ、４ｂは同じく
サージ電圧吸収用のダイオード、５ｎｐ　５ｂｐ　５ｃ
は入力信号を受けるトランジスタ、６はサージ電圧吸収
用のオフトランジスタである。In these figures, ia, lb, and ic are input terminals of the MO8 semiconductor circuit, 2a, 2b, and 2c are resistance regions formed by impurity diffusion or polysilicon, and 3a, 3b.
is a diode for absorbing surge voltage, 4a and 4b are diodes for absorbing surge voltage, 5np 5bp 5c
6 is a transistor for receiving an input signal, and 6 is an off-transistor for absorbing surge voltage.

第４図ｈ）、　（ｂ）はＭＯ８半導体回路において、第
３図（ａ）〜（ｅ）に示した入力保護回路内の抵抗領域
２ａ、２ｂおよび２ｃに対応する部分の構造を示す断面
図で、第４図（ａ）は抵抗領域２ａ、２ｂおよび２ｃが
不純物拡散で形成されている場合を示し、第４図（ｂ）
は抵抗領域２ａおよび２ｃがポリシリコンで形成されて
いる場合を示す。これらの図において、２′は不純物拡
散領域、２“はポリシリコン、７はアルミニウム配線、
８は酸化膜、９は半導体基板であるっ 次に動作について説明する。第３図（ａ）、　（ｂ）に
示した入力保護回路は、ＭＯ８半導体回路で従来より用
いられている入力保護回路であり、入力端子１ａあるい
は１ｂより印加される過大なサージ電圧は、抵抗領域２
ａあるいは２ｂとトランジスタ５ａあるいは５ｂの入力
容量等の容量で決まる時定数に従って、トランジスタ５
ａあるいは５ｂのゲートに印加される。ダイオード３ａ
、４ａあるいは３ｂ、４ｂは、ゲーＩ・に印加されるサ
ージ電圧がゲートの絶縁破壊電圧に達する前に吸収し、
ゲートに絶縁破壊電圧以上の電圧が加わらないようにす
るクランプダイオードの役目をする。ダイオード３ａあ
るいは３ｂは正極性のサージ電圧に対するクランプダイ
オードとして働き、ダイオード４ａあるいは４ｂは負極
性のサージ電圧に対するクランプダイオードとして働く
。Figures 4h) and 4(b) are cross-sectional views showing the structure of portions of the MO8 semiconductor circuit corresponding to the resistance regions 2a, 2b and 2c in the input protection circuit shown in Figures 3(a) to (e). 4(a) shows the case where the resistance regions 2a, 2b and 2c are formed by impurity diffusion, and FIG. 4(b) shows the case where the resistance regions 2a, 2b and 2c are formed by impurity diffusion.
shows the case where resistance regions 2a and 2c are formed of polysilicon. In these figures, 2' is an impurity diffusion region, 2'' is polysilicon, 7 is aluminum wiring,
Reference numeral 8 represents an oxide film, and reference numeral 9 represents a semiconductor substrate.The operation will now be described. The input protection circuit shown in FIGS. 3(a) and 3(b) is an input protection circuit conventionally used in MO8 semiconductor circuits, and excessive surge voltage applied from input terminal 1a or 1b is Area 2
The transistor 5
It is applied to the gate of a or 5b. diode 3a
, 4a or 3b, 4b absorbs the surge voltage applied to the gate I before it reaches the dielectric breakdown voltage of the gate,
It acts as a clamp diode to prevent voltage higher than dielectric breakdown voltage from being applied to the gate. The diode 3a or 3b functions as a clamp diode for a positive surge voltage, and the diode 4a or 4b functions as a clamp diode for a negative surge voltage.

第３図（ｅ）に示した入力保護回路は、通常片チャネル
（７）ＭＯＳ半導体回路で用いられる。動作は上記の入
力保護回路の場合とほぼ同じであるが、この入力保護回
路では、常にオフ状態のオフトランジスタ６が正負両極
性のサージ電圧に対するクランプの役目をする。The input protection circuit shown in FIG. 3(e) is normally used in a single channel (7) MOS semiconductor circuit. The operation is almost the same as that of the input protection circuit described above, but in this input protection circuit, the OFF transistor 6, which is always in an OFF state, serves as a clamp against surge voltages of both positive and negative polarities.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の入力保護回路では、抵抗領域２ａ、
２ｂおよび２ｃとしては第４図（ａ）　、　（ｂ）に示
すように不純物拡散領域２′またはポリシリコン２”が
用いられているが、８第４図ｂ）に”示すような不純物
拡散領域２′に過大なサージ電圧が加わると、不純物拡
散領域２′と半導体基板９との間に形成されるＰＮ接合
が破壊され、大きなサージ電圧に耐えられなくなる。ま
た第４図（ｂ）に示ずようなポリシリコン２＃に過大な
サージ電圧が加わると、ポリシリコン２″′が半導体基
板９と接していないために放熱が悪く、ポリシリコン２
′が溶断するという問題点があった。In the conventional input protection circuit as described above, the resistance region 2a,
As shown in FIGS. 4(a) and 4(b), impurity diffusion regions 2' or polysilicon 2'' are used as 2b and 2c. If an excessive surge voltage is applied to 2', the PN junction formed between impurity diffusion region 2' and semiconductor substrate 9 will be destroyed, making it unable to withstand the large surge voltage. Furthermore, if an excessive surge voltage is applied to polysilicon 2# as shown in FIG.
There was a problem that ′ would melt.

この発明は、かかる問題点を解決するためになされたも
ので、過大なサージ電圧に耐えられ信頼性の高い入力保
護回路を有するＭＯ８半導体回路を得ることを目的とす
る。The present invention was made to solve such problems, and an object of the present invention is to obtain an MO8 semiconductor circuit having an input protection circuit that can withstand excessive surge voltage and has high reliability.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るＭＯＳ半導体回路は、高不純物濃度で第
１の導電型の第１の拡散領域を、この第１の拡散領域よ
り不純物濃度が低く同じく第１の導電型の第２の拡散領
域を介して第２の導電型の半導体基板上に形成すること
により構成される入力保護回路を備えたものである。The MOS semiconductor circuit according to the present invention includes a first diffusion region of the first conductivity type with a high impurity concentration, and a second diffusion region of the first conductivity type with a lower impurity concentration than the first diffusion region. The input protection circuit is formed by forming the input protection circuit on the semiconductor substrate of the second conductivity type through the semiconductor substrate.

〔作用〕[Effect]

この発明においては、第１の拡散領域と半導体基板間に
第２の拡散領域を設けたので、第１の拡散領域と半導体
基板間の接合の絶縁耐量が増す。In this invention, since the second diffusion region is provided between the first diffusion region and the semiconductor substrate, the dielectric strength of the junction between the first diffusion region and the semiconductor substrate is increased.

〔実施例〕〔Example〕

第１図はこの発明のＭＯ８半導体回路における入力保護
回路の一実施例の構成を示す断面図で、第４図（ａ）、
　（ｂ）と同一符号は同一または相当部分を示し、１０
は高不純物濃度で第１の導導電型の第１の拡散領域であ
るｎ＋領領域１１は前記ｎ＋領領域ｏより不純物濃度が
低く第１の導電型の第２の拡散領域であるｎ−領域、１
２はｐ型の半導体基板である。FIG. 1 is a sectional view showing the configuration of an embodiment of an input protection circuit in an MO8 semiconductor circuit according to the present invention, and FIG. 4(a),
The same reference numerals as in (b) indicate the same or equivalent parts, and 10
The n+ region 11 is a first diffusion region of a first conductivity type and has a high impurity concentration.The n+ region 11 is a second diffusion region of a first conductivity type and has a lower impurity concentration than the n+ region o. ,1
2 is a p-type semiconductor substrate.

この入力保護回路では、ｎ＋−ｎ−−ｐ構成とすること
により、ｎ＋領域１０．ｎ−領域１１とｐ型の半導体基
板１２との間に形成される接合の絶縁耐量が増し、過大
なサージ電圧が加わった場合でも接合破壊を起こすこと
なく入力保護回路の機能を果すことができる。In this input protection circuit, the n+ region 10. The dielectric strength of the junction formed between the n-region 11 and the p-type semiconductor substrate 12 is increased, and even when an excessive surge voltage is applied, the input protection circuit can function without causing junction breakdown. .

なお、ｎ−領域１１の形成をＣＭＯ８半導体回路におい
ては、アイランド工程で実現することができろ。Note that the formation of n- region 11 can be realized by an island process in a CMO8 semiconductor circuit.

また上記実施例では、ｎ＋領域１０およびロー領域１１
を抵抗として使用する場合を示したが、第２図に示すよ
うに接合をダイオードとして使用してもよい。Further, in the above embodiment, the n+ region 10 and the low region 11
Although the case where the junction is used as a resistor is shown, the junction may be used as a diode as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、高不純物濃度で第１の
導電型の第１の拡散領域を、この第１の拡散領域より不
純物濃度が低く同じく第１の導電型の第２の拡散領域を
介して第２の導電型の半導体基板上に形成することによ
り構成される入力保護回路を備えたので、第１の拡散領
域と半導体基板間の接合の絶縁耐量が増し、しかも熱伝
性が阻害されないので過大なサージ電圧に耐えられ、信
頼性が高くなるという効果がある。As explained above, the present invention connects a first diffusion region of a first conductivity type with a high impurity concentration through a second diffusion region of the same first conductivity type and with a lower impurity concentration than the first diffusion region. Since the input protection circuit is formed by forming the input protection circuit on the semiconductor substrate of the second conductivity type, the dielectric strength of the junction between the first diffusion region and the semiconductor substrate is increased, and thermal conductivity is not inhibited. Therefore, it has the effect of being able to withstand excessive surge voltage and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明のＭＯＳ半導体回路における入力保護
回路の一実施例の構成を示す断面図、第２図はこの発明
のＭＯＳ半導体回路における入力保護回路の他の実施例
の構造を示す断面図、第３図（ａ）、　ｆｂ）、　（’
ｅ）は従来の入力保護回路Ｑ構造を示す断面図、第４図
（ａ）、　（ｂ）は従来の入力保護回路の構造を示す断
面図である。 図において、１０はｎ＋拡散領域、１１はｎ−拡散領域
、１２はｐ型の半導体基板である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人　大　岩　増　雄　　　（外２名）第１図 第２図FIG. 1 is a sectional view showing the structure of one embodiment of the input protection circuit in the MOS semiconductor circuit of the present invention, and FIG. 2 is a sectional view showing the structure of another embodiment of the input protection circuit in the MOS semiconductor circuit of the invention. , Fig. 3(a), fb), ('
4e) is a sectional view showing the structure of a conventional input protection circuit Q, and FIGS. 4(a) and 4(b) are sectional views showing the structure of the conventional input protection circuit. In the figure, 10 is an n+ diffusion region, 11 is an n- diffusion region, and 12 is a p-type semiconductor substrate. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 高不純物濃度で第１の導電型の第１の拡散領域を、この
第１の拡散領域より不純物濃度が低く同じく第１の導電
型の第２の拡散領域を介して第２の導電型の半導体基板
上に形成することにより構成される入力保護回路を備え
たことを特徴とするＭＯＳ半導体回路。A first diffusion region of the first conductivity type with a high impurity concentration is connected to a semiconductor of the second conductivity type via a second diffusion region of the first conductivity type and with a lower impurity concentration than the first diffusion region. A MOS semiconductor circuit comprising an input protection circuit formed on a substrate.
JP23170485A 1985-10-16 1985-10-16 Mos semiconductor circuit Pending JPS6290963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23170485A JPS6290963A (en) 1985-10-16 1985-10-16 Mos semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23170485A JPS6290963A (en) 1985-10-16 1985-10-16 Mos semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS6290963A true JPS6290963A (en) 1987-04-25

Family

ID=16927694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23170485A Pending JPS6290963A (en) 1985-10-16 1985-10-16 Mos semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS6290963A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0234963A (en) * 1988-07-25 1990-02-05 Nec Corp Semiconductor integrated circuit
JPH03272180A (en) * 1990-03-22 1991-12-03 Toshiba Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0234963A (en) * 1988-07-25 1990-02-05 Nec Corp Semiconductor integrated circuit
JPH03272180A (en) * 1990-03-22 1991-12-03 Toshiba Corp Semiconductor integrated circuit

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