JPS5916365A - Complementary semiconductor device - Google Patents
Complementary semiconductor deviceInfo
- Publication number
- JPS5916365A JPS5916365A JP57125423A JP12542382A JPS5916365A JP S5916365 A JPS5916365 A JP S5916365A JP 57125423 A JP57125423 A JP 57125423A JP 12542382 A JP12542382 A JP 12542382A JP S5916365 A JPS5916365 A JP S5916365A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- substrate
- poly
- diffusion layer
- vcc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 230000000295 complement effect Effects 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 28
- 210000004027 cell Anatomy 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は相補型半導体装置（以下ＣＭＯ８ＩＣと称する
）に係り、特にその電源配線の配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary semiconductor device (hereinafter referred to as CMO8IC), and particularly to the wiring structure of its power supply wiring.
ＣＭＯ８ＩＣに於いては、本質的に存在するＰＮＰＮ構
造によりラッチアップ現象が発生し、ＣＭＯ８ＩＣの動
作範囲を制限している。これに対して、レイアウト上さ
まざまな対策が考えられているが、内部ブロックに於て
はチップサイズを大きくしたくないために充分な対策を
ほどこすことは難かしい。In the CMO8IC, a latch-up phenomenon occurs due to the inherently existing PNPN structure, which limits the operating range of the CMO8IC. Various layout countermeasures have been considered to deal with this, but it is difficult to take sufficient countermeasures because it is not desired to increase the chip size in internal blocks.
しかしながらレイアウトルールのスケールダウンが進む
につれて、レイアウトルールの厳しい内部フｂツクでラ
ッチアップ現象がおき易くってきており、チップ上あま
り面積を占めない範囲でなんらかの対策が必要になって
きている。However, as layout rules are scaled down, latch-up phenomena are becoming more likely to occur in internal hooks with strict layout rules, and it is becoming necessary to take some kind of countermeasure within the range of not occupying too much area on the chip.
まず従来から用いられているＰ・ウェル方式ＣＭＯ８Ｉ
Ｃを例にとり、第１図を用いてラッチアップに対する一
般的対策を次に述べる。ラッチアップはＶＣＣ端子１に
つながるＮ型シリコン基板上のＰ十拡散層３と、ＧＮＤ
（グランド）端子２につながるＰウェル上のＮ十拡散層
４の間で、Ｐ十拡散層３−Ｎ型シリコン基板−Ｐウェル
から構成されるＰＮＰパイボーラントランジスタと、Ｎ
十散散Ｉ＠４−Ｐウェル−Ｎ型シリコン基板から構成さ
れる。First, the conventionally used P-well type CMO8I
Taking C as an example, general countermeasures against latch-up will be described below using FIG. Latch-up occurs between the P1 diffusion layer 3 on the N-type silicon substrate connected to the VCC terminal 1, and the GND
Between the N1 diffusion layer 4 on the P well connected to the (ground) terminal 2, a PNP piborane transistor consisting of the P1 diffusion layer 3 - the N type silicon substrate - the P well, and the N
It is composed of ten scattered I@4-P well-N type silicon substrates.
ＮＰＮバイポーラトランジスタの双方がイオン状態にな
ったときおこる。このときｖ（Ｃ端子１とＧＮＤ端子２
の間はショート状態となる。ラッチアップはＰ十拡散層
３とＮ十拡散層４の距離が小さくなるにつれておきやす
くなる。ラッチアップ全おきにくくするには、（１）Ｎ
型シリコン基板の電位の変動を防ぐために、基板表面は
形成されたＮ十拡散層５を介して基板をＶＣＣにつなぐ
、（２）Ｐウェル電の変動を防ぐために、Ｐウェル表面
に形成されたＰ十拡散層６を介して、ＰウェルをＧＮＤ
端子につなぐ、（３）ラッチアップのトリガとなる電流
をリミットするためにＶＣＣ端子１をＰ十拡散廣３の間
に抵抗Ｉｔ、を入れ、またはＧＮＩ）端子２とＮ十拡散
層４の間に抵抗Ｒ，２を入れるなどの方法がある。This occurs when both NPN bipolar transistors are in the ionic state. At this time, v(C terminal 1 and GND terminal 2
During this period, it is in a short-circuit state. Latch-up becomes easier as the distance between the P10 diffusion layer 3 and the N10 diffusion layer 4 becomes smaller. To make latch-up less likely, (1) N
In order to prevent fluctuations in the potential of the silicon substrate, the substrate surface connects the substrate to VCC through the formed N+ diffusion layer 5. (2) In order to prevent fluctuations in the P well voltage, a Connect the P well to GND through the P well diffusion layer 6
(3) Insert a resistor It between the VCC terminal 1 and the P + diffusion layer 3, or between the GNI) terminal 2 and the N + diffusion layer 4, to limit the current that triggers latch-up. There is a method such as inserting a resistor R,2 into.
このとき抵抗値を約５００Ω以上とすればラッチアップ
防止に効果がある。At this time, setting the resistance value to approximately 500Ω or more is effective in preventing latch-up.
従来ＶＣＣ端子とつながる内部ブロック内のＮ型基板上
のＰ十拡散層は、アルミニウムを用いてＶ（ＸＥ端子と
結ばれＣいる。ＧＮＤ端子とつながるＰウェル上のＮ十
拡散層に関しても同様である。Conventionally, the P1 diffusion layer on the N type substrate in the internal block connected to the VCC terminal is connected to the V (XE terminal) using aluminum.The same goes for the N1 diffusion layer on the P well connected to the GND terminal. be.
本発明は、相補型半導体装置に於て、パッドから金属配
線によシ直接のびている電源配線と、内部ブロックの電
源配線とを、拡散層以外の約５０００以上の抵抗素子を
介してらなぎ、かつ抵抗素子のパッド側の端部に近接し
た所で、電源配線と、その電源配線と同一電位にある半
導体基板または半導体基板表面に形成されたウェルとを
、電気的に接続させることによシ、より高集積度でＰ十
拡散層とＮ十拡散層の距離が短かい相補型半導体装置の
ラッチアップ発生を防止することを目的にしでいる。In a complementary semiconductor device, the present invention connects a power supply wiring extending directly from a pad to a metal wiring and a power supply wiring of an internal block through approximately 5,000 or more resistive elements other than a diffusion layer, and By electrically connecting the power supply wiring to a semiconductor substrate or a well formed on the surface of the semiconductor substrate that is at the same potential as the power supply wiring, in the vicinity of the end of the resistor element on the pad side. The purpose of this invention is to prevent latch-up in a complementary semiconductor device with a higher degree of integration and a shorter distance between the P+ diffusion layer and the N+ diffusion layer.
内部ブロックの電源電位のレベル降下が問題になるとき
は、本発明を適用することができない場合も生ずる。し
かしながら、例えばＣＭＯＳメモリＩＣに於てはセルの
■ＣＣ配線は数にΩの拡散層により形成されておシ、外
部のＶｃｃ配線とセル部のＶｃｃ配線の間に５００Ω〜
数にΩの抵抗を入れても回路動作上問題にならない。Ｃ
ＭＯＳメモリＩＣではセル部のレイアウト基準が最も厳
しくラッチアップがセル部でおきる可能性が高く、本発
明を適用することは、 ＣＭＯＳメモリＩＣのラッチア
ップ防止に大きな効果をもつ。When a drop in the level of the power supply potential of an internal block becomes a problem, the present invention may not be applicable. However, in a CMOS memory IC, for example, the CC wiring of a cell is formed by a diffusion layer with several Ω, and the resistance between the external Vcc wiring and the Vcc wiring in the cell part is 500 Ω or more.
Even if a resistor of Ω is included in the number, there will be no problem in circuit operation. C
In a MOS memory IC, the layout standards for the cell part are the most strict, and there is a high possibility that latch-up will occur in the cell part, so applying the present invention has a great effect on preventing latch-up in a CMOS memory IC.
以下具体例を用いて本発明を説明する。第２図は従来か
ら行なわれているＣＭＯＳメモリＩＣに於けるセル部１
３のＶＣＣ拡散層配線７とＶＣＣパッドから引き出され
ている外部のＶＣＣアルミニウム配線８とのつなぎ方を
示す。Ｖｃｃアルミニウム配線はセル部のＶＣＣ拡散層
配線とコンタクトホール９を介して直結されている。そ
のため前記コンタクトホール付近に於ては、コンタクト
ホールからはじまるＶｃｃ拡散層配線の抵抗が小さく、
この付近でラッチアップがおきやすい。The present invention will be explained below using specific examples. Figure 2 shows the cell section 1 in a conventional CMOS memory IC.
3 shows how to connect the VCC diffusion layer wiring 7 of No. 3 to the external VCC aluminum wiring 8 drawn out from the VCC pad. The Vcc aluminum wiring is directly connected to the VCC diffusion layer wiring in the cell portion via a contact hole 9. Therefore, near the contact hole, the resistance of the Vcc diffusion layer wiring starting from the contact hole is small.
Latch-up is likely to occur around this area.
かかる問題点を解決するため、本発明を適用した例を第
３図に示す。第３図に於て、外部のＶｃｃアルミニウム
配線８とセル部１３の拡散層配線７は、ポリシリコン抵
抗１０を介して結ばれている。In order to solve this problem, an example in which the present invention is applied is shown in FIG. In FIG. 3, external Vcc aluminum wiring 8 and diffusion layer wiring 7 of cell section 13 are connected via polysilicon resistor 10. In FIG.
このポリシリコン抵抗は、厚さ５０００Ａのポリシリコ
ンに１Ｘ１ｏ ／−のドーズ象でリンをドープしてつ
くる。巾５μｍ、長さ１５μｍ程度で約１にΩの抵抗が
つくられる。８′はポリシリコン１０と拡散層配線７と
をコンタクトホール９および９′を介してつなぐアルミ
ニウム配線である。さらにラッチアップをおきにくくす
るためにコンタクトホール１１とシリコン基板上のシリ
コン基板と同−不純物型の拡散層領域１２を介して基板
をＶＣＣ電位に保っている。This polysilicon resistor is made by doping polysilicon with a thickness of 5000 Å with phosphorus at a dose of 1×1o/−. A resistance of about 1Ω is created with a width of about 5 μm and a length of about 15 μm. Reference numeral 8' denotes an aluminum wiring connecting polysilicon 10 and diffusion layer wiring 7 via contact holes 9 and 9'. Further, in order to prevent latch-up from occurring, the substrate is maintained at VCC potential through a contact hole 11 and a diffusion layer region 12 of the same impurity type as the silicon substrate on the silicon substrate.
以上の２つの対策によりレイアウト基準のよシ厳しいＣ
ＭＯＳメモリＩＣに於いてもラッチアップを防止するこ
とができる。Due to the above two measures, the layout standards are stricter.
Latch-up can also be prevented in MOS memory ICs.
即ち本発明は、より高密度のＣＭＯＳメモリＩＣのラッ
チアップ防止対策として、非常に有用である。That is, the present invention is very useful as a measure to prevent latch-up in higher density CMOS memory ICs.
【図面の簡単な説明】
第１図はラッチアップ現象を説明するために模式的に表
わした半導基板の断面図、第２図は従来の０ＭＯ８ＩＣ
に於ける外部ＶＣＣ配線とセル部Ｖｃｃ配線のつなぎ方
を表わす平面図、第３図は本発明を適用したときの前記
２配線間のつなぎ方を表わす平面図、である。
なお図において、１・・・・・・Ｖｃｃ箪源端子、２・
・・・・・ＧＮＤ電源端子、３・・・・・・ｐ十拡散層
、４・・・・・・Ｎ十拡散層、訃・・・・・基板電位を
とる／こめのＮ＋拡散層。
６・・・・・・Ｐウェル電位をとるだめのＮ十拡散層、
７・・・・・・セル部のＶｃｃ拡散層配線、８・・・・
・・外部のＶｃｃアルミニウム配線、８′・・・・・・
アルミニウム配線、９・・・・・・拡散層とアルミニウ
ム配線をつなぐコンタクト、９′・・・・・・ポリシリ
コンとアルミニウム配線をつなぐコンタクト、１０・・
・・・・ポリシリコン抵抗、１１・・・・・・基板電位
をとるだめのコンタクト、１２・・・・・・基板電位を
とるための炉−拡散層、１３・・・・・・セルブロック
、である。
、−ゝ、
代理人弁理士内原 晋１″゛ゝ；
・ ／[Brief explanation of the drawings] Figure 1 is a cross-sectional view of a semiconductor substrate schematically shown to explain the latch-up phenomenon, and Figure 2 is a conventional 0MO8IC.
FIG. 3 is a plan view showing how to connect the external VCC wiring and the cell part Vcc wiring in the case of the present invention, and FIG. 3 is a plan view showing how to connect the two wirings when the present invention is applied. In the figure, 1...Vcc power source terminal, 2...
...GND power supply terminal, 3...P1 diffusion layer, 4...N10 diffusion layer, 2...N+ diffusion layer that takes the substrate potential. 6...N10 diffusion layer for taking P well potential,
7... Vcc diffusion layer wiring in cell section, 8...
...External Vcc aluminum wiring, 8'...
Aluminum wiring, 9...Contact connecting the diffusion layer and aluminum wiring, 9'...Contact connecting polysilicon and aluminum wiring, 10...
... Polysilicon resistor, 11 ... Contact for taking substrate potential, 12 ... Furnace-diffusion layer for taking substrate potential, 13 ... Cell block , is. ,−ゝ、Representative Patent Attorney Susumu Uchihara 1″゛ゝ; ・ /
Claims (2)
ｈパッドから金属層により延在している電源配線途中に
５０００以上の抵抗値を有する抵抗素子が挿入され、か
つ該抵抗素子の前記１を極パッド側の端部に近接した所
で前記電源配線と同一電位にある半導体基板表面に形成
されたウェルとが電気的に接続されていることを特徴と
する相補型半導体装置。(1) In a complementary semiconductor device, on a semiconductor substrate! T
A resistor element having a resistance value of 5,000 or more is inserted in the middle of the power supply wiring extending from the h pad by a metal layer, and the power supply wiring 1. A complementary semiconductor device characterized in that a well formed on a surface of a semiconductor substrate that is at the same potential as a well is electrically connected to a well formed on a surface of a semiconductor substrate.
ていることを特徴とする特許請求の範囲第（１）項記載
の相補型半導体装置。(2) The complementary semiconductor device according to claim (1), wherein the resistance element is formed including a polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57125423A JPS5916365A (en) | 1982-07-19 | 1982-07-19 | Complementary semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57125423A JPS5916365A (en) | 1982-07-19 | 1982-07-19 | Complementary semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5916365A true JPS5916365A (en) | 1984-01-27 |
| JPS6362110B2 JPS6362110B2 (en) | 1988-12-01 |
Family
ID=14909729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57125423A Granted JPS5916365A (en) | 1982-07-19 | 1982-07-19 | Complementary semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916365A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116864A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Cmos semiconductor integrated circuit device |
| JPH07326772A (en) * | 1995-05-25 | 1995-12-12 | Rohm Co Ltd | Discrete diode device |
| JPH088446A (en) * | 1995-05-25 | 1996-01-12 | Rohm Co Ltd | Discrete diode |
| JPH0832092A (en) * | 1995-05-25 | 1996-02-02 | Rohm Co Ltd | Discrete diode |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0553712A1 (en) * | 1992-01-29 | 1993-08-04 | Kaltenbach & Voigt Gmbh & Co. | Laser treatment device, especially for medical or dental use |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5458374A (en) * | 1977-10-19 | 1979-05-11 | Hitachi Ltd | Complementary mis ic |
| JPS56133865A (en) * | 1980-03-21 | 1981-10-20 | Seiko Epson Corp | Complementary mos transistor with high breakdown voltage |
-
1982
- 1982-07-19 JP JP57125423A patent/JPS5916365A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5458374A (en) * | 1977-10-19 | 1979-05-11 | Hitachi Ltd | Complementary mis ic |
| JPS56133865A (en) * | 1980-03-21 | 1981-10-20 | Seiko Epson Corp | Complementary mos transistor with high breakdown voltage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116864A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Cmos semiconductor integrated circuit device |
| JPH07326772A (en) * | 1995-05-25 | 1995-12-12 | Rohm Co Ltd | Discrete diode device |
| JPH088446A (en) * | 1995-05-25 | 1996-01-12 | Rohm Co Ltd | Discrete diode |
| JPH0832092A (en) * | 1995-05-25 | 1996-02-02 | Rohm Co Ltd | Discrete diode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6362110B2 (en) | 1988-12-01 |
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