KR100645069B1 - Electrostatic discharge protection device and mehtod of fabricating the same - Google Patents

Abstract

An electrostatic discharge protection device and a method of manufacturing the same are provided. The device includes a substrate, an n well formed on the substrate, and a p well formed on the n well. An NMOS transistor comprising a gate electrode, n + source and n + drain is formed in the p well, and a grounded p + well pick-up is formed in the p well. The n well is connected to the n + drain of the NMOS transistor and the n + source is grounded. By connecting n + drain and nwell, the trigger voltage can be lowered and the surface current density can be lowered.

Description

Electrostatic discharge protection device and its manufacturing method {ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND MEHTOD OF FABRICATING THE SAME}

1 is a view for explaining an electrostatic discharge protection circuit using a ggNMOS transistor.

2 is a graph showing voltage-current characteristics of an ggNMOS transistor during electrostatic discharge.

3 is a view showing a semiconductor device for electrostatic discharge protection described in the paper of Ming-Dou Ker et al.

4A is a cross-sectional view illustrating an electrostatic discharge protection device according to a first embodiment of the present invention.

5B is an equivalent circuit diagram of an electrostatic discharge protection device according to a second embodiment of the present invention.

6 to 8 are process cross-sectional views illustrating a method of manufacturing an electrostatic discharge protection device according to a first embodiment of the present invention, respectively.

9 to 11 are cross-sectional views illustrating a method of manufacturing an electrostatic discharge protection device according to a second embodiment of the present invention, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an electrostatic discharge protection device and a method for manufacturing the same.

Integrated circuits (ICs) composed of MOSFETs are very vulnerable to damage by electrostatic discharge (ESD). Electrostatic discharges may be delivered at the input / output (I / O), power pins, or pads of other integrated circuits, which may cause damage to the junctions, dielectrics, and unit devices of the transistors.

Various electrostatic discharge protection schemes have been developed to protect devices from electrostatic discharge. The main purpose of electrostatic discharge protection is to direct current from electrostatic discharge from a susceptible circuit section to a low-impedance path.

The ESD protection circuit is connected in parallel between the I / O and power pins and the internal circuit to provide a current path at a low voltage during electrostatic discharge to induce electrostatic discharge current to the outside. Representative electrostatic discharge protection circuits can be divided into silicon controlled rectifiers (SCRs) and npn bipolar transistors. The silicon controlled rectifier is a structure that discharges the electrostatic discharge current instantaneously to the Vss node by the parasitic npnp bipolar transistor. The npn bipolar transistor is a structure that discharges the electrostatic discharge current to the Vss node by the operation of the parasitic npn bipolar transistor of the MOS transistor against the snap-back phenomenon. For the npn bipolar transistor structure, the electrostatic discharge protection circuit uses a gated gated NMOS (ggNMOS) transistor.

1 is a view for explaining an electrostatic discharge protection circuit using a ggNMOS transistor.

2 is a graph showing voltage-current characteristics of an ggNMOS transistor during electrostatic discharge.

Referring to FIG. 1, an electrostatic discharge protection circuit 5 is connected in parallel between the pad 1 and the internal circuit 3. The drain of the ggNMOS transistor is electrically connected to the pad 1, and the gate, source and channel of the transistor are connected to the ground node Vss node.

Referring to FIG. 2, when a voltage greater than a trigger voltage (Vt) is applied to the ggNMOS transistor by electrostatic discharge, part of the charge flows to the substrate by breakdown of the drain junction of the ggNMOS transistor, and the parasitic npn caused by the charge By turning on the transistor, a large amount of electrostatic discharge current is instantaneously discharged to the Vss node through a low-impedance path, thereby protecting the internal circuit 3 from damage.

Increasing substrate surface current density, hot-carrier issue, and joule heating during electrostatic discharge result in lower ESD robustness. In order to solve this problem, a structure is used to form silicide blocking between the gate and the source / drain contacts of the ggNMOS using silicide blocking. However, this structure requires an area for separating the silicide to which the source / drain contacts are connected from the gate, which increases the area of the electrostatic discharge circuit. "Novel ESD Implantation for Sub-Quarter-Micron CMOS Technology with Enhanced Machine-Model ESD Robustness," published in IEEE 2002, is a method of electrostatic discharge protection that wraps n + drain into an n-diffusion layer without increasing the layout area. It introduces.

3 is a diagram illustrating a semiconductor device for electrostatic discharge protection introduced in a paper by Ming-Dou Ker et al.

Referring to FIG. 3, the device is formed in a p-well formed in the substrate 10 and includes NMOS transistors T1 and T2 that share n + drain 20 and are connected in series. The source 16 of each NMOS transistor is connected to the Vss node with a p + guard ring 18. The n + drain is electrically connected to the pad 24. The device includes an n-diffusion layer 22 surrounding the n + drain 20 to overcome surface current density increases and hot carrier issues. The n-diffusion layer 22 has a spacing under the n + drain 20.

The space has a relatively low break down voltage. Therefore, when the n + drain 20 is applied to the electrostatic discharge voltage, a substrate current is generated through the space and discharged to the Vss node through the parasitic npn bipolar transistors Q1 and Q2 in the NMOS transistor. This structure improves ESD robustness because it has a current path that is far from the surface of the relatively weak substrate and the channel of the transistor. However, there is a problem that a complicated process is required because an additional layer for forming the n-diffusion layer 22 having a space under the n + drain 20 is required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an electrostatic discharge protection device having excellent electrostatic discharge durability and a method of manufacturing the same.

Another object of the present invention is to provide an electrostatic discharge protection device and a method of manufacturing the same, which can improve durability without increasing the area of the electrostatic discharge circuit.

Another object of the present invention is to provide an electrostatic discharge protection device and a method of manufacturing the same, which can be manufactured by modifying an existing process without adding a complicated process.

In order to achieve the above technical problem, the present invention provides an electrostatic discharge protection device having an n + drain connected to an n well. The device includes a substrate, an n well formed on the substrate, and a p well formed on the n well. An NMOS transistor including a gate electrode, n + source and n + drain is formed in the p well, and a grounded p + well pick-up is formed in the p well. The n well is connected to the n + drain of the NMOS transistor and the n + source is grounded.

And a circuit terminal such as an input / output (I / O) or power pin of an integrated circuit (IC) and a ground terminal. An electrostatic discharge protection circuit is connected to the circuit terminal to prevent damage to the internal circuit from electrostatic discharge. The n + drain is connected to the circuit terminal and the n + source and the p + well pickup are connected to the ground terminal. The gate electrode may be connected to the ground terminal and grounded, or may be electrically connected to the n + drain.

The n well may extend vertically along the sidewalls of the p well to be connected to the n + drain. The n + drain may have a higher impurity concentration than the n + source due to the impurity concentration of the n well. The vertically extending n well borders the p well. The boundary between the n well and the p well may overlap the n + drain.

In an embodiment of the present invention, the electrostatic discharge protection device connected to the circuit terminal and the ground terminal includes a p well formed in a substrate and an NMOS transistor formed in the p well region. The NMOS transistor includes a gate electrode and n + source electrically connected to the ground terminal and n + drain electrically connected to the circuit terminal. P + well pickup is formed in the p well region. The p + well pickup is electrically connected to the ground terminal. An n well is formed below the p well, and the n well extends vertically and is connected to the drain of the NMOS transistor.

In another embodiment of the present invention, the electrostatic discharge protection device connected to the circuit terminal and the ground terminal includes a p well formed in a substrate and an NMOS transistor formed in the p well region. The NMOS transistor includes a gate electrode and n + drain electrically connected to the circuit terminal, and an n + source electrically connected to the ground terminal. P + well pickup is formed in the p well region. The p + well pickup is electrically connected to the ground terminal. An n well is formed below the p well. The n well extends vertically and is connected to the drain of the NMOS transistor. The circuit terminal and the n + drain may be connected by wiring. In this case, the gate electrode may be a portion in which the wiring is extended.

In order to achieve the above technical problem, the present invention provides a method of manufacturing an electrostatic discharge protection device having n + drain connected to n well. This method forms a p well above the substrate and an n well below the p well. The n well is formed to extend vertically to the substrate surface. As a result, a boundary between the p well region and the n well region is partitioned on the substrate surface. Impurities are implanted into the p well region to form n + sources and n + drains spaced apart from each other. In this case, the n + drain is formed to overlap the boundary between the p well region and the n well region. Impurities are implanted into the p well region to form p + well pickup. Wirings connected to the p + well pickup, the n + source and the n + drain are formed respectively. The wiring connects the p + well pickup and the n + source to a ground terminal and the n + drain connects to a circuit terminal.

In the present invention, an isolation layer may be formed on the substrate before forming the n well region and the p well region. The device isolation layer defines an active region including an n well region and a p well region in the substrate. The n + source, the p + well pickup and the n + drain are formed in the active region. The device isolation layer may be formed after forming the n well region and the p well region. Similarly, the device isolation layer defines an active region including n well regions and p well regions on the substrate, and the n + source, the p + well pickup, and the n + drain are formed in the active region.

The wiring connected to the n + drain may extend up to an area between the n + source and the n + drain. In this case, a channel portion of the field transistor may be defined between the n + drain and the n + source by forming a boundary portion of the wiring overlapping the n + source.

In an embodiment of the present invention, the n + drain and the n + source may be a source and a drain of a ground gate transistor. In the method of manufacturing the electrostatic discharge protection device, p wells are formed on a substrate and n wells are formed on a bottom of the p wells. The n wells are formed to extend vertically along the sidewalls of the fraud p wells to the surface of the substrate. As a result, a boundary between the p well region and the n well region is partitioned on the substrate surface. A gate electrode is formed on the p well region. Impurities are implanted into the substrates on both sides of the gate electrode to form n + sources and n + drains. The n + drain may be formed to overlap a boundary between the p well region and the n well region. Impurities are implanted into the p well region to form p + well pickup. Wirings connected to the p + well pickup, the gate electrode, the n + source, and the n + drain are respectively formed. The wiring connects the p + well pickup and the n + source to a ground terminal and the n + drain to a circuit terminal.

An isolation layer may be formed before or after forming the n well region and the p well region. The device isolation layer is formed on the substrate to define an active region. The active region is formed to include the n well region and the p well region. In this case, the gate electrode is formed to cross the upper portion of the p well region in the active region. The active region on one side of the gate electrode is a p well region and the active region on the other side is a p well region and an n well region. The device isolation layer may be formed after forming the n well region and the p well region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

4A is a cross-sectional view illustrating an electrostatic discharge protection device according to a first embodiment of the present invention.

Referring to FIG. 4A, the device includes an n well 25 formed in the substrate 50 and a p well 54 formed on the n well 25. The p well 54 extends to the surface of the substrate 50. The n well 52 has a portion extending vertically along the sidewall of the p well 54 to the surface of the substrate 50. An isolation layer 56 is formed on the substrate 50 to define an active region. The active region includes a region in which the p well 54 is formed (hereinafter referred to as a 'p well region') and an region in which an n well 54 is formed (hereinafter referred to as an 'n well region'). The gate electrode 58 is formed on the active region. The gate electrode 58 may cross the upper portion of the active region and extend to the upper portion of the device isolation layer 56. The gate electrode 58 bisects the active region. An active region on one side of the gate electrode 58 includes a p well region and an n well region, while an active region on the other side is a p well region. An n + source 64 and an n + drain 62 in which impurities are diffused in the active regions on both sides of the gate electrode 58 are formed. The gate electrode 58, the n + source 64 and the n + drain 62 constitute an NMOS transistor. The n + source 64 is formed in the p well 54, and the n + drain 62 is formed overlapping the p well 54 and the n well 52. Generally, the source and the drain of an NMOS transistor are formed in a p well or a p-substrate, but the drain of an NMOS transistor of an electrostatic discharge protection device according to the present invention overlaps the p well and n well and is connected to the n well. Has The n + drain 62 may have a higher impurity concentration than the n + source 64 due to the n well 52.

A p + well pick-up 66 in which impurities are implanted is formed in the p well region 54. The p + well pickup 66 may be spaced apart from the NMOS transistor by the device isolation layer 56. The n + drain 62 is connected to a circuit terminal 60 of an integrated circuit, and the n + source 64 and the p + well pickup 66 are connected to a ground terminal. The circuit terminal 60 may be an input / output (I / O) pin, a data pin, or a power pin, and may be electrically connected to an internal circuit. The gate electrode 58 serves to space the n + source 64 and the n + drain 62 to form a base of the parasitic npn bipolar transistor, but the gate electrode 58 is connected to a ground terminal to discharge an electrostatic discharge. An abnormal operation of the NMOS transistor may be prevented by the voltage drop of the p well 54 due to the current.

Although typically a single gate electrode is shown, the NMOS transistor may employ a gate electrode of a finger structure to discharge a large amount of current. Even in this case, the n well extends vertically and is connected to n + drain. In addition, the p + well pickup 66 may be formed in the p well 54 in the form of a guard ring that surrounds the outer portion of the electrostatic discharge protection circuit.

4B is an equivalent circuit diagram illustrating an electrostatic discharge protection device according to a first embodiment of the present invention.

This electrostatic discharge protection element is operated by a parallel circuit of parasitic npn bipolar transistors in the NMOS transistor. The n + source 64, the n + drain 62 and the p well 54 correspond to the emitter, collector and base of the first npn bipolar transistor Q11, respectively. In addition, the n + source 64, the n well 52, and the p well 54 correspond to the emitter, collector, and base of the second npn bipolar transistor Q12, respectively.

When the electrostatic discharge voltage is applied to the n + drain 62 so that the junction between the n + drain 62 and the n well 52 and the p well 54 breaks down, the first and The second npn bipolar transistors Q11 and Q12 are respectively triggered. The first and second npn bipolar transistors Q11 and Q12 operate by the voltage drop caused by the parasitic resistors R1 and R2 of the p well 54 so that an electrostatic discharge current is instantaneously discharged through the ground terminal. do. The electrostatic discharge protection element is formed of the n + source 64, the n + source 64, the n + drain 62 and the p well 52 as well as the horizontal npn bipolar transistor Q11. An electrostatic discharge current is discharged by the operation of a vertical npn bipolar transistor (Q12) composed of the n well 52 and the p well 54. Therefore, the discharging current can be dispersed to lower the substrate surface current, and generation of joule heat on the substrate surface can be suppressed. In addition, due to impurities in the n well 52, the n + drain 62 may have a higher impurity concentration than in the prior art. This may lower the junction breakdown voltage between the n + drain 62 and the p well 54 to provide a low trigger voltage for the bipolar transistor. At this time, the impurity concentration of the n + drain 62 is higher at the portion connected to the n well 52 at the edge portion of the p well 54 spaced from the surface of the substrate. Thus, this portion may first break down to further lower the surface current density of the region adjacent to the gate.

5A is a cross-sectional view illustrating an electrostatic discharge protection device according to a second embodiment of the present invention.

Referring to FIG. 5A, similar to the first embodiment, the device includes an NMOS transistor having an n + drain 62 connected to an n well 52. N wells 52 and p wells 54 are formed in the substrate 50. The p well 54 extends to the surface of the substrate 50. The n well 52 has a portion extending vertically along the sidewall of the p well 54 to the surface of the substrate 50. An isolation layer 56 is formed on the substrate 50 to define an active region. The active region includes a p well region and an n well region. The gate electrode 58 is formed on the active region. The gate electrode 58 may cross the upper portion of the active region and extend to the upper portion of the device isolation layer 56. The gate electrode 58 bisects the active region. An active region on one side of the gate electrode 58 includes a p well region and an n well region, whereas an active region on the other side includes only the p well region. An n + source 64 and an n + drain 62 in which impurities are diffused in the active regions on both sides of the gate electrode 58 are formed. The gate electrode 58, the n + source 64 and the n + drain 62 constitute an NMOS transistor. A thick insulating film is interposed between the gate electrode 58 and the active region. The n + source 64 is formed in the p well 54, and the n + drain 62 is formed overlapping the p well 54 and the n well 52. Thus, the drain of the NMOS transistor of this electrostatic discharge protection element has a drain connected to the n well and overlapping the p well and the n well. The n + drain 62 may have a higher impurity concentration than the n + source 64 due to the n well 52.

A p + well pick-up 66 in which impurities are implanted is formed in the p well region 54. The p + well pickup 66 may be spaced apart from the NMOS transistor by the device isolation layer 56. The n + drain 62 is connected to a circuit terminal 60 of an integrated circuit, and the n + source 64 and the p + well pickup 66 are connected to a ground terminal. In the second embodiment the gate electrode 58 is connected to the circuit terminal 60 together with the n + drain 62. In order to maintain the NMOS transistor of the electrostatic discharge protection device in the steady state, it is preferable that the NMOS transistor has a high threshold voltage. Therefore, a thick insulating film is interposed between the gate electrode 58 and the active region. The gate electrode 58 may be an extended portion of a wiring connected to the n + drain 62. In this case, the interlayer insulating film between the wiring and the substrate may correspond to the gate insulating film.

Although a single gate electrode is typically shown in the second embodiment, the NMOS transistor may employ a finger structure gate electrode to discharge a large amount of current. Even in this case, the n well extends vertically and is connected to n + drain. In addition, the p + well pickup 66 may be formed in the p well 54 in the form of a guard ring that surrounds the outer portion of the electrostatic discharge protection circuit.

5B is an equivalent circuit diagram of an electrostatic discharge protection device according to a second embodiment of the present invention.

Referring to FIG. 5B, the electrostatic discharge protection device is operated by an NMOS transistor T11 and parasitic npn bipolar transistors Q21 and Q22 in the NMOS transistor T11. The n + source 64, the n + drain 62 and the p well 54 correspond to the emitter, collector and base of the first npn bipolar transistor Q21, respectively. In addition, the n + source 64, the n well 52, and the p well 54 correspond to the emitter, collector, and base of the second npn bipolar transistor Q22, respectively.

When the electrostatic discharge voltage is applied to the n + drain 62 so that the junction between the n + drain 62 and the n well 52 and the p well 54 breaks down, the first and Second npn bipolar transistors Q21 and Q22 are triggered, respectively. The first and second npn bipolar transistors Q21 and Q22 operate by the voltage drop caused by the parasitic resistors R21 and R22 of the p well 54 so that an electrostatic discharge current is instantaneously discharged through the ground terminal. . The electrostatic discharge protection device includes a horizontal npn bipolar transistor Q21 composed of the n + source 64, the n + drain 62, and the p well 54, the n + source 64, and the n The operation of the vertical npn bipolar transistor Q22 as well as the NMOS transistor T11 composed of the well 52 and the p well 54 discharges an electrostatic discharge current. That is, a junction break down voltage between the n + drain 62 and the p well 54 and between the n well 52 and the p well 54 and the NMOS transistor T11. Triggered at the lower voltage of the threshold voltage of the electrostatic discharge current is instantaneously discharged through the ground terminal.

6 to 8 are process cross-sectional views illustrating a method of manufacturing an electrostatic discharge protection device according to a first embodiment of the present invention, respectively.

Referring to FIG. 6, impurities are implanted into the substrate 100 to form a deep nwell 102. Impurities are implanted into the substrate to form a vertical nwell 104. The deep n well 102 is spaced a predetermined distance from the surface of the substrate, and the vertical n well 104 is connected to the deep n well 102 and extends vertically to the surface of the substrate 100. CMOS integrated circuits have various well structures. For example, an integrated circuit includes a p well in which an NMOS transistor is formed, an n well in which a PMOS transistor is formed, and a pocket p well for well biasing and isolation of a well. Thus, the deep n well 102 and the vertical n well 104 can be formed without the addition of a process by changing the existing layout.

The p well 106 is formed by implanting impurities into the substrate on the deep n well 102. An isolation layer 108 is formed on the substrate on which the wells are formed to define the first active region 110a and the second active region 110b. The device isolation layer 108 may be formed first before forming the wells. The first active region 110a is a region where an NMOS transistor of an electrostatic discharge protection device is formed, and the second active region 110b is a region for forming the well pickup. When the well pickup is formed in the first active region 110a, the second active region 110b may not be formed. The surface of the first active region 110a may include a p well region in which the p well 106 is formed, and an n well region in which the vertical n well 104 is formed.

Referring to FIG. 7, a gate electrode 112 is formed on the first active region 110a. A gate insulating layer is disposed between the gate electrode 112 and the first active region 110a. A portion of the gate electrode 112 extends across the first active region 110a to an upper portion of the device isolation layer 108. The gate electrode 112 bisects the first active region 110a. The first active region 110a on one side of the gate electrode 112 is the p well region, and the other side includes the p well region and the n well region. Impurities are implanted into the first active region 110a to form n + sources 116 and n + drain 114 on both sides of the gate electrode 112, respectively. The n + source 116 is formed in the p well region, and the n + drain 114 is formed overlapping the p well region and the n well region. Thus, the n + drain 114 is connected to the vertical n well 104. Impurities are implanted into the p well region to form a p + well pickup 118. The p + well pickup 118 is formed in the second active region 110b. If the second active region 110b is not formed in the device, the p + well pickup 118 may be formed in the first active region 110a. The p + well pickup 118 may be formed in the form of a guard ring surrounding the electrostatic discharge protection device. By adopting a guard ring structure, the effect of preventing the electrostatic discharge current flowing through the p-well 106 from being concentrated in one direction and increasing the current density can be expected.

The p + well pickup 118, the n + source 116, and the n + drain 114 may be formed when forming a diffusion layer of an internal circuit. Therefore, the forming order can be changed according to the forming order of the internal circuit.

Referring to FIG. 8, an interlayer insulating film 124 is formed on the entire surface of the substrate. The interlayer insulating layer 124 is patterned to form contact holes exposing the p + well pickup 118, the n + source 116, the n + drain 114, and the gate electrode 112, respectively. The contact hole exposing the gate electrode 112 is preferably located above the device isolation layer 108. That is, a contact hole may be formed in a portion of the gate electrode that extends over the device isolation layer. Wiring is formed on the interlayer insulating film 124. The wire extends through the contact hole and extends through the contact hole and the first wire 126 connected to the p + well pickup 118 and the n + source 116 and connected to the n + drain 114. The second wiring 128 is included. The first wiring 126 may extend through the contact hole and be connected to the gate electrode 112. In the drawing, the first wiring 126 and the second wiring 128 are shown as a single layer, but the first wiring 126 and the second wiring 128 may be formed in a multilayer wiring structure, respectively. That is, local interconnections may be formed on the interlayer insulating layer 124 and another interlayer insulating layer may be further formed on the local interconnection to form global interconnections that connect the local interconnections. The local wiring and the wide wiring may be formed by applying a general multiple interconnections technology.

Prior to forming the interlayer insulating layer 124, a silicide layer 122 may be further formed on surfaces of the n + source 116, the n + drain 114, and the p + well pickup 118. A silicide layer may also be formed on the top surface of the gate electrode 112. The silicide layer 122 may be formed by applying a conventional self aligned silicidation process. In order to prevent a short between the gate electrode 112 and the silicide layer 122, a spacer pattern 120 may be formed on sidewalls of the gate electrode 112 before the silicide layer 122 is formed. The spacer pattern 120 may have a purpose of forming a ballast resistor between the silicide layer and the junction, in addition to the purpose of short-circuit prevention of the silicide layer 122 and the gate electrode 112. Even without forming the silicide layer, the spacer pattern 120 may be formed in an integrated circuit device for the purpose of junction engineering of an internal circuit.

Although not shown, the first wire 126 is connected to the ground terminal, and the second wire 128 is connected to the circuit terminal.

9 to 11 are cross-sectional views illustrating a method of manufacturing an electrostatic discharge protection device according to a second embodiment of the present invention, respectively.

Referring to FIG. 9, impurities are implanted into the substrate 200 to form a deep n well 202. Impurities are implanted into the substrate to form a vertical n well 204. The deep n well 202 is spaced a predetermined distance from the surface of the substrate, and the vertical n well 204 is connected to the deep n well 202 and extends vertically to the surface of the substrate 200. The deep n well 202 and the vertical n well 204 can be formed without the addition of a process by changing the existing layout.

The p well 206 is formed by implanting impurities into the substrate on the deep n well 202. An isolation layer 208 is formed on the substrate on which the wells are formed to define a first active region 210a and a second active region 210b. The device isolation layer 208 may be formed first before forming the wells. The second active region 210b is a region for forming the well pickup. When the well pickup is formed in the first active region 210a, the second active region 201b may not be formed. The surface of the first active region 210a may include a p well region in which the p well 206 is formed, and an n well region in which the vertical n well 204 is formed.

A dummy gate pattern 212 is formed on the first active region 210a. A portion of the dummy gate pattern 212 extends across the first active region 210a to an upper portion of the device isolation layer 208. The first active region 210a on one side of the dummy gate pattern 212 is the p well region, and the other side includes the p well region and the n well region. Impurities are implanted into the first active region 210a to form n + sources 216 and n + drains 214 on both sides of the dummy gate pattern 212, respectively. The n + source 216 is formed in the p well region, and the n + drain 214 is formed overlapping the p well region and the n well region. Thus, the n + drain 214 is connected to the vertical n well 204. Impurities are implanted into the p well region to form a p + well pickup 218. The p + well pickup 218 is formed in the second active region 210b. If the second active region 210b is not formed in the device, the p + well pickup 218 may be formed in the first active region 210a. The p + well pickup 218 may be formed in the form of a guard ring surrounding the electrostatic discharge protection device. By adopting the guard ring structure, the effect of preventing the electrostatic discharge current flowing through the p well 206 from being concentrated in one direction and increasing the current density can be expected.

The p + well pickup 218, the n + source 216, and the n + drain 214 may be formed when an impurity diffusion layer of an internal circuit is formed. Therefore, the forming order can be changed according to the forming order of the internal circuit.

Referring to FIG. 10, an interlayer insulating film 224 is formed on the entire surface of the substrate. The interlayer insulating layer 224 is patterned to form contact holes 225 exposing the p + well pickup 218, the n + source 216, and the n + drain 214, respectively. The dummy gate pattern 212 may be removed before the interlayer insulating layer 224 is formed. However, when the dummy gate pattern 212 is an insulating layer, the interlayer insulating layer 224 is formed on the dummy gate pattern 212. It may be flattened.

Before forming the interlayer insulating layer 224, a silicide layer 222 may be further formed on the n + source 216, the n + drain 214, and the p + well pickup 218. In this case, the silicide layer is not formed in the region between the n + source 216 and the n + drain 214 by the dummy gate pattern 212. Therefore, the dummy gate pattern 212 is preferably removed after the silicide layer 222 is formed.

Referring to FIG. 11, a wire is formed on the interlayer insulating film 224. The wire extends through the contact hole 225 and extends through the contact hole and the first wire 226 connected to the p + well pickup 218 and the n + source 216 and the n + drain 214. And a second wiring 228 connected to it. The second wiring 228 may extend to an upper region between the n + source 216 and the n + drain 214. In this case, one sidewall of the second interconnection 228 preferably overlaps the upper portion of the n + source 216. When a voltage of a predetermined level or more is applied to the second wiring 228, a channel may be formed in an active region between the n + source 216 and the n + drain 214. That is, the extended portion G of the second wiring, the n + source 216 and the n + drain 214 may constitute a MOS transistor. In this case, the interlayer insulating film between the stretched portion G and the first active region 210a may correspond to the gate insulating layer of the MOS transistor. Although the first wiring 216 and the second wiring 218 are illustrated as a single layer in the drawing, the first wiring 216 and the second wiring 218 may be formed in a multilayer wiring structure, respectively. That is, local interconnections may be formed on the interlayer insulating layer 224 and another interlayer insulating layer may be further formed on the local interconnection to form global interconnections that connect the local interconnections. The local wiring and the wide wiring may be formed by applying a general multiple interconnections technology.

Although not shown, the first wire 216 is connected to the ground terminal, and the second wire 218 is connected to the circuit terminal. When the electrostatic discharge voltage is applied to the second wiring, the electrostatic discharge protection device operates. When the electrostatic discharge voltage is above a predetermined level, the n + source 216 is extended by the extended portion G of the second wiring. And a channel is formed between the n + drain 214 so that the electrostatic discharge current may be discharged to the ground terminal through the n + source 216.

As described above, according to the present invention, since the electrostatic discharge current is discharged through the ground terminal by the operation of the horizontal npn bipolar transistor as well as the vertical npn bipolar transistor, the current density of the vulnerable substrate surface can be lowered, and it is separated from the substrate surface. Since the electric current is discharged along the bulk path of the substrate, generation of joule heat on the surface of the substrate can be suppressed. Further, by connecting the n well and the n + drain, the impurity concentration of the n + drain due to the n well impurities can be increased, so that the trigger voltage can be lowered. Lower trigger voltages provide fast electrostatic discharge and reduce stress on electrostatic discharge protection devices.

Furthermore, the n well connected to the drain can be formed together with the well structure formation of the internal circuit by changing only the existing layout. Therefore, since an additional process is not necessary, the existing process can be applied as it is. In addition, the present invention can improve the durability without increasing the area of the electrostatic discharge protection element because the well structure is changed without increasing the lateral dimensions.

Claims (12)

Board; An n well formed on the substrate; A p well formed on said n well; An NMOS transistor formed in the p well and including a gate electrode, n + source and n + drain; And A p + well pick-up formed in the p well and grounded; And the n + drain of the NMOS transistor is connected to the n well and connected to a circuit terminal, and the n + source is grounded. The method of claim 1, And the gate electrode is grounded. The method of claim 1, And the gate electrode is connected to the n + drain. The method of claim 1, The n + drain has a higher impurity concentration than the n + source. The method of claim 1, And the n well extends vertically below the n + drain and is connected to the n + drain. The method of claim 1, And the n well extends vertically to form a boundary with the p well, wherein a boundary between the n well and the p well overlaps the n + drain. In the electrostatic discharge protection element connected to the circuit terminal and the ground terminal, P wells formed in the substrate; An NMOS transistor formed in the p well region and including a gate electrode and n + source connected to the ground terminal and n + drain connected to the circuit terminal; A p + well pickup formed in said p well region and connected to said ground terminal; and And an n well formed under the p well and vertically extended to be connected to a drain of the NMOS transistor. The method of claim 7, wherein Further comprising a wire connected to the ground terminal, And the n + source, the gate electrode and the p + well pickup are connected in parallel to the wiring. The method of claim 7, wherein Wherein the n + drain has a higher impurity concentration than the n + source. In manufacturing an electrostatic discharge protection device connected to the circuit terminal and the ground terminal, A p well is formed on the substrate and an n well is formed below the p well, and the n well extends vertically along the sidewall of the p well so that a boundary between the p well region and the n well region is partitioned on the surface of the substrate. Forming; Implanting impurities into the p well region to form n + sources and n + drains spaced apart from each other, wherein the n + drain is formed to overlap a boundary between the p well region and the n well region; Implanting impurities into the p well region to form a p + well pickup; and Forming a wire connected to said p + well pickup, said n + source and said n + drain, respectively, wherein said p + well pickup and said n + source are connected to a ground terminal and said n + drain is connected to a circuit terminal; Method of manufacturing a discharge protection device. The method of claim 10, Before forming the n well region and the p well region, Forming an isolation layer on the substrate to define an active region; The active region includes the n well region and the p well region, wherein the n + source, the p + well pickup and the n + drain are formed in the active region. The method of claim 10, After forming the n well region and the p well region, Forming an isolation layer on the substrate to define an active region; The active region includes the n well region and the p well region, wherein the n + source, the p + source region and the n + drain are formed in the active region.

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