JPH0590522A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an MOS IC due to static electricity and high voltage, by connecting the I/O terminal for signal of an MOS IC with a protective element for preventing breakdown by using polycrystalline silicon, and setting the ratio of the length of the polycrystalline silicon in the signal propagation direction to the width in the direction perpendicular to the polycrystalline silicon length to be equal to 6 or smaller. CONSTITUTION:A bonding pad 1 is formed on a semiconductor substrate, and connected with polycrystalline silicon 105 by using an aluminum wiring 104. The ratio L/W is set to be equal to 6 or smaller where L and W are the length and the width, respectively, of the polycrystalline silicon 105 turning to the resistor of an input protecting circuit. The width of the polycrystalline silicon 105 is made smaller than the width of an input terminal 1. Thereby a field oxide film is prevented from being broken down by an excessive input voltage, while evading the latchup phenomenon. By making the width of the polycrystalline silicon 105 turning to the resistor smaller than the width of the bonding pad 1 turning to an input terminal, the amount of a current to be inputted to the polycrystalline silicon is controlled, and the insulating film is protected from an excessive voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly a MOS.
Type field effect transistor integrated device (hereinafter abbreviated as MOSIC).

[0002]

2. Description of the Related Art Since the destruction phenomenon due to excessive surge such as static electricity of MOSIC has been a problem from the beginning of its development,
So far, various measures have been proposed and improvements have been made.

A typical destruction protection circuit at an input / output terminal of a conventional complementary insulated gate semiconductor integrated device (hereinafter abbreviated as C-MOSIC) is, as shown in FIG. 2. After the potential is applied to the clamp protection diode 3, the circuit is transmitted to the input gate 4 of the C-MOSIC, and the protection resistor 2 is provided in the N-type semiconductor 101 as shown in FIG. It was provided. Is formed by a conductivity type different from that of the semiconductor substrate 101, that is, a P-type diffusion layer 102,
As shown in FIG. 2B, an insulating oxide film (hereinafter referred to as a field oxide film) 103 other than the gate oxide film 103 is formed on the surface of the semiconductor substrate 101, and then the field oxide film 10 is formed.
The protection resistor 2 is obtained by providing the polycrystalline silicon layer 105 on the surface of the protection resistor 2.

[0004]

However, when the integration density of MOSIC is further increased as in the present situation, it is possible to use the conventional measures as they are in the MOSIC as described above, because electrostatic breakdown of the field oxide film of the MOS field effect transistor,
Turn-on phenomenon of the parasitic thyristor that is inevitably present in the MOSIC (hereinafter referred to as the latch-up phenomenon)
Will result in.

That is, although the breakdown resistance against static electricity has been improved by such a structure, as described above, M
When the OSIC is highly integrated, the formation of the protection resistor 2 by the P-type diffusion layer 102 has a drawback that the latch-up phenomenon peculiar to the C-MOSIC is easily caused.
By the way, this latch-up phenomenon occurs in a conventional semiconductor device, for example, in a structure in which a high-concentration diffusion layer is provided in a semiconductor substrate as shown in the specification of Japanese Patent Publication No. 55-29139, the potential gradient of the semiconductor substrate. It is possible to reduce the parasitic thyristor characteristics and prevent them from occurring by eliminating the above and changing the layout on the mask of the MOS field effect transistor.
In C, it is desirable to use a polycrystalline silicon layer 105 as a protective resistance instead of the P + diffusion layer 102. However, if a protective resistance having a high resistance value due to the polycrystalline silicon layer, that is, having a large value of polycrystalline silicon length L / polycrystalline silicon width W is provided, the bonding pad 1
Excessive voltage due to static electricity applied to the protection diode 2
Therefore, it takes a long time to be neutralized, and the field oxide film 103 is destroyed.

Therefore, the present invention solves such a problem, and an object thereof is to provide a length L and a width W of a polycrystalline silicon layer for connecting an input / output terminal of a MOSIC and a protection element for destruction prevention. It is an improved ratio of. That is,
The signal input / output terminal of the MOSIC and the destruction prevention protection element are electrically connected using polycrystalline silicon, and the length L of the polycrystalline silicon in the signal propagation direction is orthogonal to the length of the polycrystalline silicon. The ratio of the width W in the direction, L / W, is set to 6 or less on the mask, and the
It is to improve the tolerance of the SIC to destruction.

[0007]

The semiconductor device of the present invention comprises:
In a semiconductor device having a MOS field effect transistor, a ratio of a width orthogonal to an electric signal propagating direction to an input terminal provided on a semiconductor substrate and a length along the electric signal propagating direction is 6 or less on a mask. A resistor, a first conductive wire electrically connecting the input terminal and the resistor, a second conductive wire electrically connecting the resistor and the destruction prevention element, and the destruction prevention element It is characterized in that it has a third conductive wiring that is electrically connected to the input gate of the MOS field effect transistor and has a wiring width smaller than the wiring width of the first conductive wiring.

[0008]

EXAMPLE An example of the present invention will be described with reference to FIG.

According to the present invention, as shown in FIG. 3, the latch-up phenomenon is achieved by setting the ratio L / W of the length L and the width W of the polycrystalline silicon 105 connecting the bonding pad 1 and the clamp protection diode 3 to 6 or less. While avoiding the above, the drawback of destruction of the field oxide film due to excessive input voltage is eliminated. Compared with the conventional one in which the L / W is large, for example, when the L / W of polycrystalline silicon is 10, a voltage of 400 to 500 V is instantaneously applied between the input terminal and the semiconductor substrate. The aluminum wiring 104 for connection from the bonding pad 1 and the polycrystalline silicon 1
While the field oxide film was easily destroyed at the contact portion 107 with 05, the field oxide film was not destroyed at all under the same condition of L / W = 5, and the latch-up resistance L / W = It was at the same level as that of 10.

2 to 3, 106 is a field oxide film and 108 is a contact hole.

[0011]

As described above, according to the present invention, the MO
It has a sufficient effect for preventing the breakdown of the field oxide film due to a high voltage outside the rating and static electricity that are encountered when thinning the field oxide film in advancing the miniaturization of the SIC.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing destruction protection at an input terminal of a conventional C-MOS IC.

FIG. 2 is a cross-sectional view for explaining the structure of a conventional protection resistor.

FIG. 3 is a pattern diagram showing a destruction protection mechanism according to the present invention.

[Explanation of symbols]

 101 semiconductor substrate 103 field oxide film 105 polycrystalline silicon

[Procedure amendment]

[Submission date] April 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly a MOS.
And about the integrated device of the type field effect transistor (hereinafter abbreviated as MOSIC), even more particularly the structure of the input protection circuit
Of.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

That is, although the breakdown resistance against static electricity has been improved by such a structure, as described above, M
When the OSIC is highly integrated, the formation of the protection resistor 2 by the P-type diffusion layer 102 has a drawback that the latch-up phenomenon peculiar to the C-MOSIC is easily caused.
By the way, this latch-up phenomenon occurs in a conventional semiconductor device, for example, in a structure in which a high-concentration diffusion layer is provided in a semiconductor substrate as shown in the specification of Japanese Patent Publication No. 55-29139, the potential gradient of the semiconductor substrate. It is possible to reduce the parasitic thyristor characteristics and prevent them from occurring by eliminating the above and changing the layout on the mask of the MOS field effect transistor.
In C, it is desirable to use polycrystalline silicon 105 as a protective resistance instead of the P + diffusion layer 102. However, if a protective resistor having a high resistance value of the polycrystalline silicon 105, that is, a large value of the polycrystalline silicon length L / the polycrystalline silicon width W is provided, the bonding pad 1
Excessive voltage due to static electricity applied to the protection diode 2
Therefore, it takes a long time to be neutralized, and the field oxide film 103 is destroyed. Also, as the density increases, the input of MOSIC
There is a problem that the amount of current input to the gate also increases.
It

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

Therefore, the present invention solves such a problem, and an object of the present invention is to set the length L and the width W of the polycrystalline silicon layer connecting the input / output terminals of the MOSIC and the destruction preventing element. It is an improved ratio. That is, MO
The signal input / output terminal of the SIC and the destruction prevention protection element are electrically connected using polycrystalline silicon, and the length L of the polycrystalline silicon in the signal propagation direction is orthogonal to the length of the polycrystalline silicon. the ratio of width is W, the L / W in the 6 or less, static electricity and to improve tolerance to breaking MOSIC by more high voltage rating, also the input terminal and the polycrystalline silicon
Compared to the width of the conductor to be electrically connected,
Of the conductor that electrically connects the force gate and the destruction prevention element
By inputting a narrower width to the input to the MOSIC
The flow rate can be controlled to improve the input protection performance.
At the same time, it is possible to have a configuration that supports high density.
It

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

The semiconductor device of the present invention comprises:
In a semiconductor device having a MOS field effect transistor, a resistor having a ratio of a width orthogonal to an electrical signal propagation direction to an input terminal provided on a semiconductor substrate to a length along the electrical signal propagation direction is 6 or less. Body, a first conductive wiring for electrically connecting the input terminal and the resistor, a second conductive wiring for electrically connecting the resistor and a destruction prevention element, the destruction prevention element and the MOS type Electrically connecting to an input gate of the field effect transistor, and
It is characterized by having a third conductive wiring having a wiring width smaller than the wiring width of the conductive wiring.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

The present invention, as shown in FIG. 3, the semiconductor substrate 1
Bonding pad 1 is provided on 01, and this is an input terminal
And Aluminum wiring 104 allows polycrystalline silicon 105
And are connected adjacent to each other. This polycrystalline silicon 105 is a book
It becomes the resistor of the input protection circuit. The ratio L / W of the length L and the width W of the polycrystalline silicon 105 is set to 6 or less, and the input terminal
The width of the polycrystalline silicon 105 is made smaller than the width of 1. This
This avoids the latch-up phenomenon and eliminates the defect that the field oxide film is destroyed by an excessive input voltage. In addition, the bonding pad 1
The width of polycrystalline silicon 105, which is a resistor, is smaller than the width.
This reduces the amount of current input to the polycrystalline silicon.
Control on the bonding pad side, and excessive voltage of the insulating film
Can contribute to protection from. Furthermore, bondin
Even if the pad 1 becomes smaller, the resistor
It is possible to achieve high integration by reducing the width of
Wear. Furthermore, polycrystalline silicon 105 and clamp protection dio
And connect it to the terminal 3 with aluminum wiring so that they are adjacent to each other.
Aluminum wiring for the terminal connected to the input gate of MOSIC
Connect more. At this time, beside the clamp protection diode
An input gate is provided in contact with it. In addition, the bonding pattern
Of the aluminum wiring 104 connecting the pad 1 and the polycrystalline silicon
Compared to the width, the clamp protection diode and the MOS input gate
The width of the aluminum wiring that connects to the terminal that connects to the
Make it thin. That is, with the bonding pad 1
Width of aluminum wiring 104 connecting polycrystalline silicon 105
Clamp protection diode and MOSIC input
The width of the aluminum wiring that connects to the terminal that connects to the gate
If the thickness is thick, the static electricity applied to the bonding pad 1
Is the overvoltage caused by the clamp protection diode 3 at once?
May cause damage to the field oxide film.
You L / W = 6 or less on the mask as in this embodiment
Comparing a protection circuit using a polycrystal silicon 105 with a conventional one having a large L / W, for example,
When the L / W of the polycrystalline silicon is set to 10, only a voltage of 400 to 500 V is instantaneously applied between the input terminal and the semiconductor substrate, and the aluminum wiring 104 for connection from the bonding pad 1 and the polycrystalline silicon 105 are formed. While the field oxide film was easily destroyed at the contact portion 107 with, under the same condition of L / W = 5, the field oxide film was not destroyed at all, and the latch-up resistance was L / W.
It was at the same level as that of W = 10.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

As described above, according to the present invention, there are
The ratio L / W of the length L and the width W of the crystalline silicon 105 is set to 6 or less.
Then, the input terminal and the polycrystalline silicon 105 are electrically connected to each other.
Input gate of MOSIC compared to the width of the connecting conductor
The width of the conductor that electrically connects the
The thinness has a sufficient effect for preventing the breakdown of the field oxide film due to high voltage outside the rating and static electricity which are encountered when thinning the field oxide film in advancing the miniaturization of MOSIC. In addition, with high integration,
Input to MOSIC with small electrical resistance and weak electrical resistance
It becomes possible to limit the amount of electric current
It has the effect of achieving high reliability and high reliability.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (1)

[Claims] 1. A semiconductor device having a MOS field effect transistor, wherein a ratio of a width of an input terminal provided on a semiconductor substrate and a width orthogonal to the electrical signal propagation direction to a length along the electrical signal propagation direction is: A resistor having 6 or less on the mask, a first conductive wire electrically connecting the input terminal and the resistor, a second conductive wire electrically connecting the resistor and the destruction prevention element, A breakdown preventing element and an input gate of the MOS field effect transistor are electrically connected, and a third conductive wiring having a wiring width smaller than a wiring width of the first conductive wiring is provided. Semiconductor device.