JPS59218764A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the breakdown resistance of an input protecting circuit against an overvoltage in an IC having an input protecting circuit by enhancing an P-N junction withstand voltage between a resistor near the connection unit of wirings extending from an external terminal, to which an unexpected overvoltage is applied to a resistor, and semiconductor substrate. CONSTITUTION:An IC is formed of a P<-> type semiconductor substrate 4 formed of silicon single crystal and having an impurity density, for example, of 1X10<15> (atoms/cm<3>), an N<-> type semiconductor region 32 is a connection unit of an external terminal 9 and a resistor 10, connected to the resistor 10, and provided on a main surface of a semiconductor substrate 4 to cover it. The impurity density of this N<-> type semiconductor region is low in the degree, for example, of 1X10<16> (atoms/cm<3>). Since the elongation of a depletion layer formed of a P-N junction of the region 32 and the substrate 4 is larger than that of the depletion layer formed of a P-N junction of the resistor 10 and the substrate 4, the breakdown resistance of the resistor 10 against the overvoltage for causing an electrostatic breakdown is improved in the connection unit of the terminal 9 to the resistor 10.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to a semiconductor integrated circuit device (
(hereinafter referred to as 10). [Background Art] Insulated gate field effect transistors (hereinafter referred to as ios used as the main constituent elements of M-paths) constitute the input stage circuit of the integrated circuit due to unexpected overvoltages caused by their artificial handling. In order to prevent breakdown of the gate insulating film of the MISFET (hereinafter referred to as electrostatic breakdown), a human power protection circuit is provided between the external terminal to which an unexpectedly excessive voltage is applied and the human power stage circuit. This human power protection circuit includes a resistance element to dampen unexpected overvoltage from an external terminal, and a surface breakdown or Zener breakdown that occurs when unexpected overvoltage occurs at the pn junction between the drain region and the semiconductor substrate. It is common to use a clamp MISF"ET which is clamped by the IC in series. For example, when a PM semiconductor substrate with a low impurity concentration is used as the semiconductor substrate constituting the IC To obtain a parasitically generated diode, to deal with the manufacturing process constraints of 0, and to prevent delays in operation time of 10, etc., an n+ type with a high impurity concentration is used as the resistive element. The present inventors have conducted electrostatic breakdown tests and studies on OVC equipped with an input protection circuit using an n+ type diffused layer resistor. , miniaturization of IC.

[I discovered that the input protection circuit itself does not have sufficient strength against unexpected overvoltage (1).And this is due to the fact that the input protection circuit itself does not have sufficient strength against unexpected overvoltage. Elucidation that this is based on the fact that the pn junction between the diffused layer resistor and the semiconductor substrate near the connection between the extending wiring and the diffused layer resistor is destroyed by thermal energy due to an unexpected overvoltage. As described above, with conventional IO, it was not possible to increase the voltage at which IO would break down due to an unexpected overvoltage, and increase the strength against excessive voltage. [Objective of the Invention] The object of the present invention is to improve the strength against unexpected excessive voltages that may cause electrostatic damage.
Our goal is to provide the following. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Summary of the Invention] A typical outline of the invention disclosed in this application is as follows. That is, in one IC that includes an input protection circuit including a resistor made of a semiconductor region in a semiconductor substrate, at least the electrical connection between the resistor and a wiring extending from an external terminal to which an unexpectedly excessive voltage is applied is provided. By improving the breakdown voltage of the pn junction between the resistor and the semiconductor substrate in the vicinity of the external connection, the breakdown strength (withstand voltage) of the input protection circuit against unexpected overvoltage is improved. The present invention will be described in detail below along with examples. In this embodiment, a complementary insulated gate field effect transistor [hereinafter referred to as OMIS (Oomple e-mentaly)] is constructed by MISFETs of different channels.
10, which uses an integrated circuit (MISFET) as a main component of an integrated circuit. Deaths that have the same function in all figures are given the same number, and repeated explanations will be omitted. [Example 1] FIG. 1 shows an IC for explaining [Example I] of the present invention.
1 is an equivalent circuit diagram showing an outline of an input protection circuit. In the IC shown in FIG. 1, reference numeral 1 denotes an external terminal, which is used to print operating signals of the integrated circuit inside the IC from the outside. When 1 (3) is handled by humans, an unexpected excessive voltage that may cause electrostatic damage is applied to this external terminal 1. This is the first manually operated input stage circuit in the annual bond circuit.This input stage circuit 2 constitutes an inverter circuit by p-channel MisFE'l'Q, , and n-channel M, ISF'ETQ2. .VCc is the operating voltage of the IC, GND is the ground potential, and OUT is the output terminal of the inverter circuit. S is the source region, D is the drain region, and G is the gate electrode. 3 is the external terminal 1 and the input stage circuit. This is an input protection circuit according to [Embodiment I] of the present invention provided between the input stage circuit 2 and the input stage circuit 2, and prevents electrostatic damage to the input stage circuit 2 when an unexpected excessive voltage is applied to the external terminal 1. This input protection circuit 3 includes a resistor R to dampen unexpected overvoltage, and a resilient surface breakdown or zener at the pn junction between the drain region and the semiconductor substrate. n-channel/l/MIS l!" E i' Q for clamping to clamp unexpected excessive kite pressure that causes breakdown, and the resistance R1 is formed by a diffusion layer 1-, thereby forming a connection with the semiconductor substrate. A zener diode D is placed in between,
and the zener diode D2, which has a higher breakdown voltage in the reverse direction of the pn junction than the zener diode D1 (and is especially provided according to [Embodiment 1] of the present invention and is disposed closer to the external terminal 1). 2 (5) is a plan view showing the main parts of (1) to explain the specific structure of the equivalent circuit diagram shown in FIG.
FIG. 2 FB) is a sectional view taken along the line ■-■ of the second drawing. In addition, in FIG. 2 (5), in order to make the drawing easier to see, lf! should be provided in each conductive layer flJj.
3 Green membrane not shown. □ Fig. 2 (At, 03+, 4 is made of silicon single crystal, and, for example, I XI O''' [atomic side/
It is a p-type semiconductor substrate having a low impurity concentration of about cta 1, and is used to constitute the semiconductor substrate 10. Reference numeral 5 denotes a main surface portion of the semiconductor substrate 4, and is a field insulating film provided between semiconductor elements to electrically isolate them. Reference numeral 6 designates a Tp-type channel stopper region provided in the semiconductor substrate 4 below the field insulating film 6, which further electrically isolates the semiconductor elements.
It's from Kome. 7 is a first insulating film provided on the main surface of the semiconductor substrate 4 other than the yield insulating film 5; 3. This insulating film can be omitted. 8 is a second insulating film provided in a portion of the first insulating film 7-1, and a gate electrode, a first insulating film 7-1, and a gate electrode. f? This is for electrically separating the A-th wiring and the second layer wiring provided in the second insulating film 8F section. Reference numeral 9 designates the aforementioned external terminals (1) provided several times around the semiconductor substrate 4, and is made of, for example, an aluminum film. 0 is the main part of the semiconductor substrate 4, for example, a 2×10” provided between the external terminal 9 and the input stage circuit described later
The resistor (R7) is made of an n+ type semiconductor region with a high impurity concentration of ~3xio" [atomic example/cml], and is protected against an unexpected excessive charge that would cause electrostatic damage that would be applied to the external terminal 9. One end of the resistor 10 is electrically connected to the external terminal 9 via the connection hole 11.A pair of resistors 12 are installed on the main surface of the semiconductor substrate 4 and are spaced apart from each other. For example, 2×1
0" ~ 3 X 10" [Atom side/cra':l
This is an n+ type semiconductor region having a relatively high impurity concentration, and each region serves as a source region S and a drain region to constitute an n-channel MISFET Qs for clamping. The drain region is provided between the external terminal 9 and the input stage circuit. Further, the drain region and the other end of the diffusion layer resistor 10 are integrated and electrically connected. 1
A gate electrode 3 is provided on the main surface of the semiconductor substrate 4 between the semiconductor regions 12, and is used to configure an n-channel conductivity type MISFET Q3 for clamping. Reference numeral 14 denotes a wiring, one end of which is electrically connected to the semiconductor region 12 through a connection hole 15, and the other end electrically connected to the gate electrode 13 through a connection hole 16. Reference numeral 17 denotes a wiring, one end of which is electrically connected to the semiconductor region 12 via a connection hole 18, and the other end electrically connected to a gate electrode constituting an input stage circuit to be described later through a connection hole 19. It is connected. 20 is lXl0" [atomic example/cm
It is an n-type well region with an impurity concentration of about 0Ml5 in the input stage circuit.
This is for configuring Q+. 21 is the above n
q(7) A p-type well region provided on the main surface of the semiconductor substrate 4 adjacent to or apart from the well region 20;
Input stage circuit 0Ml50) n-channel MiSFETQ
. Reference numeral 22 denotes a pair of p + -type semiconductor regions which are provided separately on the main surface of the n - -type well region 2o, and are used for the source region S and the tunnel region of the p-channel conductivity type MISFETQ of the input stage circuit. It is for configuring. 23 is a pair of p-type well regions 21 and provided at a distance from each other on the main surface, for example, 2X1019 to 3X.
It is an n+ type semiconductor region having a high impurity concentration of about 10" [atomic side/cf+l)], and is used to configure the source region S and drain region DiK of +1SFETQ2 to the n-channel conductivity type of the input stage circuit. The semiconductor region 12 and the resistor 10 for configuring the n-channel MISFET Qs for the flang are formed in the same manufacturing process as the semiconductor region 23 in the IC manufacturing process. and the semiconductor region 23, and is a gate electrode provided in common between the p-channel and n-channel A/MI
5FETQ, %- and Q2 are configured for 1-filtering. Reference numeral 25 denotes a wiring to which an operating voltage VCC of 10 is applied, and one end thereof is electrically connected to the semiconductor region 22, which becomes the source region S, through a sliding hole 26. 2
Reference numeral 7 denotes a wiring to which the ground τIL level GND is applied, and one end thereof is electrically connected to the semiconductor region 23 which becomes the source region S via the connection hole 28 . Reference numeral 29 denotes a wiring to which an output signal from the input stage circuit is applied, one end of which is electrically connected to the semiconductor region 22.23 which becomes a drain region through a connection hole 30.31, and the other end can be electrically connected to other circuit elements. 3
Reference numeral 2 denotes a connecting portion between the external terminal 9 and the resistor 10, which is electrically connected to the resistor 0 and covered with a half 7. T
V: [Embodiment 1] of the present invention provided on the main surface of the body substrate 4
This is a low-type semiconductor region. The impurity concentration is as low as, for example, 1 x 101'''atoms/cnl', and is 100) '4. The semiconductor region 32 is formed by the same manufacturing process as the well region 20 of the mold. This is to prevent the resistor 10 around the human power section (connection hole 11) from being destroyed even if an excessive voltage is input to the resistor 0. This is because the resistor 10 and the semiconductor substrate are connected to the input section. A diode D that is parasitically generated at the pn junction between the semiconductor region 32 and the semiconductor substrate 4 should be provided, which has higher breakdown strength against unexpected overvoltage than the diode D that is parasitically generated at the pn junction between the semiconductor region 32 and the semiconductor substrate 4. In other words, the extension of the depletion layer formed by the pn junction between the n-type semiconductor region 32 and the p-type semiconductor substrate 4 is
This is because the elongation is larger than the elongation of the depletion layer formed by the pnW junction of the p-type semiconductor substrate 4 and the p-type semiconductor substrate 4. Therefore, it is possible to improve the breakdown strength of the resistor 10 against unexpected excessive voltage that may cause electrostatic damage at the connection portion between the external terminal 9 and the resistor 10. [Example ■] Figure 3 is an IO diagram for explaining [Example H] of the present invention.
In particular, it is an equivalent circuit diagram showing an outline of the input capture circuit. In FIG. 3, 3A is an input retention circuit according to [Embodiment 2] of the present invention, which is provided between the external terminal 1 and the input stage circuit 2. This is to prevent electrostatic damage to the input stage circuit 2 in such a case. R2 is a resistor according to [Embodiment 2] of the present invention that is provided before the resistor R7, and like the resistor R7, it is used to dampen unexpected excessive voltage that may cause electrostatic damage. be. This resistor R2 has a higher breakdown strength than the resistor R8 against an unexpected overvoltage that may cause electrostatic damage. The fourth drawing shows a specific example of the equivalent circuit diagram shown in FIG. FIG.
Figure (E is a cross-sectional view taken along the line IV-IV in Figure 4 (5). In Figure 4 (Al), Figure 2 (5)
Similarly, in order to make the drawing easier to see, the insulating film that should be provided between each conductive layer is not shown. In FIGS. 4(5) and 4(B), 33 is electrically connected to the external terminal 9 through the contact hole 34, and is provided on the main surface of the semiconductor substrate 4 of a certain value, e.g., 2X10" to 3XIO". [
It is an n+ type semiconductor region having a high impurity concentration of approximately atomic atoms/c+ff 1, and is primarily used to reduce the contact resistance value between the external terminal 9 of the metal material and the silicon material. Reference numeral 35 denotes a connecting portion between the external terminal 9 and the semiconductor region 33, one end of which is electrically connected to the semiconductor region 33, and the other end electrically connected to the previous stage of the resistor 10 made of a semiconductor region. Semiconductor substrate 4 covers them.
711n according to [Example ■] of the present invention provided on the crown part
- type semiconductor region. The impurity concentration is, for example, I
It has a low impurity concentration of about 11'1 atoms/cnt1, and is formed in the same manufacturing process as the n-type well region 20 in the manufacturing process of step 10. .This semiconductor region 35 is
External terminal 9 may be exposed to unexpected excessive voltage that may cause electrostatic damage.
This is to prevent the resistor 10 around the input portion from being destroyed even if the unexpected excessive voltage is applied to the resistor 1 (). This requires a resistor 1 at the input section.
The diode D2, which is parasitically generated at the pn junction between the semiconductor region 35 and the semiconductor substrate 4, has higher breakdown strength against unexpected overvoltage than the diode D1, which is parasitically generated at the pn junction between the semiconductor region 35 and the semiconductor substrate 4. A resistor R? with a higher resistance value than the resistor to(, R+) is provided between the external terminal 9 and the resistor 10 by the semiconductor region 35. By providing The resistor R2 is connected to the semiconductor region 3 constituting it.
Since the impurity concentration of 5 is low, the depletion layer formed at the pn junction between the semiconductor region 35 and the semiconductor substrate 4 is highly dependent on the voltage. In other words, the IO operating voltage ■. When C is applied to the external terminal 9, the semiconductor region 35
The expansion of the depletion layer formed inside is small, and the apparent resistance value of the resistor R2 becomes small, causing electrostatic damage.If an unexpected excessive voltage is applied to the external terminal 9, , Semiconductor region: 35 The depletion layer formed in the same portion is greatly extended, and the apparent resistance value of the resistor R2 becomes large. Therefore, at the connection between the external terminal 9 and the resistor 10, what is the breakdown strength of the resistor 10 against unexpected excessive voltage that may cause electrostatic damage? l>, the resistance value can be varied depending on the voltage applied manually.
2, it is possible to manually apply power to the resistor 10 after an unexpected overvoltage that would cause electrostatic damage has sufficiently cooled down. [Effects] (1) Equipped with a resistor made of a semiconductor region.
In the device 10 equipped with a human power protection circuit, a semiconductor region 32 having the same conductivity type and lower impurity concentration as that covering the resistor 10 is provided on the semiconductor substrate at the connecting portion between the external terminal 9 and the resistor 10. 4 on the main surface, the extension of the depletion layer formed at the pn junction caused by them is thicker than the extension of the depletion layer formed at the pn junction caused by the resistor 10 and the semiconductor substrate 4. , resistor 10 against unexpected overvoltage to cause electrostatic damage.
can improve the breaking strength of (2) Connect electrically between the external terminal 9 and the resistor 10, have the same conductivity as the resistor 10, have a lower impurity concentration than that, and depend on the input voltage. By providing the semiconductor region 35 whose resistance value can be varied by changing the resistance value, unexpected overvoltage that may cause electrostatic damage is blunted, and damage to the resistor 10 due to unexpected overvoltage is prevented. Although the invention made by the present inventor has been specifically explained above based on Examples, the present invention is not limited to the above Examples, and various modifications can be made without departing from the spirit of the invention. Needless to say, changes can be made.For example, in [Embodiment 2], it is possible to omit the semiconductor region 33 provided to reduce contact resistance.Also, it is possible to omit the semiconductor region 33 provided in order to reduce the contact resistance. The present invention can also be applied when the molds are reversed.

[Brief explanation of drawings]

FIG. 1 is an IO diagram for explaining [Embodiment 1] of the present invention.
, % is an equivalent circuit diagram showing an outline of the human power protection circuit, the second drawing is a plan view showing 10 main parts for explaining the concrete structure of the equivalent circuit diagram shown in FIG. Figure 2 (Bl is a sectional view taken along the line ■-■ in the second drawing, and Figure 3 is an I
O, in particular, an equivalent circuit diagram showing an overview of the input protection circuit; Figure 4 (5) is a plan view showing the main parts of the process 0 to explain the specific structure of the equivalent circuit diagram shown in Figure 3; , Figure 4 (
13) is a sectional view taken along the line IV-IV in FIG. 4(5). In the figure, 1.9...external terminal, 2...manual stage 1-way,
3゜3A...Input retention circuit, 4...Semiconductor board, 5
... Field insulating film, 6... Channel strike region, 7°8... Insulating film, 10... Diffusion layer resistance,
11,15°16.18,19,26,28,30,3
1゜34... Connection hole, 12.22.23, 32, 33
35: Semiconductor region, 13.24: 14.17, 25, 27.29: Self-line, 20°21: Well region. Agent: Patent Attorney Akio Takahashi, :゛・,Nino

Claims (1)

[Claims] 1. A first semiconductor region of a second conductivity type having an input section provided on the main surface of a first m-type semiconductor substrate and an output section separated from the human power section; A first wiring is provided, one end of which is electrically connected to a human power section of the semiconductor region, and the other end is electrically connected to an external terminal, and an output section of the first semiconductor region and one end thereof are electrically connected. In the semiconductor integrated circuit device, at least one of the first semiconductor regions is connected to A second semiconductor region is provided in the semiconductor substrate to be electrically connected to the input portion and to cover the input portion, and has a second conductivity type and a lower impurity concentration than the first semiconductor region. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein the first semiconductor region is partially partitioned by the second semiconductor region within the second semiconductor region.