JPH0732236B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit. .

[Conventional technology]

A semiconductor integrated circuit device having a MISFET is apt to cause so-called electrostatic breakdown in which the gate insulating film forming the input stage circuit is destroyed by a steep and extremely high excessive voltage induced by artificial handling. Therefore, an electrostatic breakdown prevention circuit (protection circuit) is provided between the external input terminal to which an excessive voltage is input and the input stage circuit.

The electrostatic breakdown prevention circuit is generally composed of a protective resistance element and a clamp MISFET as described in, for example, Japanese Patent Application No. 59-216181.

The protective resistance element is composed of an n ⁺ type semiconductor region,
It has a feature that it can be formed in the same manufacturing process as the source region or the drain region of the MISFET forming the internal circuit.
The clamp MISFET has a feature that it can be formed in the same manufacturing process as the MISFET forming the internal circuit, like the protective resistance element.

The protective resistance element of the electrostatic breakdown prevention circuit configured as described above can blunt an excessive voltage input to the external input terminal and flow it to the substrate side by breakdown. Further, the clamp MISFET can reduce the peak value of the excessive heavy pressure relaxed and summed.

[Problems to be solved by the invention]

The present inventor has found the following problems as a result of the examination in the above-mentioned technology.

Excessive voltage that is input to the external input terminal has a substrate resistance of 10 [Ω
Since it is as high as [cm], it does not flow sufficiently to the substrate side due to breakdown of the protective resistance element. Therefore, the excessive current is directly input to the drain region of the clamp MISFET, and the clamp MISFET is destroyed.

An object of the present invention is to provide a technique capable of improving the electrical reliability against electrostatic breakdown in a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit.

Another object of the present invention is to provide a technique capable of reducing the occupied area of the electrostatic breakdown prevention circuit and improving the degree of integration in a semiconductor integrated circuit device having the electrostatic breakdown prevention circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The following is a brief description of the outline of the typical inventions among the inventions disclosed in the present application.

That is, in a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit, a conductive film having a low resistance value electrically connected to a main surface of a semiconductor substrate or a well region at a position close to a semiconductor region forming a protective resistance element. Provide layers.

[Action]

According to the above means, an excessive current flowing in the semiconductor substrate or the well region due to the breakdown of the protective resistance element can be immediately charged to the parasitic capacitance formed in the conductive layer. Excessive current flowing in the circuit can be reduced and its destruction can be prevented. That is, the electrical reliability of the electrostatic breakdown prevention circuit or the next-stage circuit against electrostatic breakdown can be improved.

[Example I]

The present Example I is an example in which the present invention is applied to a semiconductor integrated circuit device provided with a complementary MISFET (hereinafter referred to as CMOS).

FIG. 1 (equivalent circuit diagram) shows an input section of a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit which is Embodiment I of the present invention.

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

As shown in FIG. 1, the external input terminal (bonding pad) BP and the input stage circuit I of the internal circuit are electrically connected via an electrostatic breakdown prevention circuit II.

The input stage circuit I includes an n-channel MISFETQn and a p-channel MISF.
It is composed of a CMOS inverter circuit consisting of ETQp.

Vss is a reference voltage (for example, a terminal for circuit ground voltage 0 [V], Vcc is a power supply voltage (for example, circuit operating voltage 5 [V])
It is a terminal for. Vout is an output signal terminal of the inverter circuit.

The electrostatic breakdown prevention circuit II includes a protective resistance element R and an n-channel type MISFET Qc for clamping. One end of the protective resistance element R is connected to the external input terminal BP and the other end is MI.
It is connected to the input stage circuit I through the drain region of SFETQc. The source region and the gate electrode of MISFETQc are connected to the reference voltage terminal Vss.

Next, a specific configuration of this embodiment will be described.

An input portion of a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit which is Embodiment I of the present invention is shown in FIG. 2 (plan view of a main portion) and cut along a line IIIa-IIIa and a line IIIb-IIIb in FIG. A cross section is shown in FIG. Note that FIG. 2 does not show an insulating film other than the field insulating film provided between the conductive layers in order to make the configuration of this embodiment easier to understand.

In FIGS. 2 and 3, reference numeral 1 is a p ⁻ type semiconductor substrate made of single crystal silicon. Reference numeral 2 is an n ^- type well region, which constitutes a CMOS.

Reference numeral 3 is a field insulating film, and 4 is a p-type channel stopper region, which are provided on the main surface of the semiconductor substrate 1 or the well region 2 between semiconductor elements.

The MISFET Qn or Qp forming the input stage circuit I is provided on the main surface of the semiconductor substrate 1 or the main surface of the well region 2 in the region surrounded by the field insulating film 3. That is, MISFETQn
Is composed of a semiconductor substrate 1, a gate insulating film 5, a gate electrode 6, and a pair of n ⁺ type semiconductor regions 7A used as source or drain regions. MISFETQp is a well region 2 and a gate insulating film 5. , A gate electrode 6, and a pair of p ⁺ type semiconductor regions 8 used as a source region or a drain region.

Clamping MISFET Qc that composes the electrostatic discharge prevention circuit II
Like MISFETQn, is composed of a semiconductor substrate 1, a gate insulating film 5, a gate electrode 6 and a pair of n ⁺ type semiconductor regions 7B.

The protective resistance element R that constitutes the electrostatic breakdown prevention circuit II is n ⁺
The semiconductor region 7C of the mold. Protective resistance element R
Is integrally formed with the semiconductor region 7B whose one end is used as the drain region of the MISFET Qc.

The protective resistance element R and the MISFET Qc are configured in the same manufacturing process as the MISFET Qn that constitutes the internal circuit.

An interlayer insulating film 9 covers the semiconductor element. Reference numeral 10 is a connection hole, which is provided by removing the insulating film 9 on the predetermined semiconductor regions 7A to 7C, 8 or the gate electrode 6.

Reference numerals 11A to 11G denote conductive layers, which are electrically connected to the semiconductor regions 7A to 7C, 8 and the gate electrode 6 or the semiconductor substrate 1 through the connection holes 10. The conductive layers 11A to 11G are made of, for example, a conductive material such as an aluminum film or an aluminum film into which a predetermined additive is introduced, which has a much smaller specific resistance value than the semiconductor substrate 1.

The conductive layer 11A constitutes the external input terminal BP and is electrically connected to the other end of the semiconductor region 7C constituting the protective resistance element R.

The conductive layer 11B constitutes wiring for the reference voltage Vss, and the dielectric layer 11C
Is designed to form the wiring for the power supply voltage Vcc,
The conductive layer 11D constitutes the output signal wiring Vout. The conductive layer 11E is the semiconductor region 7B used as the drain region of the MISFET Qc and the gate electrode 6 of the MISFET Qn, Qp.
Wiring for electrically connecting to and is configured.

One end of the conductive layer 11F is electrically connected to the main surface of the semiconductor substrate 1 at a position close to the protective resistance element R (semiconductor region 7C) through the connection hole 10, and the other end is used as a guard ring. It is electrically connected to the conductive layer 11G. The conductive layer 11G is provided so as to extend around the periphery of the semiconductor chip and forms a parasitic capacitance having a large capacitance value. The conductive layer 11G is configured to hold the potential of the semiconductor substrate 1 at the reference voltage Vss.

As described above, by providing the conductive layer 11F electrically connected to the main surface of the semiconductor substrate 1 at a position close to the protective resistance element R, the pn of the semiconductor region 7C forming the protective resistance element R and the semiconductor substrate 1 is formed. An excessive current flowing to the semiconductor substrate 1 side due to the breakdown at the junction is passed through the conductive layer 11F to the conductive layer 1
Since the parasitic capacitance formed by 1 G can be immediately charged, the excessive current flowing in the MISFET Qc or the input stage circuit I can be reduced. Therefore, the breakdown of the MISFET Qc or the input stage circuit I can be prevented, and the electrical reliability of the electrostatic breakdown prevention circuit II or the input stage circuit I against electrostatic breakdown can be improved.

Further, since the electrical reliability of the electrostatic breakdown prevention circuit II can be improved, the area occupied by the semiconductor region C7 forming the protective resistance element R can be reduced and the degree of integration can be improved.

In addition to the conductive layer 11G used as a guard ring, the conductive layer 11F may be connected to, for example, a wiring for the reference voltage Vss that extends around the semiconductor chip.

Further, it is preferable to connect the conductive layer 11F and the semiconductor substrate 1 at a position closer to the MISFET Qc side than to the external input terminal BP (conductive layer 11A) side. This is because the excessive current that has been relaxed to some extent in the protective resistance element R breaks down,
This is because it is possible to prevent thermal destruction of the pn junction during breakdown.

In addition, the semiconductor region 7C used as the protective resistance element R
In order to reduce the impurity concentration gradient with the semiconductor substrate 1, a low-concentration n-type semiconductor region may be interposed between the semiconductor substrate 1 and the semiconductor substrate 1. The n-type semiconductor region is, for example,
It is composed of an n-type well region. Further, the n-type semiconductor region is an n-type low-concentration semiconductor region formed along a high-concentration semiconductor region (source region or drain region) when a double drain structure MISFET is formed in an internal circuit. You may form in the same manufacturing process.

Example II

Example II is another example of the present invention in which the contact resistance value between the conductive layer provided near the protective resistance element and the substrate (or well region) was reduced.

An input portion of a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit which is Embodiment II of the present invention is shown in FIG. 4 (main part sectional view).

In Example II, as shown in FIG. 4, a P ⁻ type well region 2 is provided on an n ⁻ type semiconductor substrate 1. The conductive layer 11F provided near the semiconductor region 7C used as the protective resistance element R is electrically connected to the well region 2 via the P ⁺ type semiconductor region 8A. 8A is formed in the same manufacturing process as the semiconductor region 8 of the MISFET Qp, for example.

In this way, by electrically connecting the conductive layer 11F and the well region 2 via the semiconductor region 8A, the contact resistance value can be reduced as compared with the case where they are directly connected, so that a break occurs. An excessive current flowing down to the well region 2 can be immediately charged by the parasitic capacitance formed by the conductive layer 11F.

Although the invention made by the present inventor has been specifically described based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

For example, in the present invention, the electrostatic breakdown prevention circuit II may be composed of only the protective resistance element R.

Further, in the present invention, a conductive layer formed in the same manufacturing process as the gate electrode 6 may be electrically connected to the main surface of the semiconductor substrate 1 in a position close to the protective resistance element R.

Further, the present invention may be applied to a protective resistance element of an electrostatic breakdown prevention circuit connected to an external output terminal.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

A semiconductor integrated circuit device having an electrostatic breakdown prevention circuit, comprising a conductive layer electrically connected to a main surface of a semiconductor substrate or a well region in a position close to a semiconductor region forming a protective resistance element. The excessive current flowing in the semiconductor substrate or the well region due to the breakdown of the protective resistance element can be charged in the parasitic capacitance formed in the conductive layer, so that the excessive current flowing in the clamp MISFET or the next stage circuit can be reduced. , Its destruction can be prevented.
Therefore, the electrical reliability of the electrostatic breakdown prevention circuit or the next-stage circuit against electrostatic breakdown can be improved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an input section of a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit which is Embodiment I of the present invention, and FIG. 2 is an electrostatic breakdown prevention circuit which is Embodiment I of the present invention. FIG. 3 is a cross-sectional view taken along line IIIa-IIIa and line IIIb-IIIb in FIG. 2, and FIG. 4 is an embodiment II of the present invention. FIG. 4 is a cross-sectional view of a main part of an input section of a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit. In the figure, BP: external input terminal, I: input stage circuit, II:
Electrostatic breakdown prevention circuit, Q ... MISFET, R ... Protective resistance element, 1 ... Semiconductor substrate, 2 ... Well region, 3 ... Field insulating film, 4 ... Channel stopper region, 5 ... Gate insulating film, 6 ... Gate electrode, 7A to 7C, 8, 8A ... Semiconductor region, 9 ... Insulating film, 10 ... Connection hole, 11A to 11G ... Conductive layer.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having an electrostatic breakdown prevention circuit having a resistance element, wherein the resistance element is of a second conductivity type provided on a main surface of a semiconductor substrate of a first conductivity type or a well region. A semiconductor integrated circuit device comprising a semiconductor region, and a conductive layer electrically connected to the main surface of a semiconductor substrate or a well region adjacent to the resistance element. 2. The conductive layer is electrically connected via a semiconductor region of the same first conductivity type as the semiconductor substrate or the well region and having an impurity concentration higher than that. The semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit according to claim 1, wherein the conductive layer is electrically connected to a wiring having a large parasitic capacitance value such as a guard ring. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the conductive layer is made of an aluminum film or the like having a small specific resistance value.