GB2151846A - A high voltage destruction-prevention circuit for a semiconductor integrated circuit device - Google Patents
A high voltage destruction-prevention circuit for a semiconductor integrated circuit device Download PDFInfo
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- GB2151846A GB2151846A GB08431596A GB8431596A GB2151846A GB 2151846 A GB2151846 A GB 2151846A GB 08431596 A GB08431596 A GB 08431596A GB 8431596 A GB8431596 A GB 8431596A GB 2151846 A GB2151846 A GB 2151846A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 239
- 239000000758 substrate Substances 0.000 claims abstract description 67
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- 239000012212 insulator Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 230000006378 damage Effects 0.000 abstract description 31
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 8
- 108091006146 Channels Proteins 0.000 description 6
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- 239000000470 constituent Substances 0.000 description 3
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 230000009467 reduction Effects 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
An IC is provided with high voltage destruction-preventing circuit (7) which consists of a resistor (R1) and a bipolar lateral transistor (Tr). A first semiconductor region constitutes the resistor (R1), and a second semiconductor region of the same conductivity type as the first semiconductor region is spaced at a predetermined distance from the first semiconductor region. Thus, a parasitic, lateral transistor (Tr) made up of the semiconductor substrate and first and second semiconductor regions is formed. In addition, the length of opposed edges of the first and second semiconductor regions can be set substantially equal to or not less than the channel width of a clamping MISFET (Q2) so as to reduce rapidly and reliably an unexpected, excessively high voltage which could cause destruction of the input circuit. The second semiconductor region may be part of a guard ring or other structure carrying a suitable bias voltage thus reducing the additional space required for the protective circuit. <IMAGE>
Description
SPECIFICATION
A high voltage destruction-prevention circuit for a semiconductor integrated circuit device
This invention relates generally to techniques for preventing an integrated circuit element from being destroyed by unexpected, excessively large applied energy, and more particularly to techniques which can be applied effectively to the prevention of the electrostatic destruction of a semiconductor integrated circuit device (which will hereinafter be called "IC").
In an IC using an insulated gate type field-effect transistor (which will hereinafter be called "MISFET" as an abbreviation of metal insulator semiconductor field -effect transistor) as a main constituent element thereof, an electrostatic destruction-preventing circuit is typically provided between an external terminal (bonding pad) to which the unexpected, excessively large energy is applied and an input circuit of the IC. The purpose of this is to prevent the destruction (which will hereinafter be referred to as "electrostatic destruction") of a gate-insulating film, which constitutes a MISFET, of an input circuit for an integrated circuit, due to the unexpected, excessively large energy (voltage) generated when a person handles the IC.This electrostatic destructionpreventing circuit generally consists of a diffused semiconductor layer resistor for weakening an unexpected, excessively high voltage which is applied to an external terminal and which causes the electrostatic destruction, and a clamping MISFET for discharging such an unexpected, excessively large energy into a semiconductor substrate. The clamping MISFET has an earth potential caused by connecting a source region and a gate electrode thereof together electrically, and is adapted to clamp an unexpected, excessively high voltage by the surface breakdown or Zener breakdown occurring in the PN junctions of the drain region and channel region thereof with respect to the semiconductor substrate.
The clamping MISFET is formed in the same step in a process for manufacturing a MISFET which forms an integrated circuit, so that there is a large demand for the clamping MISFET. The semiconductor layer resistor mentioned above also has a large demand since it is formed in the same step in a process for making the source region and drain region of a
MISFET which has additionally a diode annexed to a semiconductor substrate and which constitutes an integrated circuit.
in such an electrostatic destruction-preventing circuit, a semiconductor layer resistor provided on the front side of a clamping MISFET is much more liable to be destroyed than the clamping MISFET (Japanese Patent Publication No. 101283/79). From our research we consider that, since the absorption of the unexpected, excessively large energy which causes the electrostatic destruction depends mainly on the clamping MISFET, a large current will first flow to the semiconductor layer resistor, which is provided on the front side of the clamping MISFET (on the side of the external terminal), to destroy the same.
We have discovered that an input circuit connected to a destruction-preventing circuit having a semiconductor layer resistor, which is close to a semiconductor layer connected to a power source voltage or an earth potential, has a destructionresisting voltage 2 - 5 times as high as that of an input circuit connected to any other type of destruction-preventing circuit. We have also discovered that the destructio-resisting voltage depends upon the length (which will hereinafter be called "length of opposed edges") of the substantially parallelopposed edges of the semiconductor layer resistor and the semiconductor layer close thereto.
An object of the present invention is to provide an
IC provided with an electrostatic destructionpreventing circuit, which is capable of increasing the electrostatic destruction-resisting voltage with respectto an unexpected, excessively high voltage in its integrated circuit.
Another object of the present invention is to provide an IC provided with an electrostatic destruction preventing circuit, which is capable of improving the destruction strength with respect to an unexpected, excessively high voltage of the electrostatic destruction-preventing circuit.
According to one aspect of the present invention there is provided a semiconductor integrated circuit device formed in a semiconductor substrate having a first conductivity type and provided with a high voltage destruction-preventing circuit which includes:
(a) a first semiconductor region of a second conductivity type having one end portion connected electrically with an external terminal and the other end portion connected electrically with a field-effect transistor which forms an input circuit for an integrated circuit; and
(b) a second semiconductor region of a second conductivity type provided in said semiconductor substrate and spaced at a predetermined distance from said first semiconductor region,
wherein a portion of predetermined length of an edge of said second semiconductor region is opposed to and substantially parallel to an edge of said first semiconductor region to provide a spaced interface having said predetermined length between said portion of said edge of said second semiconductor region and said edge of said first semiconductor region to form a lateral protection transistor comprised of said first and second semiconductor regions and a portion of said substrate located in said spaced interface to absorb a portion of an unexpected voltage having a voltage level higher than a normal operation voltage of said input circuit.
According to a second aspect of the present invention there is provided a semiconductor integrated circuit device formed in a semiconductor substrate having a first conductivity type and provided with a high voltage destruction-preventing circuit which includes:
(a) a resistor formed of a first semiconductor region of a second conductivity type having one end portion connected electrically with an external terminal and the other end portion connected electrical- ly with a gate electrode of an insulated gate type field-effect transistor which forms an input circuit for an integrated circuit; and
(b) a second semiconductor region of a second conductivity type provided in said semiconductor substrate and spaced at a predetermined distance from said first semiconductor region,
wherein a portion of predetermined length of an edge of said second semiconductor region is opposed to and substantially parallel to an edge of said first semiconductor region to provide a spaced interface having said predetermined length between said portion of said edge of said second semiconductor region and said edge of said first semiconductor region to form a lateral protection transistor having one of an emitter or a collector comprised of said resistor, a base comprised of a portion of said substrate located in said spaced interface and the other of said emitter or collector comprised of said second semiconductor region to absorb a portion of an unexpected voltage having a voltage level higher than a voltage which would destroy a gate insulator film of said gate electrode.
The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein :- Figure 1 is a schematic diagram of a DRAM, for use in describing Examples l, ll and III of the present invention;
Figure 2 is a diagram which shows an electrostatic destruction-preventing circuit provided in the DRAM and which is drawn for describing Examples I, II and
Ill of the present invention;
Figure 3 is a plan view of a principal portion of the electrostatic destruction-preventing circuit, drawn for describing the concrete construction of Example I of the present invention;
Figure 4 is a sectional view taken along line X-X in
Figure 3;
Figure 5 is a diagram for use in describing the effects of Example Iin the present invention;;
Figure 6 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, drawn for describing the construction of Example II of the present invention;
Figure 7 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, drawn for describing the construction of Example Ill of the present invention;
Figure 8 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, drawn for describing the construction of Example IV of the present invention; and
Figure 9 is a sectional view taken along line Y-Y in
Figure 8.
Examples l, ll and Ill will be described with reference to [ Cs, each of which is formed on a semiconductor substrate consisting of a silicon single crystal, especially, a dynamic random access memory (which will hereinafter be called "DRAM" (Dynamic Random Access Memory)), and Example
IV with reference to an IC formed on a semi-insulated substrate consisting of gallium arsenide (GaAs).
In all of the drawings, the parts having the same functions are designated by the same reference numerals or letters, and the descriptions of such parts will not be given repeatedly.
Example I
Figure 1 is a schematic diagram of a DRAM for describing Example I of the present invention as well as Examples II and Ill which will be described later.
Referring to Figure 1, the IC comprises a p--type semiconductor substrate 1, which consists of a silicon single crystal and has a low concentration of impurities, and which is used to form a DRAM. It further comprises a memory array 2 positioned in the central portion of the semiconductor substrate 1 and provided with a plurality of memory cells arranged in a matrix, having MISFETs as the main constituent elements and constituting a memory function of the DRAM. Peripheral circuits 3 and 4 are provided on the upper and lower portions of the semiconductor substrate 1, and external terminals 5 (bonding pads) are provided at the peripheral portion of the semiconductor substrate 1.The external terminals 5 receive from the outer side of the DRAM a signal for energizing the internal circuit therein and output a signal from the internal circuit in the DRAM to the outside thereof. These signals are in a range of 0 - 5 V (or 7 V) in normal operation. The external terminals 5 often receive by accident the unexpected, excessively large energy (voltage) which could cause the electrostatic destruction in an input circuit connected electrically with the external terminals 5. An outermost peripheral portion 6 of the semiconductor substrate 1,forms a guard ring consisting of an nt-type semiconductor region having a high concentration of impurities and adapted to be set to the substrate potential, earth potential or power source potential.The guard ring 6 is used to capture unneccessary minority carriers occurring mainly in the interior of the semiconductor substrate 1.
Figure 2 is a diagram showing an electrostatic destruction-preventing circuit provided in a DRAM, and drawn for describing Example I of the present invention and Examples II and II, which will be described later, thereof.
Referring to Figure 2, the circuit includes an external terminal BP(1) referred to above as terminals 5, an n-channel MISFET Q, provides so as to form an input circuit for the DRAM, a source region S, of the MISFET 01, a drain region D1 of the MlSFETQ1, and a gate electrode G1 of the MOSFET Q,.
An electrostatic destruction-preventing circuit 7, according to the present invention, is provided between the external terminal BP(1) and the gate electrode G1 of the MISFET Q. The circuit 7 is provided so as to prevent the electrostatic destruction from occurring in the gate electrode G1 of the
MISFET Q1, when such unexpected, excessively large energy that causes the electrostatic destruction, for example, an excessively high voltage due to the static electricity, is applied to the external terminal BP(1). A resistor R1 consisting of an n-type semiconductor region, for example, a diffused semiconductor layer, is used to weaken an unexpected, excessively high voltage.A diode D1 having a backward breakdown voltage of about 20 V is provided parasitically by the PN junction of the resistor R1 composed of an n-type semiconductor layer and a drain region D2 which consists of an n-type semiconductor region of a MISFET Q2 which will be described later, and the semiconductor substrate 1. An n-channel MISFET Q2 is provided for clamping an unexpectedly, excessively high voltage.
The MISFET Q2 has a source region S2 which is connected with earth potential GND with a gate electrode G2, and a drain region D2. A transistor Tr is connected at its collector region C with a front step portion of the resistor R1, at its emitter region E with a terminal V1 of the substrate potential, earth potential or power source potential, and at its gase region B with the semiconductor substrate 1. When a predetermined electric potential (about 20 V) is applied to the collector region C of the transistor Tr, the electric potential in the base region B increases to turn on the transistor Tr. This transistor Tr also serves to reduce an unexpected, excessively high voltage with the MISFET Q2.The base region B is connected with a predetermined portion between the external terminal BP(1) or 5 and gate electrode G1 through the parasitic resistor R2 formed by the semiconductor substrate 1 and diode Dl. A capacitor
C which occurs parasitically in the semiconductor substrate 1, is connected at its one end with the semiconductor substrate 1 and at the other end with a terminal V2 having a predetermined electric potential, i.e., earth potential. The capacitor C is used to alleviate the variations in the electric potential applied to the semiconductor substrate 1 by a pulse signal. A diode Dll occurs parasitically by the junction of the emitter region E consisting of an n-type semiconductor region and the semiconductor substrate 1. A terminal 113 has the same level of electric potential as the terminal V1.
The construction of an electrostatic destructionpreventing circuit shown in Figure 2 will now be described with reference to Figures 3 and 4.
In order that the drawings can be easily understood, the insulating films to be provided among the wiring layers are not shown in Figure 2 and the plan views thereafter.
Referring to Figures 3 and 4, a field insulating film 8 is provided on the main surface portion, which is between semiconductor elements, of a semiconductor substrate 1 so as to electrically separate the semiconductor elements. A p--type channel stopper region 28 is formed under the field insulating film 8 acting as a part of the base region B of the transistor
Tr. An insulating film 9 is provided in the main surface portion of the semiconductor substrate 1, on which semiconductor elements are to be formed, to form mainly a gate insulating film for MISFETs. A semiconductor layer 10 represents the resistor R1 in
Example I of the present invention. Resistors R1 is provided on the main surface portion, which is between an external terminal 5 and a gate electrode
G1 of an input circuit-forming MISFET Q1, of the semiconductor substrate 1, and it consists of an type semiconductor region.This semiconductor layer resistor 10 is connected electrically at its one end portion with an external terminal 5 through a connecting hole 11. At the other end it is connected with a gate electrode (G1) 13 of the MISFET Q1 and with a drain D2, which is formed continuously and unitarilywith the semiconductor layer resistor 10, of a MISFET Q2. The connection with gate G1 is through a connecting hole 12. The part of the semiconductor resistor 10 which is on the side of the external terminal 5 forms an input region 10A having an edge of a length L opposed to and extending substantially in parallel with a guard ring 6 with a semiconductor substrate portion 1 therebetween.Thus, an npn-type lateral tranistor Tr is formed on the front side of the semiconductor layer resistor 10, in which transistor
Tr a collector region C, a base region B and an emitter region E, which consist substantially of the input region 1 OA, semiconductor substrate 1 (channel stopper region 28) and guard ring 6, respectively, occur parasitically. According to the present invention, a transistor Tr operable by a predetermined voltage (about 20 V) is formed positively on the front side of a semiconductor layer resistor 10. Especially, forming a transistor Tr by using a guard ring 6 provided on a DRAM does not require an ICmanufacturing process to be changed, and, therefore, it enables the manufacturing cost to be reduced very advantageously.A tapering portion 10B is provided so as to extend from a wider region 10A to a narrower region of the semiconductor layer resistor 10. The tapering portion 10B is used to alleviate the electric field concentration of an unexpected, excessively high voltage in the semiconductor layer resistor 10 and prevent the resistor 10 from being destroyed. A pair of N type semiconductor regions 14 are provided in a spaced manner with a gate electrode G2 therebetween, having a high concentration of impurities, consisting of a source region S2 and a drain region D2 and forming the MISFET 02. As mentioned previously, the semiconductor region 14 forming the drain region D2 is connected electrically with the semiconductor layer resistor 10.A gate electrode G2 is provided on the portion of the main surface of the semiconductor substrate which is between the semiconductor regions 14, and it is used to form the MISFET Q2. This gate electrode (G2) 15 is connected electrically at its one end portion with the semiconductor region 14, which forms the source region S2, through a connecting bore 15A. A wire 16 is provided, one end portion of which is connected electrically with the gate electrode (G2) 15 through a connecting hole 17, and the other end portion of which is connected with earth potential.
n type semiconductor regions 18 are provided on the portions of the main surface of the semiconductor 1 which are on both sides of the gate electrode (G1), having a high concentration of impurities, consisting of a source rgion S1 and a drain region D1 and used to form a MISFET Q,. A wire 19 is provided, one end of which is connected electrically with a semiconductor region 18, which is to form a drain region Da, through a connecting hole 20. A wire 21 is provided one end portion of which is connected electrically with the semiconductor region 18, which is to form a source region Si, through a connecting bore 22. An insulating film 23 is provided between the gate electrodes 13, 15, external terminal 5 and wires 16, 19, 21 so as to separate them from one another electrically.
The operation of Example I of the present invention will now be described on the basis of a typical, parasitically formed transistor Tr with reference to
Figures 2, 3 and 4.
First, the unexpected, excessively high energy, for example, an excessively high voltage of the static electricity, which causes the electrostatic destruction in an external terminal (BP) 5 of an IC, is applied thereto from a certain cause, for example, when the
IC is handled by a person. This unexpected, excessively high voltage is inputted into the semiconductor layer resistor 10 through the connecting hole 11.
When the unexpected, excessively high voltage inputted into the semiconductor layer resistor 10 and the semiconductor region 14, which is to form the drain region D2 of the clamping MISFET #2, has reached a predetermined electric potential (about 20 V) lower than a peak thereof, a part of the unex- pected, excessively high voltage flows from the PN junction between the semiconductor layer resistor 10 or the semiconductor region 14 and semiconductor substrate 1 into the interior of the same substrate 1 through the diode D1. Consequently, the electric potential of the base region B of the transistor Tr increase to cause the transistor Tr to be turned on.
As a result, a part of unexpected, excessively high voltage increasing from a level lower than a peak to a maximum level, and the greater part of the unexpected, excessively high voltage in a level immediately after the peak, which voltage might possibly cause the electrostatic destruction, can be introduced into the guard ring 6 at the input region 1 OA of the semiconductor layer resistor 10. This enables the unexpected, excessively high voltage, which causes the electrostatic destruction to occur, to be reduced by the input region 1 OA, i.e., transistor
Tr and clamping MISFET Q2w The part of the semiconductor layer resistor 10 which does not directly operate as part of the transistor Tr contributes to the turn-on thereof.
In the above description of the operation of the invention, the transistor Tr which parasitically occurs is used as a typical device to which the invention is applied. The present invention will now be described with regard to a punch-through phenomenon occurring between the input region 1 0A and guard ring 6, by using Figures 2, 3 and 4.
First, an unexpected, excessively high voltage which causes the electrostatic destruction is applied to the external terminal. This unexpected, excessively high voltage is inputted into the semiconductor layer resistor 10 through the connecting hole 11.
When the unexpected, excessively high voltage, which has been inputted into the semiconductor layer resistor 10 and the semiconductor region 14 which is to form the drain region D2 of the clamping
MISFET Q2, reaches a predetermined level (about 20
V) of electric potential before reaching a peak thereof, a depletion layer formed in the semiconductor substrate 1 reaches from the PN junction between the input region 1 OA of the semiconductor layer resistor 10 and the semiconductor substrate 1 to the guard ring 6. Therefore, the greater part of the unexpected, excessively high voltage flows into the guard ring 6. From experimentation and research we have ascertained that, when a distance between the input region 10A and guard ring 6 becomes around 10 Fm, the depletion layer is combined by a voltage of around 100 V.Such electrical connection between the input region 10A and guard ring 6 due to the combination of the depletion layer, i.e., a punchthrough phenomenon, enables the unexpected, excessively high voltage, which causes the electrostatic destruction, to be reduced in the input region 10A and clamping MISFET Q2.
The operation of the present invention will be further described.
Figure 5 is a graph for use in describing the concrete effects of Example I of the present invention.
Referring to Figure 5, the axis of ordinates represents the destruction-resisting voltage in the input circuit, which is shown in accordance with an arbitrary scale in which a base value of 1 is a reference rated regular value thereof. The axis of the abscissa representes a base width of the transistor
Tr, i.e., the length L of the opposed edges of the input region 10A and guard ring 6, the length L being shown in accordance with an arbitrary scale in which a base value of 1 is the channel width W of the clamping MISFET Q2 (refer to Figure 3).
As is clear from the data curve in Figure 5, the electrostatic destruction-resisting voltage in the input circuit increases in proportion to the base width of the tra nsistor Tr, i.e., the length L of the opposed edges of the input region 1 OA and guard ring 6. For example, when the length L of the opposed edges of the input region 1 OA and guard ring 6 is set to around 50 - 70 Fm which is equal to the channel width of the clamping MISFET Q2 with a distance therebetween, i.e., the base length of the transistor
Tr set to 40 Fm, the input circuit becomes capable of standing an unexpected, excessively high voltage of around 1000 V.Namely, an electrostatic destructionresisting voltage substantially equal to or not less than a reference rated regular electrostatic destruction-resisting voltage can be obtained. The value of this electrostatic destruction-resisting voltage is 2 - 5 times as high as that in a conventional electrostatic destruction-preventing circuit. Such an excellent effect of the present invention is due to the capability of the input region 1 OA of the semiconductor layer resistor 10 to positively supply an unexpected, excessively high voltage, which causes the electrostatic destruction, to the guard ring 6. This prevents a maximum level of unexpected, excessively high voltage from being inputted directly into the clamping MISFET Q2 through the semiconductor layer resistor 10, so that the destruction strength of the semiconductor layer resistor 10 can be improved.
Namely, this capability of the semiconductor layer resistor 10 enables the destruction strength of the electrostatic destruction-preventing circuit 7 to be improved.
Example 11 Figure 6 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, for use in describing the construction of Example II of the present invention.
Example II is substantially the same as the abovedescribed Example I except that the layout is modified. In particular, the shape of the resistor 10 differs from that of Figure 3, and the elements 5, 13 and 15 are coupled at different locations. Also, it should be noted that the taper portion has only a single taper side 10b.
In Examples I and II, the transistor Tr is formed positively by the regularly-provided guard ring 6 and semiconductor layer resistor 10 to deal with such an unexpected, excessively high voltage that causes the electrostatic destruction. According to this layout, a resistor, a MISFET and a diode can be effectively arranged.
Example Ill Figure 7 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, for use in describing the concrete construction of Example Ill of the present invention.
Referring to Figure 7, nf type semiconductor regions 24 according to Example Ill are spaced at a predetermined distance from a semiconductor layer resistor 10, and which are provided on the main surface portion of a semiconductor substrate 1 so as to extend substantially in parallel with the direction in which the semiconductor layer resistor 10 extends. The substrate potential, earth potential or power source potential is applied to the semiconductor regions 24. Thus, an NPN type lateral transistor
Tr is parasitically formed, in which an input region 10A, a semiconductor substrate 1 and semiconductor regions 24 occur as a collector region C, a base region B and an emitter region E, respectively, in the front portion of the semiconductor layer resistor 10.
As such, the regions 24 are used in place of the guard ring 6 for defining the emitter region of the parasitic transistor Tr. The base width of the transistor Tr, i.e., the length L of the opposed edges of the input region 1 OA of the semiconductor layer resistor 10 and semiconductor regions 24 is set substantially equal to or not less than the channel width of a clamping MISFET Q2 in the same manner as in
Examples I and 11 described above. Voltage is applied to a wire 25 to cause the wire to have the substrate potential, earth potential or power source potential.
The wire 25 is connected electrically with the semiconductor regions 24 through the connecting holes 26. In this embodiment, the semiconductor regions 24 are provided on both sides of the semiconductor layer resistor 10 but only one semiconductor region 24 may be provided on one side thereof. Also, as shown, the input portion 1 OA can effectively begin with the tapered portion 1 OB, if desired. Further, although Figure 7 shows the resistor region 1 Ob as tapering to provide a tapered interface between the region 10 and the regions 24, it should be understood that the region 10 could have a non-tapered edge while the region 24 is tapered to provide the tapered interface between the two regions.
In the transistor Tr in this Example, which occurs parasitically due to the input region 1 OA of the semiconductor layer resistor 10, semiconductor regions 24 and semiconductor substrate 1, the base length of a tapering portion 10B is smaller than those of the other portions (for example about 1/3).
The tapering portion 1 OB make a transistor action of the parasitical transistor formed thereby strong compared with other portions to absorb the energy of the excessively high voltage in the first 1/3 portion of resistor 10. This prever ts the destruction of the resistor 10 by the voltage drop of dissipation of the energy therein when the excessively high voltage is applied to the resistor 10.
On the other hand, thetapering portion 1 0B make it possible to prevent the destruction of the resistor 10 by concentration of current in normal operation.
The strongest portion of electric field is first 1/3 portion of the resistor in normal operation. Accordingly, an unexpected, excessively high voltage of a value recorded before a peak value thereof, an unexpected, excessively high voltage of a peak value and the greater part of an unexpected, excessively high voltage which occurs after the peak value was recorded and could cause the electrostatic destruction can be introduced into the semiconductor regions 24 mainly by the tapering portion 10B.
Namely, an unexpected, excessively high voltage which could cause the electrostatic destruction can be reduced by the transistor Tr and clamping MISFET Q2 in the input region 1 OA, especially, the tapering portion 10B.
The portions of the semiconductor layer resistor 10 other than the tapering portion 1 OB contribute to positively turning-on the transistor Tr.
Example IV
Figure 8 is a plan view of a principal portion of an electrostatic destruction-preventing circuit, for use in describing the construction of Example IV of the present invention, and Figure 9 is a sectional view taken along the line Y-Y in Figure 8.
This Example will be described with reference to an IC provided with a Schottky field-effect transistor (which will hereinafter be called "MESFET") using a semi-insulated substrate, for example, a gallium arsenide IC.
Referring to Figures 8 and 9, the device comprises a semi-insulated substrate for forming an IC thereon.
The circuit includes a MESFET Q1 for forming an input circuit, and a clamping MESFET Q2 for forming an electrostatic destruction-preventing circuit. Voltage is applied to a wire 25A to cause the same to have earth potential or power source potential. The wire 25A is connected electrically with the semiconductor regions 24 through the connecting holes 26A.
A p-type well region 27 is formed in Example IV of the present invention, which is provided so as to include a semiconductor layer resistor 10, a semiconductor region 14 of the clamping MESFET Q2, and the semiconductor regions 24, i.e., the electrostatic destruction-preventing circuit-forming portions.
This well region 27 is used to positively form an NPN type lateral transistor Tr in cooperation with the semiconductor layer resistor 10 and semiconductor regions 24. Voltage is applied to the well region 27 to set the same in a predetermined level of electric potential, i.e., earth potential.
When an unexpected, excessively high voltage, which could cause the electrostatic destruction, is applied to the semiconductor layer resistor 10 in an
IC in which the semiconductor layer resistor is formed on a semi-insulated substrate, a leakage current flowing into the substrate does not substantially occur in the junction between the semiconductor layer resistor and the substrate (unlike the case of a PN junction between a semiconductor layer resistor and a semiconductor substrate where such a leakage current does occur). Instead, the unexpected, excessively high voltage flows as it is in the semiconductor layer resistor.Consequently, in an electrostatic destruction-preventing circuit for an IC using a semi-insulated substrate, especially, the destruction strength of the semiconductor layer resistor and the electrostatic destruction-resisting voltage of the input circuit have, in some cases, low values that do not satisfy the reference rated regular values. However, according to this Example, an unexpected, excessively high voltage can be dealt with by the transistor Tr with occurs parasitically due to the input region 1 OA of the semiconductor resistor 10, semiconductor regions 24 and well regions 27, and the clamping MESFET 02. The reasons why this effect can be obtained are as follows.A part of the unexpected, excessively high voltage of a value recorded before a peak value is attained flows into the well region 27 through the junction between the semiconductor layer resistor 10 and the semiconductor regions 14 which are to form the drain region
D2 of the MESFET 02, and the well region 27. As a result, the electric potential in the well region 27 increases, so that the greater part of an unexpected, excessively high voltage, which could cause the electrostatic destruction, and which has a value before a peak value, a peak value and a value after a peak value, can be discharged into the semiconductor regions mainly by the tapering portion 1 OB.
Namely, the unexpected, excessively high voltage which could cause the electrostatic destruction can be reduced by the transistor Tr in the input region 1 or, especially, tapering portion 1 OB, and the clamping MESFET 02. The portions of the semiconductor layer resistor 10 other than the input region 10A contribute positively to turn on the transistor Tr.
From the foregoing description it can be seen that the present invention provides an IC with an electrostatic destruction-preventing circuit between an external terminal and an input circuit which includes a a lateral transistor operable by an unexpected, excessively high voltage. The circuit has the constituent parts of a semiconductor layer resistor, semiconductor regions (the conductivity type of which is the same as that of the semiconductor layer resistor), spaced at a predetermined distance from each other, and a well region formed in a substrate or a substrate (the conductivity types of which are contrary to that of the semiconductor regions) used to form the semiconductor regions therein to thereby form the lateral transistor.Since an unexpected, excessively high voltage can be reduced by this transistor, the electrostatic destruction-resisting voltage of the input circuit can be improved.
When a clamping element is employed additionally in the electrostatic destruction-preventing circuit, an unexpected, excessively high voltage can be reduced by the lateral transistor and clamping element, so that the electrostatic destructionresisting voltage can be further improved.
When the base width of the lateral transistor is set substantially equal to or not less than the channel width of the clamping element, the electrostatic destruction-resisting voltage can also be improved.
When the lateral transistor is provided in the input portion of the semiconductor layer resistor, an unexpected, excessively high voltage applied to the semiconductor layer resistor can be reduced in the input portion thereof, so that the destruction strength of the semiconductor layer resistor, i.e. the electrostatic destruction-preventing circuit can be improved.
A number of modifications of the invention described in the above referred to examples is possible. For example, the semiconductor regions formed in each Example may also consist of reverse conductivity type semiconductor regions. Although it is preferable to use a guard ring, another semiconductor region may be provided instead thereof to achieve the present invention. It is needless to say that the semiconductor regions may be formed not only by the termal diffusion but also by the ion implantation. Also, it is to be understood that the invention is not limited to use with any particular input circuitry since it can be applied in any situation where reduction of an unexpected, excessively high input voltage will be useful to avoid damage to an input circuit. Further, although the foregoing description has been directed to excessively high voltages occurring from electrostatic sources, it is to be understood that the invention could also be useful to prevent destruction from other unexpected, excessively high voltages such as malfunctioning in other circuitry connected to the input pads or surges in an input signal caused from other reasons.
Claims (26)
1. A semiconductor integrated circuit device formed in a semiconductor substrate having a first conductivity type and provided with a high voltage destruction-preventing circuit which includes:
(a) a first semiconductor region of a second conductivity type having one end portion connected electrically with an external terminal and the other end portion connected electrically with a field-effect transistor which forms an input circuit for an integrated circuit; and
(b) a second semiconductor region of a second conductivity type provided in said semiconductor substrate and spaced at a predetermined distance from said first semiconductor region,
wherein a portion of predetermined length of an edge of said second semiconductor region is opposed to and substantially parallel to an edge of said first semiconductor region to provide a spaced interface having said predetermined length between said portion of said edge of said second semiconductor region and said edge of said first semiconductor region to form a lateral protection transistor comprised of said first and second semiconductor regions and a portion of said substrate located in said spaced interface to absorb a portion of an unexpected voltage having a voltage level higher than a normal operation voltage of said input circuit.
2. A semiconductor integrated circuit device according to claim 1, wherein said high voltage destruction-preventing circuit further comprises a clamping element coupled between said first semiconductor region and said input step circuit.
3. A semiconductor integrated circuit device according to claim 2, wherein said clamping element comprises an insulated gate type field-effect transistor having parameters set at predetermined values to clamp said unexpected voltage having a voltage level higher than the normal operating voltage range of the input circuit.
4. A semiconductor integrated circuit device according to claim 3, wherein said predetermined length is substantially equal to or greater than a channel width of said clamping element.
5. A semiconductor integrated circuit device according to claim 1, wherein said second semiconductor region is provided on the side of one end portion of said first semiconductor region.
6. A semiconductor integrated circuit device according to claim 1, wherein said second semiconductor region comprises a guard ring formed in said substrate to surround said semiconductor integrated circuit device.
7. A semiconductor integrated circuit device according to claim 1, wherein said first semiconductor region has a first portion coupled directly to said external terminal and a second portion coupled between said first portion and said field-effect transistor of said input circuit, wherein said predetermined length for said spaced interface is formed by an edge of said first portion which faces toward said second semiconductor region.
8. A semiconductor integrated circuit device according to claim 7, wherein a longitudinal axis of said second portion is substantially perpendicular with a longitudinal axis of said first portion and connected to said first portion to form a substantially
T-shaped intersection with a side of said first portion which is opposite to said edge of said first portion which faces toward said second semiconductor region.
9. A semiconductor integrated circuit device according to claim 8, wherein said second portion includes at least one tapered area which tapers from a point of intersection of said second portion with said first portion to a predetermined point along the length of said portion so that said second portion has its greatest width at said point of intersection with said first portion.
10. A semiconductor integrated circuit device according to claim 8, wherein said second semiconductor region comprises a guard ring formed in said substrate to surround said semiconductor integrated circuit device.
11. A semiconductor integrated circuit device according to claim 7, wherein said first and second portions of said first semiconductor region have longitudinal axes which are substantially parallel to one another, and wherein an edge of said second portion facing said second semiconductor region is spaced further from said second semiconductor region than said edge of said first portion which faces said second semiconductor region.
12. A semiconductor integrated circuit device according to claim 11, wherein said second semiconductor region comprises a guard ring formed in said substrate to surround said semiconductor integrated circuit device.
13. A semiconductor integrated circuit device according to claim 1, wherein a first portion of said edge of said first semiconductor region is substantially parallel to said portion of predetermined length of said edge of said second semiconductor region, and wherein a second portion of said edge of said first semiconductor region tapers toward said portion of predetermined length of said edge of said second semiconductor region.
14. A semiconductor integrated circuit device according to claim 1, wherein said portion of said predetermined length of said edge of said second semiconductor region includes an area which tapers toward said edge of said first semiconductor region which faces said edge of said second semiconductor region.
15. A semiconductor integrated circuit device according to claim 1, wherein said semiconductor substrate comprises a semi-insulating substrate, and wherein said high voltage destruction-preventing circuit is formed within a well region formed in said semi-insulating substrate.
16. A semiconductor integrated circuit device according to claim 15, wherein said semi-insulating substrate is comprised of GaAs.
17. A semiconductor integrated circuit device according to claim 15, wherein said input circuit is formed in said semi-insulating substrate outside of said well region.
18. A semiconductor integrated circuit device according to claim 17, wherein said field-effect transistor of said input circuit comprises a Schottky gate type field-effect transistor, and wherein other end portion of said first semiconductor region is formed to be electrically connected to a gate electrode of Schottky gate type field-effect transistor.
19. A semiconductor integrated circuit device according to claim 1, wherein said other end portion of said first semiconductor region is connected with a gate electrode of said field-effect transistor.
20. A semiconductor integrated circuit device formed in a semiconductor substrate having a first conductivity type and provided with a high voltage destruction-preventing circuit which includes:
(a) a resistor formed of a first semiconductor region of a second conductivity type having one end portion connected electrically with an external terminal and the other end portion connected electrical- ly with a gate electrode of an insulated gate type field-effect transistor which forms an input circuit for an integrated circuit; and
(b) a second semiconductor region of a second conductivity type provided in said semiconductor substrate and spaced at a predetermined distance from said first semiconductor region,
wherein a portion of predetermined length of an edge of said second semiconductor region is opposed to and substantially parallel to an edge of said first semiconductor region to provide a spaced interface having said predetermined length between said portion of said edge of said second semiconductor region and said edge of said first semiconductor region to form a lateral protection transistor having one of an emitter or a collector comprised of said resistor, a base comprised of a portion of said substrate located in said spaced interface and the other of said emitter or collector comprised of said second semiconductor region to absorb a portion of an unexpected voltage having a voltage level higher than a voltage which would destroy a gate insulator film of said gate electrode.
21. A semiconductor integrated circuit device according to claim 20, wherein said lateral transistor is parasitic.
22. A semiconductor integrated circuit device according to claim 20, wherein said second semiconductor region comprises a guard ring formed in said substrate to surround said semiconductor integrated circuit device.
23. A semiconductor integrated circuit device according to claim 20, wherein said second semiconductor region is connected to a fixed potential.
24. A semiconductor integrated circuit device according to claim 23, wherein said second semiconductor region comprises a guard ring formed in said substrate to surround said semiconductor integrated circuit device.
25. A semiconductor integrated circuit device according to claim 1, wherein said second semiconductor region is connected to a fixed potential.
26. A semiconductor integrated circuit device constructed substantially as herein described with reference to any one of the examples given and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236132A JPS60128653A (en) | 1983-12-16 | 1983-12-16 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8431596D0 GB8431596D0 (en) | 1985-01-30 |
| GB2151846A true GB2151846A (en) | 1985-07-24 |
Family
ID=16996229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08431596A Withdrawn GB2151846A (en) | 1983-12-16 | 1984-12-14 | A high voltage destruction-prevention circuit for a semiconductor integrated circuit device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS60128653A (en) |
| KR (1) | KR850005155A (en) |
| GB (1) | GB2151846A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225586A1 (en) * | 1985-12-03 | 1987-06-16 | SGS MICROELETTRONICA S.p.A. | An overvoltage protection circuit for an integrated MOS device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| US8069817B2 (en) * | 2007-03-30 | 2011-12-06 | Lam Research Corporation | Showerhead electrodes and showerhead electrode assemblies having low-particle performance for semiconductor material processing apparatuses |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1337220A (en) * | 1971-12-09 | 1973-11-14 | Ibm | Monolithic entegrated circuit |
| GB2090701A (en) * | 1980-11-19 | 1982-07-14 | Ates Componenti Elettron | Improvements in or relating to input protection for MOS integrated circuits |
| GB2133926A (en) * | 1982-11-18 | 1984-08-01 | Nec Corp | Protection circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5380A (en) * | 1976-06-23 | 1978-01-05 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6034824B2 (en) * | 1979-05-03 | 1985-08-10 | 三菱電機株式会社 | MOS field effect semiconductor device |
| JPS5640272A (en) * | 1979-09-10 | 1981-04-16 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1983
- 1983-12-16 JP JP58236132A patent/JPS60128653A/en active Granted
-
1984
- 1984-12-06 KR KR1019840007685A patent/KR850005155A/en not_active IP Right Cessation
- 1984-12-14 GB GB08431596A patent/GB2151846A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1337220A (en) * | 1971-12-09 | 1973-11-14 | Ibm | Monolithic entegrated circuit |
| GB2090701A (en) * | 1980-11-19 | 1982-07-14 | Ates Componenti Elettron | Improvements in or relating to input protection for MOS integrated circuits |
| GB2133926A (en) * | 1982-11-18 | 1984-08-01 | Nec Corp | Protection circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225586A1 (en) * | 1985-12-03 | 1987-06-16 | SGS MICROELETTRONICA S.p.A. | An overvoltage protection circuit for an integrated MOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0530073B2 (en) | 1993-05-07 |
| KR850005155A (en) | 1985-08-21 |
| JPS60128653A (en) | 1985-07-09 |
| GB8431596D0 (en) | 1985-01-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |