JPS60128653A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve capacility to withstand statics-induced destruction and to augment physical strength to resist destruction under excessive voltages by a method wherein a semiconductor region separated a specified distance from a first semiconductor region constituting a resistor and a second semiconductor region similar in conductivity to the first semiconductor region are provided in a semiconductor substrate. CONSTITUTION:A P<-> type semiconductor substrate 1 constituted of single crystal Si containing an impurity of low concentration constitutes a DRAM. A memory array 2 that is a line-up of a plurality of memories whose important components are MISFETs performs the memorizing function for the DRAM. External electrodes (bonding pads) 5 are located along the circumference of the substrate 1, receiving signals from outside that will activate the inner circuits of the DRAM and outputting signals generated inside the DRAM. A guard ring 6, which is an n<+> type semiconductor region of a high impurity concentration, located along the outermost periphery of the substrate 1, whereto a substrate, ground or power source potential is applied, arrests unnecessary minority carries generated chiefly inside the substrate 1.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a destruction prevention technique for preventing aging circuit elements from being destroyed by unexpected excessive energy, and in particular, to a semiconductor integrated circuit device. (hereinafter referred to as IC)
The present invention relates to effective technology that can be applied to prevent electrostatic discharge damage.

[Background technology] Insulated gate field effect transistor (hereinafter referred to as MI 5F)
ET (Metal 1nsulator Sem1c
onductorField Effect Tran
In an IC that uses a sistor] as the main component of an integrated circuit, the gates that make up the MISFET, which is the input stage circuit of the integrated circuit, are affected by unexpected excessive energy (voltage) caused by human handling. In order to prevent breakdown of the insulating film (hereinafter referred to as electrostatic breakdown), external terminals (to which unexpectedly excessive energy is applied) must be
An electrostatic damage prevention circuit is provided between the input stage circuit (the bonding pad) and the input stage circuit. This electrostatic damage prevention circuit includes a diffusion layer resistor to dampen unexpected overvoltage that may cause electrostatic damage applied to external terminals, and a diffusion layer resistor to release the unexpected large energy into the semiconductor substrate. It is common to use a clamp MISFET for this purpose.

The clamping MISFET has its source region and gate electrode electrically connected to a ground potential, and the surface breakdown or Zener breakdown that occurs at the pn junction between the drain region and the semiconductor substrate in the channel region causes the expected It clamps excessive voltages that may occur, and is formed in the same manufacturing process as the MISFETs that make up the integrated circuit.
Its demand is extremely high. Further, the diffusion layer resistance also has a parasitic diode connected to the semiconductor substrate.

Because they are formed in the same manufacturing process as the source and drain regions of MISFETs constituting the integrated circuit, their demand is extremely high.

In such a destruction prevention circuit, the clamp M]'5
Compared to FETs, the diffusion layer resistance provided in the front stage is much more easily destroyed (Japanese Patent Laid-Open No. 101283/1983).
. This mainly relies on the clamp J (41SFET) to absorb unexpected excessive energy that may cause electrostatic damage, so a large current flows through the diffusion layer resistor in the previous stage (external terminal side). The present inventor considers that the destruction will occur by flowing first.

The present inventor has proposed that an input stage circuit connected to a destruction prevention circuit having a diffusion layer resistance close to a diffusion layer connected to a power supply voltage or a ground potential is an input stage circuit connected to another destruction prevention circuit. We discovered that the breakdown voltage is about 2 to 5 times higher than that of the diffusion layer resistor, and furthermore, we found that the diffusion layer resistor and the adjacent diffusion layer are broken when the length of the side facing them is approximately parallel (hereinafter referred to as the opposing length). I discovered the fact that withstand pressure depends on the pressure.

[Purpose of the invention]

An object of the present invention is to provide an IC equipped with an electrostatic breakdown prevention circuit that can improve the electrostatic breakdown voltage of the integrated circuit against unexpected overvoltage.

Another object of the present invention is to provide an IC equipped with an electrostatic breakdown prevention circuit that can improve the breakdown strength of the electrostatic breakdown prevention circuit against unexpected overvoltage.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, when there is an open connection between the external terminal and the input stage circuit of the integrated circuit,
In an IC equipped with a destruction prevention circuit including a resistor and a clamping MI8FET, the fourth semiconductor region is separated from a first semiconductor region constituting the resistor by a predetermined distance 1li1f in a semiconductor substrate; By providing a second semiconductor region of the same conductivity type, the semiconductor substrate and the first. By providing a parasitic lateral transistor formed in the second semiconductor region, and further making the opposing length of the first and second semiconductor regions equal to or more than the channel width of the clamping MI8FET,
The purpose is to promptly and reliably reduce unexpected excessive voltages that may cause electrostatic damage.

The present invention will be described in detail below along with examples. In addition, [Example ■], [Example ■], and [Example 111]
is an IC constituted by a semiconductor substrate made of silicon crystal, especially a dynamic random access memory (hereinafter referred to as DRAM).
m AccCss Memory)],
Example (2)] will be explained using an IC constituted by a semi-permanent substrate made of gallium arsenide (QAAs).

In all the figures, parts having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted.

[Example ■]

FIG. 1 is a schematic diagram of a DRAM for explaining [Example 2] of the present invention, as well as [Example 2] and [Example 2], which will be described later.

In FIG. 1, reference numeral 1 denotes a P-type semiconductor substrate made of silicon single crystal and having a low impurity concentration.
It is for configuring. Reference numeral 2 denotes a memory array in the center of the semiconductor substrate 1, in which a plurality of memory cells whose main constituent elements are MISFETs are arranged in rows and columns, and is used to configure the memory function of the DRAM. . 3 and 4 are peripheral circuits provided on the upper and lower parts of the semiconductor substrate 1. 5 is an external terminal (ponding pad) provided on the periphery of the semiconductor substrate 10, and is connected to the internal circuit FM! of the DRAM. An operation signal for operating the DRAM is applied from the outside, and an output signal from the internal circuit of the DRAM is output to the outside. This external terminal 5 is exposed to unexpected excessive energy (voltage) that may cause electrostatic damage to the input stage circuit electrically connected to the external terminal 5.
There is one thing that happens when . 6 is the most peripheral part of the semiconductor substrate 1, has a high impurity concentration, and is not applied to the substrate potential, the ground Irb7 or the power supply Ti,
This is a guard ring consisting of a type semiconductor region, and is mainly used to capture unnecessary minority carriers generated inside the half-2 external body group 1.

FIG. 2 shows [Example ■] of the present invention, as well as [Example ■] and [Example III] to be described later.
) is a diagram showing a destruction prevention circuit provided in the RAM.

In FIG. 2, BP is the external terminal 5 mentioned above. ,
Q, ke I) It is also an n-channel MIS'FET provided to configure the input stage circuit of the RAM.

Sl is the source region 1 of M I S F E T Q +
DI is MI S F B 'I Q + ') t'
1' (71iri area, G Ii'j: M I S
This is the gate electrode of FICTQ. 7 is an external terminal (
5) An electrostatic breakdown prevention circuit according to the present invention provided between BP and the gate electrode G1 of M I S F B T Q + .

This prevents electrostatic breakdown in the gate electrode G1 of the MISFE'rQ when unexpected excessive energy that would cause breakdown, such as excessive voltage due to static electricity, is applied to the external terminal (5) BP. It is for. R4 is a resistor made of an n-type semiconductor region, for example, a diffusion layer, in order to dampen unexpected overvoltage, and DI is a resistor R1 mainly made of the n-type diffusion layer and MIS, which will be described later.
Drain region D2 consisting of an n-type semiconductor region of FETQ2
J is parasitically provided by the pn junction between
diode, Q2 is for unexpected overpressure, clamp I] channel MISFE'l', S
2 is the ground potential GNT, together with the gate electrode G2)
J is the source region of MISFETQ2 connected to J, and D2 is the drain region of MISFETQ2. A transistor whose collector region C is connected to the front part of the resistor R1, whose emitter region E is connected to a terminal V at the substrate potential, ground potential, or power supply potential, and whose base region B is a semiconductor transistor. It is connected to the board 1. In the transistor Tr, when a predetermined potential is applied to the collector region C, the potential of the base region B increases, and the transistor 1'riO
VC is set to do N. This transistor Tr is
Both MIS FE 71+ C2 are designed to reduce unexpected excessive voltage. The base region B is
The external terminal (5) BP and the gate electrode G are connected via a parasitic resistance R2 caused by the semiconductor substrate 1 and a diode D1.

It is connected to a certain part between the tongues. C is a capacitor generated parasitically on the semiconductor substrate 1, one end of which is connected to the semiconductor substrate 1, and the other end a terminal with a predetermined potential.
It is connected to 2. The capacitor C is used to alleviate fluctuations in the first voltage applied to the semiconductor substrate l by a pulse signal.

DII is a diode that is generated parasitically by the pn junction between the emitter region Efn type semiconductor region and the semiconductor substrate 1 by providing it in the emitter region Efn type semiconductor region. vs is a terminal having the same potential as Vl.

Next, the specific structure of the electrostatic damage prevention circuit shown in FIG. 2 will be explained.

FIG. 3 is a plan view showing the main parts of the electrostatic breakdown prevention circuit for explaining the specific construction of Example (1) of the present invention, and FIG. It is a cross-sectional view at -X. In addition, in FIG. 2 and the plan views after the first part, the insulating film to be provided between each wiring layer is not shown in order to make the drawings easier to see.

In FIGS. 3 and 4, 8 is a field insulating film provided on the main surface of the semiconductor substrate l between semiconductor elements;
This is for electrically isolating semiconductor elements. 9
is an insulating film provided on the main surface of the semiconductor substrate 1 on which a semiconductor element is to be formed, and is mainly used to constitute the gate insulating film of the MI 8 FET. 10 is the gate electrode G of MI8FETQ, which constitutes the input stage circuit with the external terminal 5;

This is a diffusion layer resistor (R1) according to [Embodiment 2] of the present invention, which is provided on the main surface of the semiconductor substrate 1 between the substrate 1 and the semiconductor substrate 1, and is made of an n+ type semiconductor region. This diffusion layer resistor 10 has one end connected to the outside Qj,'+75 through the connection hole 11, and the other end connected to the outside Qj,'+75 through the connection hole 12.
Gate electrode (Gl) 13''f of FETQ+
MISI continuously integrated with the diffusion layer resistor 10
The drain region D2 of ETQ2 is electrically connected to the drain region D2. Diffusion layer f (11 on a part of the resistor 10, on the external terminal 5 side, an input stage area 10A with an opposing length of L approximately parallel to the guard ring 6, sandwiching the two hot water substrates 1) As a result, an input stage region 10A is formed before and after the diffusion layer resistance]0.

collector region C2 semi-η7 body substrate 1 and base region B?
and the guard ring 6 as the mitter area E.
(J'J t?2 is generated so that the type II didecyl transistor name Tr is composed of two).

The present invention thus provides 41. Transistor Trf that operates by pressure: , diffusion layer 11 (
In the front stage of the resistor 1.0, actively create 4'F'l (this is done with ~.Specially, install +'-, t+ card ring 6 in the DRAM) and transistor 11441 strong ν, -no word, ■C's sword c, 1! Because it is not necessary to change the entire manufacturing process, it is extremely advantageous in terms of cost, etc. 1OBij diffusion layer provided from the wide area of the resistance 1o to the sandwich area. This is a tapered portion, which is intended to alleviate the electric field concentration in the diffusion layer resistance lo caused by an unexpected overvoltage, and to prevent destruction of the diffusion layer resistance 1o. A pair of n+ type semiconductor regions having a high impurity concentration are provided on the main surface of the semiconductor substrate 1, and serve as a source region s2 and a drain region, and constitute MISFET C2.As described above, The semiconductor region 14 serving as the drain region D2 is electrically connected to the diffusion layer resistor 1o. 15 is a gate electrode G2 provided on the main surface of the semiconductor substrate 1 between the semiconductor regions 14, and constitutes the MISFET C2. This gate insulating film (G2) 1
5, one end thereof is connected to the source region s through the connection hole 15A.
It is electrically connected to the semiconductor region 14 serving as No. 2.

Reference numeral 16 denotes a wiring, one end of which is electrically connected to the gate insulating film (G2) 15 via a connection hole 17, and the other end connected to the ground potential. Reference numeral 18 denotes an n+ type semiconductor region having an extremely high impurity concentration, which is provided in the main part of the semiconductor substrate 1 on both sides of the gate electrode (G1), and serves as a source region S and a drain region 1).
This is for configuring S 1” ETQ.19
is a wiring, one end of which is electrically connected to the drain region and the semiconductor region 18 via the 5i8 hole 20i. Reference numeral 21 denotes a wiring, one end of which connects to the semiconductor g1 region 1 which becomes the source region S1 via the connection hole 22.
8 and is electrically connected. 23 is the gate electrode 13.
This is an insulating film provided between the external terminal 5 and the wirings 16, 19, and 21 to electrically isolate them.

Next, regarding the specific operation of [Embodiment ■] of the present invention,
Figure 2 1. An explanation will be given using a parasitic transistor Tr as a model using FIGS. 3 and 4.

Due to unfreezing and other causes such as human handling, an unexpected high I/RJ energy, such as a large voltage caused by static electricity, is applied to the external terminal (BP) 5 of the IC, which can cause damage. This unexpected overvoltage is input to the diffusion layer resistor 10 via the connection hole 11. Drain 9 region D2 of diffusion layer resistor 10 and clamp MI8FETQ
When the unexpected overvoltage input to the semiconductor region 14 reaches a predetermined potential before reaching its maximum peak value, the diffusion layer resistance 10, the semiconductor region 14, and the semiconductor substrate 1
A part of the unexpected excessive voltage flows into the semiconductor substrate 1 from the pn junction with the semiconductor substrate 1 through the diode D1. This inflow causes the potential of the base region B of the transistor Tr to rise, turning on the transistor DA Illr. As a result, most of the unexpected overvoltage that reaches the maximum peak value before the maximum peak value of the unexpected overvoltage and causes electrostatic discharge damage after the maximum peak value is absorbed by the diffused layer resistance 1.
In the input stage region 10A section of 0, it is possible to flow into the guard link 6. As a result, unexpected excessive voltage that may cause electrostatic discharge damage can be reduced by the input stage region 10A, that is, the transistor Tr and the clamping MI8FBTQt. Discarded transistor Tr
The other diffusion layer resistors 10 contribute to turning on the transistor Tr.

The above operation was explained using the parasitic transistor Tr as a model.

3rd [Using i41 and FIG. 4, input stage area 10A
The punch-through phenomenon that occurs between the guard ring 6 and the guard ring 6 will be explained as a model.

Sunzu, outside? 71 (An excessive η°C pressure that would cause damage to the terminal (BP) 5) is applied. This unexpected excessive pressure is input to the diffusion layer resistor 10 through the connection hole ll. MIS for diffusion layer resistor 10 and clamp
Semiconductor region 14 which becomes the drain region 1) of FETQy
Before the unexpected excessive voltage input to the semiconductor substrate 1 reaches its maximum peak value, that is, when it reaches a predetermined potential, the unexpected excessive voltage input to the semiconductor When the depletion layer formed in the substrate 1 reaches the guard ring 6, most of the unexpected overvoltage flows into the guard ring 6. The inventor has proposed that the input stage area 10
It has been confirmed that when the distance between A and the guard ring 6 is about 10 [μm], the depletion layer is coupled by a voltage of about 100 [V]. Due to such an electrical connection between the input stage region 10A and the guard link 6 due to the coupling of the depletion layer, that is, the punch-through phenomenon, there is a possibility that electrostatic damage may occur in the input stage region 10A and the clamping MISFET Qt. It is possible to reduce excessive voltage.

The effects of the present invention will be further explained.

FIG. 5 is a diagram for explaining all the specific effects of [Embodiment 2] of the present invention.

In FIG. 5, the vertical axis shows the breakdown voltage in the input stage circuit, and is shown on an arbitrary scale with the standard value being 1.

The horizontal axis is the base width of the transistor Tr, that is, the opposing length (r) between the input stage region 10A and the guard ring 6, and is shown on an arbitrary scale with the channel width (5) of the clamping MISFBTQ2 as 1. Yes (3rd
Clothes for medical rounds).

As is clear from the data curve shown in FIG. 5, as the base width of the transistor Tr, that is, the opposing length between the input stage region 10A and the guard ring 6 increases, the electrostatic breakdown voltage in the input stage circuit improves. . For example, the opposing length between the input stage area 10A and the guard ring 6 (1? 50 to 70
[μm], and the distance between the rays, that is, the base length of the transistor Tr, is 40 [μm], then the input stage circuit can cope with an unexpected overvoltage of about l 000 [V]. . In other words, the standard value and the same sum y
[Or, static ↑n on fl, 9, breakdown voltage can be obtained. This result shows that the electrostatic breakdown voltage is 2 to 5 times higher than that of conventional electrostatic breakdown prevention circuits1.
, this kind of effect can be obtained by adding 1.
i' This is because the input stage region 10A of the IIE resistor 10 actively supplies the card link 6 with an unexpected excessive voltage that would cause electrostatic damage 91. According to this, the maximum peak value of the unexpected overvoltage is directly caused by the diffusion layer resistance 10
MISFBTQ for clamping via 17, [no input is required, and the breakdown strength of the diffusion layer resistor 10 is improved]
Two can be done. That is, the breakdown strength of the electrostatic breakdown prevention circuit 7 can be improved.

[Example ■]

FIG. 6 is a plan view showing a main part of an electrostatic breakdown prevention circuit for explaining the specific structure of [Embodiment 2] of the present invention.

This embodiment is substantially the same as the above-mentioned [Embodiment 1], but the layout has been changed.

In [Example ■] and [Example ■], by using a normally provided guard link 6 and actively constructing a transistor Tr with the guard ring 6 and the diffusion layer resistor 10, it is possible to prevent electrostatic damage from occurring. It is designed to handle unexpected overvoltage. Further, according to this layout, the resistor, MISFET, and diode can be effectively arranged.

[Embodiment III] FIG. 7 is a plan view showing a main part of an electrostatic breakdown prevention circuit for explaining the specific structure of [Embodiment 111] of the present invention.

In Fig. 237, 24 is a predetermined distance C from the diffusion layer resistance 10.
The front corner is 1F, and Sakae conductor 7 is located approximately parallel to the direction of its extension.
．． Example 111 of the present invention provided on the main surface of the +- plate l
] is an n+ type semiconductor region. This semi-circular body extension area 2
4 is applied with a substrate potential, a ground potential, or a power supply potential. As a result, an npn type lateral transistor Tr is formed in the front stage of the diffusion layer resistor 10, which is parasitically generated with the input stage region 10A as the collector head C2, the semiconductor substrate 1 as the pace region B, and the semiconductor region 24 as the emitter region E. It is now possible to do so. The base width of this transistor Tr, that is, the opposing length between the input stage region 10A of the diffusion layer resistor 1d and the semiconductor region 24 (J→ is determined from the above-mentioned [Actual Mli Example I] and [Implementation Example III])
Similarly, the channel width of the MI8FETQ2 for clamping is about the same or larger. Reference numeral 25 indicates a position where the substrate potential, ground potential, or power supply is applied, and is electrically connected to the respective semiconductor region 24 through the connection hole 26. In this embodiment, Although the semiconductor regions 24 are provided on both sides of the diffusion layer resistor 10, they may be provided only on one side.

According to this embodiment, the input stage region 10A of the diffusion layer resistor 10
In the transistor Tr that is parasitically generated by the semiconductor region 24 and the semiconductor substrate 1, the base length in the tapered portion 10B is shorter than other parts, so that the maximum peak value of the unexpected overvoltage increases even before the maximum peak value. In addition, most of the unexpected heavy pressure of jD that may cause electrostatic discharge damage after the maximum peak value can be mainly channeled into the semiconductor region 24 by the Taber portion 10B. That is, unexpected excessive voltage that may cause static electricity or breakdown can be reduced by the transistor Tr and the clamping λ4ISFET Q2 in the input stage region 10A, particularly in the tapered portion 10B.

That's too bad, the diffusion layer resistor 10 other than the tapered portion 10B is very effective in actively turning on the transistor Tr.

[Example ■]

FIG. 8 is a plan view showing the main parts of the electrostatic breakdown prevention circuit for explaining the specific structure of [Embodiment 2] of the present invention, and FIG. FIG.

This example describes a Schottky gate field effect transistor (hereinafter referred to as MES) using an insulating substrate.
1. ] Il+), for example, gallium arsenide 1C will be explained.

7Q B g, and in FIG. 9, one is a semi-insulating fast board, and is for forming an IC.

Q, is ME8FET for configuring the input stage circuit, Q2
is an MIi for clamping to configure an electrostatic damage prevention circuit.
It is an SFET. 25A is ground potential or 1! 1. This is a wiring that is applied to the bottom level, and is electrically connected to each of the semiconductor regions 24 through the connection holes 26A.

27 is a p-type well region according to [Embodiment 2] of the present invention, which covers the semiconductor region 14 and the semiconductor region 24 of the diffusion layer resistance 10° clamp MESFETQ, that is, the electrostatic damage prevention circuit component. It is provided. This well region 27 includes the diffusion layer resistor 10 and the semiconductor region 2.
4, it is used to actively constitute an npn type lateral transistor Tr. In addition, well area 2
7 is applied to the 5th place of a given city.

When a diffused layer resistor is configured on a semi-insulating substrate, if an unexpected excessive voltage that causes electrostatic breakdown is applied to the diffused layer resistor, the diffused layer resistor will be damaged at the junction between the diffused layer resistor and the semi-insulating substrate. Unlike a pn junction between a resistor and a semiconductor substrate, there is almost no leakage current into the semiconductor substrate, and unexpected overvoltage flows directly through the diffused layer resistor. For this reason, the electrostatic breakdown prevention circuit of an IC using a semi-insulating substrate, especially the breakdown strength of the diffusion layer resistor and the electrostatic breakdown voltage of the input stage circuit, exhibit a value so low that it cannot satisfy the standard specification value. There are cases. However, according to this embodiment, it is possible to cope with an unexpected overvoltage by the transistor Tr and the clamping ME8FETQL that are parasitically generated by the input stage region 10A of the diffusion layer resistor 10, the semiconductor region 24, and the well region 27. I can do it. This means that a part of the unexpected overvoltage before the maximum peak value is caused by the diffusion layer resistance 10 and the drain region D2 of the MESFET Qt, the half 3, the main body f1 14 and the well region 27. It flows into the well region 27 via the pn junction. As a result, the potential of the well region 27 increases, and most of the unexpected overvoltages that cause electrostatic damage from before the maximum peak value of the unexpected overvoltage to the maximum peak value and further after the maximum peak value. The semiconductor region 2 is mainly formed by the tapered portion 10B.
It can be passed to 4. In other words, the input stage region 10A,
Particularly, the pressure can be reduced by the transistor Tr and the clamp ME S F E l''Q2 in the tapered portion 10B.

1 degree, 10 diffusion layer resistors other than input stage area 10A, 5
Use a lot of power to turn on the transistor Illr at 4+-i (-r l/).

[Eri-]

In an IC in which one destruction prevention circuit is installed between the external n/i element and the input stage circuit, the destruction prevention circuit has a diffusion layer resistor composing it and a predetermined distance of the same conductivity type as the diffusion layer resistance. A semiconductor region configured with a conductivity opposite to them,
The substrate for configuring them in a mold or a well region provided in the substrate makes it possible to provide lateral transistors that operate with unexpectedly high voltages. As a result, unexpected excessive voltage can be reduced, and the static breakdown voltage of the input stage circuit can be improved.

Further, by using a clamping element in the breakdown prevention circuit, unexpected excessive voltage can be reduced by the lateral transistor and the clamping element, so that the electrostatic breakdown voltage can be further improved.

Further, by making the base width of the lateral transistor equal to or larger than the channel width of the clamping element, breakdown voltage can be improved.

Furthermore, by providing a lateral transistor at the input stage of the diffused layer resistor, unexpected excessive voltage applied to the diffused layer resistor can be alleviated at the input stage. The breaking strength of the prevention circuit can be improved.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in each embodiment, each semiconductor region can be formed with opposite conductivity types. Also, although it is preferable to use a guard ring, other semiconductor regions may alternatively be provided to achieve the present invention. Further, the method for forming the semiconductor region is not limited to thermal diffusion, and of course, ion implantation may also be used.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of I) RAM for explaining [Example ■], [Example ■], and (Example 111) of the present invention, Figure m2 is [Example ■] of the present invention, [Example I] and [Example Ill E] A diagram showing an electrostatic damage prevention circuit suitable for DR and AM for complete explanation, FIG. 3 is a specific diagram of [Example I] of the present invention. FIG. 4 is a cross-sectional view taken along the line X-X in FIG. 3, and FIG. FIG. 6 is a plan view showing the main parts of an electrostatic breakdown prevention circuit for explaining the specific structure of [Embodiment 2] of the present invention. FIG. 7 is a plan view showing the main parts of the static and destruction prevention circuit for explaining the specific structure of [Embodiment 2] of the present invention, and FIG. 8 is [Embodiment 2] of the present invention. FIG. 9 is a plan view showing the main parts of the electrostatic damage prevention circuit for explaining the specific structure of the circuit. FIG. In the figure, 1... semiconductor substrate, 1A... semi-insulating substrate,
2...Memory array, 3, 4...Peripheral circuit, 5...
・External terminal, 6... Guard ring, 7... Electrostatic breakdown prevention circuit 8... Field insulating film, 9, 23... Insulating film, 10... Diffusion layer resistance, IOA... Input Kadan Tsukuda area, 10'B... Taper part, 11.12, 15A, 17
, 20, 22, 26° 26A...↑zu, drill hole, 13
．． 15...Ge-1 electrode, 14°18.24-...semiconductor region, 16,19,21,25°25A...wiring, 27...well region, Q,...MISF E T
or N E 8 Fxv T, Q2... MI S I” 14 T or ME8F for clamp
ET, :R+. 1L...Resistor, Tr...Transistor. Fig. 1 Fig. 2 Fig. 5 Fig.

Claims (1)

[Claims] 1° Second conductor T7f provided on the first conductor type semiconductor substrate
, the first half-dedicated region of the mold is electrically connected to an external terminal at one end thereof, and electrically connected to the gate electrode of an insulated gate field effect transistor forming an input stage circuit of the integrated circuit at the other end thereof. In a semiconductor integrated circuit device equipped with an electrostatic breakdown prevention circuit connected to the semiconductor substrate, a first half paddle is provided in the semiconductor substrate, the first half paddle is spaced apart from the first semiconductor region by a predetermined distance, and is substantially parallel to the body region. A semiconductor integrated circuit device equipped with an electrostatic damage prevention circuit which is a city-wide feature and includes a second semiconductor region of a second conductivity type whose opposing sides have a predetermined length. 2. The electrostatic breakdown prevention circuit is characterized in that a clamping element made of an insulated gate field effect transistor is provided between the first semiconductor region and the input stage circuit for clamping unexpected excessive voltage. 'I':j A semiconductor integrated circuit device comprising the electrostatic damage prevention circuit according to claim 1. 3. The electrostatic breakdown prevention circuit is provided with a clamping element consisting of an insulated gate field effect transistor for clamping unexpected excessive voltage between the first semiconductor region and the input stage circuit; Electrostatic damage according to claim 1, characterized in that the opposing sides of the first semiconductor region and the second semiconductor region have a length equal to or longer than the channel width of the clamping element. A semiconductor integrated circuit device equipped with a prevention circuit. 4. A semiconductor integrated circuit device equipped with an electrostatic breakdown prevention circuit according to claim 1, wherein the second semiconductor region is provided on one end side of the first semiconductor region. 5. A Schottky gate type in which a first semiconductor region of a second conductivity type provided on a semi-insulating substrate is electrically connected to an external terminal at one end, and the other end constitutes an input stage circuit of an integrated circuit. "A semiconductor integrated circuit device equipped with an electrostatic breakdown prevention circuit electrically connected to a gate electrode of a field effect transistor", wherein the semi-insulating substrate includes at least a component of the electrostatic breakdown prevention circuit. A well region of a first conductivity type is provided, and within the well region, the first semiconductor region and the first conductive region are separated by a predetermined distance, and a first half is formed.
, a 229th trough-shaped second semiconductor candy area is provided, the side of which faces substantially parallel to the outside area has a predetermined length! Shizuka as a sign of 1? lli, 7jυ Semiconductor integrated circuit system G1゜ equipped with one anti-vandalism circuit