JP2748938B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device provided with a MISFET, and more particularly, to a protection element for preventing the MISFET from being destroyed by a surge current flowing from an external electrode. The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device including

[Conventional technology]

The semiconductor integrated circuit device is provided with a protection element for preventing the internal MISFET from being destroyed by a surge current flowing from a bonding pad. This protection element is configured as a diode by using an N-channel MISFET, for example, with its drain connected to a bonding pad, its source connected to a ground line, and its gate electrode connected to a ground line. The surge current is emitted to the semiconductor substrate by surface breakdown or junction breakdown between the drain and the semiconductor substrate. The technology for protecting the internal MISFET from surge current is disclosed in
-65360.

[Problems to be solved by the invention]

The present inventor has studied the protection element using the interface breakdown or the surface breakdown of the MISFET, and has found the following problem.

That is, since the junction breakdown has a small current capacity per unit area, the drain itself is easily broken when the junction breakdown occurs. On the other hand, surface breakdown has a large current capacity per unit area,
Because it occurs on the very thin part of the surface of the semiconductor substrate,
After all, the portion causing the surface breakdown is easily broken.
If the protection element itself is destroyed as described above, there is a problem that the internal MISFET is destroyed when a surge current flows again.

An object of the present invention is to prevent the internal MISFET from being destroyed by a surge current and improve the reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, in a semiconductor integrated circuit device provided with a protection element for preventing a MISFT constituting a circuit from being destroyed by an excessive current flowing from an external electrode, the protection element is provided on a main surface of a first conductivity type semiconductor substrate. Two semiconductor regions of two conductivity type are provided close to each other, one of the semiconductor regions is connected to the external electrode, the other semiconductor region is connected to a power supply line, and the one semiconductor region is connected to the other semiconductor region. Has a structure in which the punch-through breakdown voltage is set lower than the junction breakdown voltage between the one semiconductor region and the semiconductor substrate.

[Action]

According to the above-described means, the surge current flowing from the external electrode is emitted from the first semiconductor region connected to the external electrode to the second semiconductor region connected to the power supply wiring. At this time, the current capacity per unit area of the cross-section of the channel formed by the punch-through is large, and the cross-sectional area of the channel is large. Can be protected. Therefore, the reliability of the semiconductor integrated circuit device can be improved.

[Example I of the invention]

Hereinafter, a semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to Embodiment I of the present invention. FIG. 2 is a circuit diagram illustrating an equivalent circuit of an input protection circuit according to one embodiment of the present invention. FIG. 3 is a plan view of a protection element constituting the input protection circuit shown in FIG. 1, and FIG. 4 is a sectional view taken along the line IV-IV of FIG. FIG.

As shown in FIG. 1, the input protection circuit of the semiconductor integrated circuit device according to the present embodiment includes resistance elements R1 and R2 and a clamp MISFEC.
Qn1, CQn2, and CQn3. PAD is a bonding pad and is used as an external electrode of a semiconductor integrated circuit device. The clamp MISFETCQn1 is an N-channel MISF
One of the two semiconductor regions corresponding to the source and drain of the ET is connected to a power supply potential Vcc, for example, a wiring of 5 V, and the other semiconductor region is connected to a bonding pad via a resistance element R1.
It is configured by connecting to a PAD and connecting a gate electrode to a wiring of a ground potential Vss, for example, 0V. Clamp MISFETCQn2
Is equivalent to the source and drain of the N-channel MISFET.
One of the two semiconductor regions is connected to the bonding pad PAD via the resistance element R1, the other semiconductor region is connected to the ground potential Vss wiring, and the gate electrode is also connected to the ground potential Vss.
It is configured by connecting to the ss wiring. Clamp MISF
ETCQn3 connects one of the two semiconductor regions corresponding to the source and drain of the N-channel MISFET to the bonding pad PAD via the resistor R2 and the resistor R1,
The other semiconductor region is connected to the wiring of the ground potential Vss, and the gate electrode is also connected to the wiring of the ground potential Vss. Qp1 is P channel MISFET, Qn1 is N channel
These are MISFETs, which constitute an input buffer (inverter).

After the surge current coming from the bonding pad PAD is attenuated by the resistance element R1,
It is emitted to the wiring of the power supply potential Vcc through n1, and is emitted to the wiring of the ground potential Vss through the clamp MISFETCQn2. Then, the clamp MISFETs CQn1 and CQn2, which could not be released completely, were attenuated by the resistor R2 and then clamped.
It is emitted to the wiring of the ground potential Vss or the semiconductor substrate (p ⁻ type) through the MISFETCQn3. This prevents the destruction of the internal P-channel MISFETQp1 or N-channel MISFETQn1.

Next, as shown in FIG. 2, the output protection circuit provided in the semiconductor integrated circuit device of the present embodiment includes a clamp MISF.
It is composed of ETCQn4 and clamp MISFETCQn5. The clamp MISFET connects one of the two semiconductor regions corresponding to the source and the drain of the N-channel MISFET to the wiring of the power supply potential Vcc, connects the other semiconductor region to the bonding pad PAD, and connects the gate electrode to the ground potential. It is connected to Vss wiring. Clamp MISFETCQn5
One of the two semiconductor regions corresponding to the source and drain of the N-channel MISFET is connected to the bonding pad PAD, the other semiconductor region is connected to the wiring of the ground potential Vss, and the gate electrode is connected to the wiring of the ground potential Vss. It is configured by connecting to. Qp2 is a P-channel MISFET and Qp2
n2 is an N-channel MISFET.

The surge current coming from the bonding pad PAD is released to the wiring of the power supply potential Vcc by the clamp MISFETCQn4, and the ground potential Vs by the clamp MISFETCQn5.
Released to s wiring. This allows the internal P-channel M
Destruction of ISFETQp2 and N-channel MISFETQn2 is prevented.

Next, the specific configuration of the resistance elements R1 and R2 and the clamp MISFETs CQn1 to CQn3 constituting the input protection circuit shown in FIG. 1 will be described with reference to FIGS.

As shown in FIG. 3 and FIG.
The PAD is connected to one end of the resistance element R1, and is made of an aluminum film or the like. The resistance elements R1 and R2 are composed of n ⁺ type semiconductor regions on the main surface of the semiconductor substrate 1 made of p ⁻ type single crystal silicon. 8 denotes a first passivation film 7 and a thin silicon oxide film 5 on the surface of the semiconductor substrate 1.
This is a connection hole formed by removing.

Clamp MISFETCQn2 of Figure 1 includes two n ⁺ -type semiconductor region 4 which is eccentrically disposed with respect to the main surface of the semiconductor substrate 1, a thin silicon oxide film 5 of the surface of the n ⁺ semiconductor region 4,
A field insulating film 2A made of a silicon oxide film between the n ⁺ semiconductor regions 4 on the main surface of the semiconductor substrate 1, a p-type semiconductor region 3A under the field insulating film 2A, and a first passivation film 7 A shield layer (corresponding to a gate electrode) 9D made of an aluminum film and a portion of the passivation film 7 below the shield layer 9D.
The shield layer 9D is arranged right above the field insulating film 2A. The passivation film 7 is made of a silicon oxide film formed by CVD. One of the two n ⁺ -type semiconductor regions 4 is connected to the end of the resistance element R1 by a wiring 9A made of an aluminum film. The n ⁺ type semiconductor region 4 different from the above is provided with a ground potential Vss made of an aluminum film.
Is connected to the wiring 9B. The shield layer 9D is formed integrally with the wiring 9B, and is always fixed to the ground potential Vss. Here, the distance between the two n ⁺ -type semiconductor regions 4 is set such that the punch-through breakdown voltage between them is lower than the surface breakdown breakdown voltage between the n ^{+ -type} semiconductor region 4 and the semiconductor substrate 1. . n ⁺ -type surface breakdown voltage of the semiconductor region 4, the n ⁺ -type semiconductor region impurity concentration of 4 and Ili by impurity concentration of the semiconductor substrate 1, for example, n ⁺ -type impurity concentration of 1 × 10 semiconductor region 4
When the order of ¹⁶ / cm ³ is about 15V. If the surface breakdown voltage is 15 V and the distance between the two n ⁺ -type semiconductor regions 4 is set to 0.8 to 1.0 μm, the punch-through breakdown voltage between the two n ⁺ -type semiconductor regions 4 is 9 V Can be set to about. When the second-layer passivation film 10 and the third-layer passivation film (final protection film) 11 are charged up, the shield layer 9B is placed between the two n ⁺ -type semiconductor regions 4 by the charge. In order to prevent the threshold value from lowering and the clamp MISFET CQn2 from malfunctioning, the passivation films 10, 1
This is to shield from the charge of 1. Note that the passivation films 10 and 11 are, for example, a silicon oxide film, a phosphor silicate glass (PSG) film, or a coating glass (SO
G) Consists of a laminated film composed of films.

FIGS. 3 and 4 show the clamp MISFETCQn1 of FIG.
Although the clamp MISFETs CQn4 and CQn5 in FIG. 2 are not shown, the respective structures of the clamp MISFETs CQ1, CQn4 and CQn5 are the same as those of the clamp MISFETCQn2.

The clamp MIFET CQn3 includes two n ⁺ -type semiconductor regions 4 on the main surface of the semiconductor substrate 1, a thin silicon oxide film (gate insulating film) 5 on the semiconductor substrate 1, and a tungsten silicide ( WSi ₂ ) film and a gate electrode 6 composed of a two-layer film. One of the two n ⁺ -type semiconductor regions 4 is connected to one end of a resistance element R2 via a wiring 9C made of an aluminum film. The other n ⁺ type semiconductor region 4 is connected to a wiring 9B of the ground potential Vss.
It is connected to the. The gate electrode 6 is also connected to the wiring 9B. The gate electrode 6 has the internal MISF shown in FIG.
It is formed in the same process as the gate electrodes 6 of the ETQp1 and Qn1 and the P-channel MISFETQp2 and the N-channel MISFETQn2 shown in FIG. 2, and has a gate length of about 1.3 μm. The internal N-channel MISFET Qn1 and the N-channel MISFET Qn2 shown in FIG. 2 are MISFETs having a so-called LDD (Lightly Doped Drain) structure in which the ends of the source and drain on the channel region side are made lower in concentration than other portions. is there. The sidewall 12 provided on the side of the gate electrode 6 of the clamp MIFET CQn3 is
This is formed at the same time when the sidewall 12 is formed on the side of the gate electrode 6 of the SFET Qn1.
From a silicon oxide film. The wiring 9C is the first
It is connected to the gate electrodes of the P-channel MISFETQp1 and the N-channel MISFETQn1 in the figure. Reference numeral 2 denotes a field insulating film made of a silicon oxide film, under which a p-type channel stopper region 3 is formed. The clamp MISFETCQ
The p-type semiconductor region 3A below the n2 field insulating film 2A is
It is formed in the same step as the mold channel stopper region 3.

Next, clamp MISFETCQn when surge current enters
The operation of 1, CQ2, CQn3 will be described.

Bonding pads PAD of the resistance element R1, the surge current enters one of the n ⁺ -type semiconductor region 4 of the clamp MISFETCQn2 through the wire 9A, the depletion from the n ⁺ -type semiconductor region 4 to the semiconductor substrate 1 and a p-type semiconductor region 3A The layer extends greatly, and punch-through occurs between the layer and the n ⁺ type semiconductor region 4 to which the wiring 9B is connected. Through the channel formed by this punch-through, the clamp MISFETCQn2 emits a surge current to the wiring 9B. In the clamp MISFETCQn1, n ⁺ -type semiconductor region in which the wiring of the other n ⁺ -type semiconductor region 4 i.e. the power supply potential Vcc, which is formed from one of the n ⁺ -type semiconductor region 4 wire 9A are connected by the punch-through is connected 4. A surge current is emitted to 4. In addition, clamp MISFETCQ
n2 (CQn1 same), since the surge current enters the one of the n ⁺ -type semiconductor region 4 may be one of the structures that can be released by the punch-through to the other n ⁺ -type semiconductor regions 4, as minimum configuration requirements , P ⁻ type semiconductor substrate 1 and only two n ⁺ type semiconductor regions 4 separated by an appropriate distance.

Next, the operation of the clamp MISFETCQn3 will be described. The clamp MISFET CQn3 applies a surge current from the bonding pad PAD to the n ⁺ -type semiconductor region 4 through the resistance element R1, the wiring 9A, the resistance element R2, and the wiring 9C to the n ⁺ -type semiconductor region 4.
Is released into the semiconductor substrate 1 by the surface breakdown. Although not shown, a third-layer wiring made of an aluminum film is interposed between the second-layer passivation film 10 and the third-layer passivation film 11.

Embodiment II of the Invention FIG. 5 is a plan view of a protection element of a semiconductor integrated circuit device according to Embodiment II of the present invention, and is a plan view of a clamp MISFETCQn2 shown in the equivalent circuit of FIG.

FIG. 6 is a sectional view taken along the line VI-VI of FIG.

The clamp MISFETCQn2 of the present embodiment II is composed of two n ⁺ -type semiconductor regions 4 provided separately on the main surface of the semiconductor substrate 1.
A portion of the semiconductor substrate 1 between the n ⁺ type semiconductor regions 4, a thin silicon oxide film (gate insulating film) 5 on the surface of the semiconductor substrate 1, and a gate electrode 6 on the silicon oxide film 5.
And a passivation film 7 on the gate electrode 6 and a shield layer 9D on the passivation film 7. The gate electrode 6 is not connected to any wiring and is electrically floating. And two n
^{The +} type semiconductor region 4 is formed by ion implantation with respect to the gate electrode 6 in a self-aligned manner. 2
The separation distance between two n ⁺ -type semiconductor regions 4 is equal to the internal MISFET Qp
The separation distance between the source and drain of 1, Qn1 or Qp2, Qn2 is 1.2
When it is about μm, it is set to about 0.8 to 1.0 μm. By doing so, the punch-through breakdown voltage between the two n ⁺ -type semiconductor regions 4 is made lower than the surface breakdown voltage of the n ⁺ -type semiconductor regions 4. This clamp MISFETCQn2 has two n ⁺ , similarly to the clamp MISFETCQn2 of the first embodiment.
The surge current is released by punch-through between the mold semiconductor regions 4. The clamp MISFETCQn1 shown in FIG. 1 and the clamp MISFETs CQn4 and CQn5 shown in FIG. 2 have the same structure. The clamp MISFETCQn3 in FIG. 1 has the same structure as the clamp MISFETCQn3 described in the first embodiment.

Next, the electrical operation of the clamp MISFETCQn2 of the embodiment II will be described.

FIG. 7 shows the clamp MISFET shown in FIGS. 4 and 6.
FIG. 9 is a cross-sectional view for describing an electrical operation when a surge current enters CQn2.

As shown in FIG. 7, with one surge voltage V _SUR the n ⁺ -type semiconductor region 4 of the two Cal, depletion Dep extends largely from the n ⁺ -type semiconductor region 4 into the semiconductor substrate 1 Then, the junction with the depletion layer Dep around the other n ⁺ type semiconductor region 4 is formed. That is, punch-through occurs between the two n ⁺ -type semiconductor regions 4 due to the surge voltage V _SUR . The part where this punch-through occurs becomes a channel, and the surge current I
_SUR flows. At this time, the punch-through occurs at a portion deeper than the surface of the semiconductor substrate 1, and the cross-sectional area of the channel formed by the punch-through is smaller than the cross-sectional area of the channel at the time of surface breakdown of the n ⁺ type semiconductor region 4. Much larger. Therefore, it is possible to obtain a clamp MISFET (protection element) CQn2 having a large current capacity that is not destroyed by a surge current.

Next, a method for forming the n ⁺ type semiconductor region 4 of the clamp MISFETCQn2 will be described. Other clamp MISFETCQn1CQ4, CQn5
Is formed by the same method as that of the clamp MISFETCQn2, and a description thereof will be omitted.

8 and 9 are cross-sectional views of the clamp MISFETCQn2 shown in FIGS. 5 and 6 in a manufacturing process.

The clamp MISFETCQn2 is, as shown in FIG.
^- type field insulating film 2 on the semiconductor substrate 1, p-type channel stopper region 3, after forming the gate insulating film 5, for example,
A polycrystalline silicon film is formed on the semiconductor substrate 1 by CVD, and a refractory metal film such as a tungsten silicide (WSi ₂ ) film is further formed thereon. Then, the refractory metal film and the polycrystalline silicon film are patterned by anisotropic dry etching such as reactive ion etching to form the gate electrode 6. Reference numeral 20 denotes a mask for patterning the gate electrode 6, which is made of a resist film.
The mask 20 is removed after patterning the gate electrode 6. Here, since the processing accuracy of the anisotropic dry etching is very high, the gate electrode 6 can be formed with almost no dimensional error between the mask 20 and the patterned gate electrode 6. After the gate electrode 6 is formed, as shown in FIG. 9, the main surface of the semiconductor substrate 1 is n-implanted by ion implantation 21 using the gate electrode 6 as a mask.
A type impurity 22, for example, phosphorus (P) or arsenic (As) is introduced. The impurity concentration is about 1 × 10 ¹⁶ / cm ³ . This ion implantation can also serve as ion implantation for forming low-concentration layers of the source and drain of the N-channel MISFET having the LDD structure. That is, low-concentration ion implantation is performed on the clamp MISFETCQn2 region by utilizing the ion-implantation step for forming the low-concentration layers of the source and drain. Thereafter, the area other than the clamp MISFETCQn2 region is covered with a mask made of a resist film, and the clamp MISFETCQn
Ion implantation into the region to reduce the impurity concentration to 1 × 10 ¹⁶ /
cm ³ After the ion implantation, the mask made of the resist film is removed. Thereafter, the semiconductor substrate 1 is annealed to diffuse the impurity 22, thereby forming the n ⁺ type semiconductor region 4. Thus, the n ⁺ type semiconductor region 4 can be formed in a self-aligned manner with respect to the gate electrode 6. And n
The lateral spread of the ⁺ type semiconductor region 4 can be accurately adjusted by controlling the annealing temperature and time.

That is, at the separation distance of the n ⁺ type semiconductor region 4,
Since there is little error between the design dimensions and the actual size after formation, and an accurate value can be obtained, the punch-through breakdown voltage between the two n ⁺ -type semiconductor regions 4 is accurate, and a highly reliable clamp MISFETCQn2 is provided. Obtainable. The other clamp MISFETCQn1 shown in FIG. 1 and the clamp MISF shown in FIG.
Since ETCQn4 and CQn5 are formed in the same manner, a highly reliable one can be obtained.

As described above, the clamp according to the embodiment I of the present invention is described.
According to the MISFET, the MISFET (Qp1, Qn1, or Qp) connected to the external electrode (bonding pad PAD) on the semiconductor substrate 1
2, Qn2) and a protection element (clamp) for preventing the MISFET from being destroyed by a surge current flowing from the external electrode.
MISFETs CQn1 and CQn2 or CQn4 and CQn5).
A first semiconductor region 4 provided on the main surface of the semiconductor substrate and connected to the external electrode (bonding pad PAD) with a conductivity type opposite to that of the semiconductor substrate, and a portion of the main surface of the semiconductor substrate different from the first semiconductor region. A second semiconductor region 4 which is provided on the semiconductor substrate and has a conductivity type opposite to that of the semiconductor substrate and is connected to a power supply wiring (Vcc wiring or Vss wiring) of the semiconductor integrated circuit device;
The semiconductor substrate comprises a region between the first semiconductor region and the second semiconductor region, and a punch-through breakdown voltage between the first semiconductor region and the second semiconductor region is between the first semiconductor region and the semiconductor substrate. With the structure set lower than the junction withstand voltage, the surge current flowing from the external electrode
The light is emitted from the first semiconductor region connected to the external electrode to the second semiconductor region connected to the power supply wiring. At this time,
Since the current capacity per unit area of the cross section of the channel formed by the punch-through is large and the cross section of the channel is large, it is possible to protect the internal MISFET from surge current without breaking the protection element itself. it can. Therefore, the MISFET can be protected from surge current without destroying the protection element itself, and the reliability of the semiconductor integrated circuit device can be improved.

Further, according to the clamp MISFET of Example II of the present invention,
Since two n ⁺ -type semiconductor regions 4 are formed in self-alignment with respect to the gate electrode 6 having a small error from the design dimensions, the distance between the two n ⁺ -type semiconductor regions 4 can be set accurately. As a result, a highly reliable clamp MISFET with little variation in punch-through withstand voltage can be obtained.

As described above, the present invention has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Absent.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

The surge current flowing from the external electrode is a punch-through in which a channel having a large current capacity per unit area and a large cross-sectional area is formed, and the surge current flowing from the first semiconductor region connected to the external electrode to the power supply wiring. 2 is released to the semiconductor region. Therefore, the MISFET can be protected from the surge current without breaking the protection element itself, and the reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to Embodiment I of the present invention. FIG. 2 is a circuit diagram illustrating an equivalent circuit of an input protection circuit according to one embodiment of the present invention. FIG. 3 is a plan view of a protection element constituting the input protection circuit shown in FIG. 1, and FIG. 4 is a sectional view taken along the line IV-IV of FIG. 5, FIG. 5 is a plan view of a protection element of the semiconductor integrated circuit device according to Example II of the present invention, FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5, FIG. Clamp MISFETCQ shown in FIGS. 5 and 6
FIG. 8 and FIG. 9 are cross-sectional views in a manufacturing process of the clamp MISFETCQn2 shown in FIG. 5 and FIG. 6 for explaining an electrical operation when a surge current enters n2. . In the figure, PAD: bonding pad, R1, R2: resistance element, CQn1, CQn2, CQn3, CQn4, CQn5: clamp MISFET, Qp
1, Qp2, Qn1, Qn2 ... MISFET, 1 ... p ^- type semiconductor substrate, 2,
2A: Field insulating film, 3, 3A: p-type channel stopper region, 4: n ⁺ type semiconductor region, 5: thin silicon oxide film, 6: gate electrode, 9D: shield layer (aluminum).

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit device having a protection element for preventing a MISFET constituting a circuit from being destroyed by an excessive current flowing from an external electrode, wherein the protection element is a semiconductor substrate of a first conductivity type. Two adjacent semiconductor regions of the second conductivity type on the surface and a gate provided on the main surface of the semiconductor substrate between the two semiconductor regions via an insulating film; one semiconductor region is connected to the external electrode; Connecting the region to a power supply wiring, a punch-through withstand voltage between the one semiconductor region and the other semiconductor region is set lower than a junction withstand voltage between the one semiconductor region and the semiconductor substrate, and an insulating layer is provided on the gate. A semiconductor integrated circuit device comprising a shield layer provided through a film. 2. A field insulating film is provided on a main surface of the semiconductor substrate located between the first semiconductor region and the second semiconductor region of the semiconductor substrate, and the gate electrode is provided on the field insulating film. The semiconductor integrated circuit device according to claim 1, wherein: