JPH021983A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the breakage of an inner MISFET due to a surge current so as to improve a semiconductor integrated circuit device in reliability by a method wherein a punch-through breakdown strength between a first semiconductor substrate and a second semiconductor region is set lower than a junction breakdown strength between them. CONSTITUTION:Concerning a clamp MISFET CQn2, one of two semiconductor regions, corresponding to a source and a drain of an N-channel MISFET, is connected with a bonding pad PAD through the intermediary of a resistance element R1, and the other semiconductor region and a gate electrode are connected with a wiring of a ground potential Vss. Therefore, after a surge current flowing from the bonding pad has been attenuated through the resistance element R1, it is discharged to a wiring of a power source potential Vcc through the clamp MISFET CQn1 and the wiring of the ground potential Vss through the clamp MISFET CQn2. By these processes, a P channel MISFET Qp1 or an N channel MISFET Qn1 inside are protected against damage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device equipped with an MISFET, and particularly to a protection element for preventing the MISFET from being destroyed by a surge current flowing from an external electrode. The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with the present invention.

[Conventional technology]

Semiconductor integrated circuit devices are provided with protection elements to prevent internal MISFETs from being destroyed by surge currents flowing from bonding pads. This protection element uses, for example, an N-channel MISFET,
The drain is connected to a bonding pad, the source is connected to a ground line, and the gate electrode is connected to a ground line to form a diode. surge current.

It is released into the semiconductor substrate by surface breakdown or junction breakdown between the train and the semiconductor substrate. Note that a technique for protecting the internal MISFET from surge current is described in Japanese Patent Laid-Open No. 62-65360.

[Problem to be solved by the invention]

The inventor of the present invention discovered the first problem as a result of studying the interfacial breakdown of the MISFET or the S-wire using the surface breakdown.

That is, since the junction breakdown has a small current capacity per unit area, the drain itself is easily destroyed when the junction breakdown occurs. On the other hand, surface breakdown has a large current capacity per unit area, but since it occurs in an extremely thin portion of the surface of the semiconductor substrate, the portion where surface breakdown occurs is likely to be destroyed. If the protection element itself is destroyed in this way, there is a problem in that when a surge current flows in again, the internal MISFET will be destroyed.

The purpose of the present invention is to eliminate internal MI 5F by surge current.
The object of the present invention is to prevent the ET from being destroyed and improve the reliability of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of Specification H and the accompanying drawings.

[Means to solve the problem]

A brief overview of one typical invention disclosed in this application is as follows.

That is, M connected to the external electrode on the semiconductor substrate
In the semiconductor integrated circuit device comprising an I S FET and a protection element for preventing the M I S FET from being destroyed by the surge X11 flow flowing from the external electrode, the a first semiconductor region provided on the main surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and connected to the external electrode; and a first semiconductor region provided on the main surface of the semiconductor substrate in a different part from the first semiconductor region The second semiconductor region has a conductivity type opposite to that of the semiconductor substrate and is connected to a power supply wiring of a semiconductor integrated circuit device, and a region of the semiconductor substrate between the first semiconductor region and the second semiconductor region.

The punch-through breakdown voltage between the first semiconductor region and the second semiconductor region is set lower than the junction breakdown voltage between the first semiconductor region and the semiconductor substrate.

[Effect]

According to the above-described means, the surge current flowing from the external electrode is discharged from the first semiconductor region connected to the external electrode to the second semiconductor region connected to the power supply wiring. At this time, since the current capacity per unit area of the cross-section of the channel formed by the punch-through is large and the cross-sectional area of the channel is large, the internal MISFET can be protected from the surge current without destroying the protection element itself. can be protected. Therefore, the reliability of the semiconductor integrated circuit device can be improved.

[Embodiments of the invention! ]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to Embodiment I of the present invention will be described below with reference to the drawings.

FIG. 1 shows an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to Embodiment I of the present invention, and FIG. 2 shows an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to an embodiment of the present invention. Fig. 3 is a plan view of the protection element forming the input protection circuit shown in Fig. 1; Fig. 4 is the equivalent circuit of the output protection circuit shown in Fig. 3; FIG.

As shown in FIG. 1, the human power protection circuit of the semiconductor integrated circuit device of this embodiment includes resistance elements R1 and R2, and a clamp MI
SFETCQnl, CQrr2. It is composed of CQn3. PAD is a bonding pad and is used as an external electrode of a semiconductor integrated circuit device. The clamp MISFET CQn1 connects one of two semiconductor regions corresponding to the source and drain of the N-channel MISFET to a wiring with a power supply potential Vcc, for example, 5. PAD, and the gate electrode is connected to a wiring at a ground potential Vss, for example, Ov. Clamp MI 5FET CQn2 connects one of the two semiconductor regions corresponding to the source and train of the N-channel MISFET to the bonding pad PAD via the resistance element R1.
, the other semiconductor region is connected to the wiring at ground potential Vss, and the gate electrode is also connected to the wiring at ground potential Vss. Clamp MISFETCQ
n3 is the source of N-channel MISFET.

One of the two semiconductor regions corresponding to the drain is connected to the bonding pad PAD via the resistor R2 and further through the resistor R1, and the other semiconductor region is connected to the ground potential Vs.
s wiring, and the gate electrode is also connected to the ground potential Vss.
It is configured by connecting to the wiring. Qpl is a P-channel MISFET, and Qnl is an N-channel MISFET, which constitute an input buffer (inverter).

After the surge current entering from the bonding pad PAD is attenuated by the resistive element R1.

Power supply potential Vcc through clamp MISFET CQnl
is emitted to the wiring of the clamp MISFE T CQ
It is released to the wiring at ground potential Vss through n2.

And those clamps MISFETCQn1. ．． CQ
The amount that could not be released by n2.

Clamp MISFE'l after being attenuated by resistor element T-R2
", is released through CQn 3 to the wiring at ground potential Vss or to the conductive substrate (p-type). This prevents the internal P-channel MISFET QPI or N-channel MISFET QnL from being destroyed.

Next, as shown in FIG. 2, the output protection circuit provided in the semiconductor integrated circuit device of this embodiment is a clamp MIS
It is composed of FETCQn4 and clamp MISFETC, Qn5. Clamp MISFET is N channel M
ISFET source.

One of the two semiconductor regions corresponding to the train is connected to the wiring of the power supply potential Vcc.

The other semiconductor region is connected to the bonding pad PAD, and the gate electrode is connected to the wiring at the ground potential Vss. Clamp MISFET CQn5 connects one of the two semiconductor regions corresponding to the source and drain of the N-channel MISFET to the bonding pad PAD, connects the other semiconductor region to the wiring at the ground potential Vss, and connects the gate electrode to the ground. It is configured by being connected to a wiring having a potential Vss. Q p 2 is P channel M
ISFET = Qn2 is an N-channel MISFET.

The surge current coming from the bonding pad PAD is applied to the power supply potential vc by the clamp MISFET CQn4.
c wiring and also clamp MISFET CQn
5, it is released to the wiring at ground potential Vss. This prevents the internal P-channel MISFETQp2 and N-channel MISFETQn2 from being destroyed.

Next, resistor elements R1, R2 and clamp MISFETs CQnl to CQ that constitute the input protection circuit shown in FIG.
, n3 will be explained with reference to FIGS. 3 and 4.

As shown in FIGS. 3 and 4, the bonding pad P
AD is connected to one end of the resistance element R1 and is made of an aluminum film or the like. Resistance elements R1 and R2 are
It consists of an n-type semiconductor region on the main surface of a conductive substrate 1 made of p-type single crystal silicon. Reference numeral 8 denotes a contact hole formed by removing the first layer passivation film 7 and the thin silicon oxide film 5 on the surface of the conductive substrate 1.

The clamp MISFET CQn2 shown in FIG. , a field insulating film 2A made of a silicon oxide film between the open-type semiconductor regions 4 on the main surface of the semiconductor substrate 1, a p-type semiconductor region 3A under this field insulating film 2A, and a first layer [ ]. It is composed of a shield layer (corresponding to a gate electrode) 9D made of an aluminum film on the passivation film 7, and a portion of the passivation film 7 below the shield layer 9D. The shield layer 9D is placed directly above the field insulating film 2A.

The passivation film 7 is made of a silicon oxide film or the like produced by CVD. One of the two n-type semiconductor regions 4 is connected to the end of the resistance element R1 by a wiring 9A made of an aluminum film.

The n-type semiconductor region 4, which is different from the above, is connected to a wiring 9B made of an aluminum film and having a ground potential Vss.

The shield layer 9D is formed integrally with the wiring 9B and is always fixed to the ground potential Vss. Here, the separation distance between the two n'-type semiconductor regions 4 is determined by the punch-through breakdown voltage between them.

It is set to be lower than the surface breakdown voltage between the n-type semiconductor region 4 and the semiconductor substrate 1. The surface breakdown voltage of the n° type semiconductor region 4 varies depending on the impurity concentration of the n° type semiconductor region 4 and the impurity concentration of the semiconductor substrate 1. For example, if the impurity concentration of the n° type semiconductor region 4 is I x 10" /cj, it is about 15V.And when this surface breakdown voltage is 15V,
The distance between the two n° type semiconductor regions 4 is 0.8 to 1.
．． When set to 0 μm, the two n-type semiconductor regions 4
The punch-through withstand voltage between the two can be set to about 9V. The shield layer 9B is a second layer of the shield layer 9B.
0. Third layer passivation film (final protective film) 11
In order to prevent the clamp MI 5FET CQn2 from malfunctioning due to the lowering of the threshold voltage between the two n° type semiconductor regions 4 due to the charge when the charge is increased, the passivation is applied under the shield layer 9B. This is to shield the membrane 10.11 from charges.

Note that the passivation films tO and U are composed of laminated films constructed using, for example, a silicon oxide film, a silicon oxide glass (PSG) film, or a coated glass (SOG) film.

Figures 3 and 4 show the clamp MISFET of Figure 1.
CQnl and clamp MISF' E T in Fig. 2
Although CQ n 4 and CQ n 5 are not shown,
Clamp MISFET CQ n 1,
The structures of CQ n 4 and CQ n 5 are the same as those of the clamp MISFE'rCQ n 2.

The clamp MISFET CQ n 3 connects two n-type semiconductor regions 4 on the main surface of the semiconductor substrate 1 and a thin silicon oxide film (gate insulating film) 5 on the semiconductor substrate 1.
and a gate electrode 6 made of a two-layer film in which, for example, a tungsten silicide (WSxz) film is laminated on a polycrystalline silicon film. One of the two n-type semiconductor regions 4 is connected to one end of the resistance element R2 via a wiring 9C made of an aluminum film. The other n-type semiconductor region 4 is connected to a wiring 9B at ground potential Vss. Gate electrode 6 is also connected to wiring 9B. The gate electrode 6 is connected to the internal MISFETQ shown in FIG.
p 1 + Q n 1 and the P-channel MISFET Qp2. shown in FIG. N channel M I S F E
It was formed in the same process as the gate electrode 6 of TQn2, and its gate length is about 1.3 μm. Note that the internal N-channel MISFETQnl and the N-channel MISFETQ shown in FIG.
n2 is a so-called LDD (Li
MISF with Ghtly Doped Drain) structure
It is ET. Clamp MISFET CQ
The side wall 12 provided on the side of the gate electrode 6 of n3 is connected to the internal N-channel MISFETQn.
It is formed at the same time as the sidewall 12 is formed on the side of the gate electrode 6 of 1, and is made of, for example, a silicon oxide film formed by CVD. The wiring 9C is the first
P-channel MISFET Qpl and N-channel MI in the figure
Connected to the gate electrode of 5FETQn1. 2
is a field insulating film made of a silicon oxide film, under which a p-type channel stopper region 3 is formed. Said clamp MISFET CQ n 2
The p-type semiconductor region 3A under the field insulating film 2A is
It is formed in the same process as p-type channel stopper region 3.

Next, when a surge current occurs, the clamp MIS F
ET CQ n 1 , CQ n 2 , CQ
The operation of n3 will be explained.

From bonding pad PAD to resistance element R1゜ wiring 9A
When a surge current enters one n'-type semiconductor region 4 of the clamp MISFET CQn2 through the surge current, a depletion layer greatly extends from this n'-type semiconductor region 4 to the semiconductor substrate 1 and the P-type semiconductor region 3A, and the wiring 9B is connected. A punch-through occurs between the n-type semi-soul region 4 and the n-type semi-soul region 4. Through the channel formed by this punch-through, the clamp M
I S FE TCQ n 2 connects surge current to wiring 9B
Release to. In the clamp MI S FETCQn 1, one of the n-type semiconductor regions 4 to which the wiring 9A is connected
A surge current is discharged from the n-type semiconductor region 4 formed by punch-through to the other n-type semiconductor region 4, that is, the n-type semiconductor region 4 to which the wiring of the power supply potential Vcc is connected. In addition,
The clamp MISFET CQn2 (same as CQnl) only needs to have a structure that can discharge the surge current that has entered one n° type semiconductor region 4 to the other n type semiconductor region 4 by punch-through, so the minimum configuration requirements are as follows. In this case, only the p-type semiconductor region 1 and two n°-type semiconductor regions 4 separated by an appropriate distance are required.

Next, the clamp M I S F E T CQ n
The operation of step 3 will be explained. Clamp MISFETC-Qn
3 is.

From bonding pad PAD to resistance element R1, wiring 9A
, resistance element R2, and the n° type semiconductor region 4 through the wiring 9C.
The surge current that has entered is discharged into the semiconductor substrate 1 by surface breakdown of the n-type semiconductor region 4. Although not shown, a third layer wiring made of an aluminum film is interposed between the passivation film 10 of the second layer [1] and the passivation film 11 of the third layer.

[Embodiment 11 of the Invention] FIG. 5 is a plan view of a protection element of a semiconductor integrated circuit device according to Embodiment H of the invention, and the clamp MISFET CQ shown in the equivalent circuit of FIG. It is a top view of n2.

FIG. 6 is a sectional view taken along the line Vl-VI in FIG. 5.

Clamp M I S F E T CQ of this embodiment H
n 2 is 2 spaced apart from each other on the main surface of the semiconductor substrate 1.
11-type semiconductor regions 4 and those D of the semiconductor substrate 1
``Type 1'': The part between the conductor regions 4 and the ``type conductor substrate l''
A thin silicon oxide layer (gate insulating film) 5 on the surface of
It is composed of a gate electrode 6 on a silicon oxide film 5, a passivation film 7 on the first and second gate electrodes 6, and a shield layer 9D on the passivation film 7. The gate electrode 6 is not connected to any wiring and is electrically floating. The two n-type semiconductor regions 4 are formed by ion implantation into the gate electrode 6 in a self-aligned manner. The separation distance between the two n-type semiconductor regions 4 is equal to the internal M I S F E
T Q p 1 , Q nl or Qp2. When the separation distance between the source and drain of Qn2 is about 1.2 μm, 0
．． The thickness is set to about 8 to 1.0 μm. By doing so, the punch-through breakdown voltage between the two n.sup.-type semiconductor regions 4 is made lower than the surface breakdown voltage of the n.sup.-type semiconductor region 4. This clamp MISFETCQn2 is similar to the clamp MISFETCQn2 of the embodiment (2).
Since a surge current is emitted by punching through the two n° type semiconductor regions 4, even the two n° type semiconductor regions 4 and the region between the two n° type semiconductor regions 4 of the semiconductor substrate 1 are provided. That's fine.

That is, the silicon oxide film 5. Gate electrode6. Pansivation film7. The shield layer 9D may be omitted. In addition,
Clamp MISFET CQnl and second
Clamp MISFE TCQ n 4 shown in the figure,
CQ n 5 also has a similar structure. The clamp MISFET CQ n 3 in FIG.

Said embodiment I″r: r: Description lamp MIsFETcQn
It has the same structure as 3.

Next, the clamp M I S FETCQn of Example H
The electrical operation of No. 2 will be explained.

Figure 7 shows the clamp MISF shown in Figures 5 and 6.
FIG. 3 is a cross-sectional view for explaining electrical operation when a surge current enters ETCQn2.

As shown in FIG. 7, when a surge voltage V S LI R is applied to one of the two n-type semiconductor regions 4 , a depletion layer D is formed from the semiconductor region 4 into the semiconductor substrate 1 .
ep is greatly extended, and the other n-type semiconductor region I! ! ll
: Junction with depletion layer Dep around 4. That is, punch-through occurs between the two n' type semiconductor regions 4 due to the surge voltage V S u R. The portion where this punch-through occurs becomes a channel, and a surge current Isu8 flows therethrough. At this time, the punch-through occurs deeper than the surface of the semiconductor substrate l, and the cross-sectional area of the channel formed thereby is larger than the cross-sectional area of the channel at the time of surface breakdown of the n-type semiconductor region 4. Much bigger. Therefore, it is possible to obtain a lamp MISFET (protection element) CQn2 with a large current capacity that is not destroyed by surge current.

Next, a method of forming the n° type half-soul region 4 of the clamp MISFET CQn2 will be explained. Other clamp MISFET
CQnlCQn4. CQn5 is a clamp MISFET
Since it is formed by the same method as CQn2, the explanation will be omitted.

8 and 9 are cross-sectional views of the clamp MI 5FETCQn2 shown in FIGS. 5 and 6 during the manufacturing process.

As shown in FIG. 8, the clamp MISFET CQn2 includes a p-type semiconductor substrate 1, a field insulating film 2, a p-type channel stopper region 3. After forming the gate insulating film 5, a polycrystalline silicon film is formed on the semiconductor substrate 1 by, for example, CVD, and a high melting point metal film such as a tungsten silicide (WSi2) film is further formed on this film. and,
The high melting point metal film and polycrystalline silicon film are patterned by anisotropic dry etching such as reactive ion etching to form the gate electrode 6. 20 is the gate electrode 6
It is a mask used when patterning, and is made of a resist film. This mask 20 is.

After patterning the gate electrode 6, it is removed. here,
Since anisotropic dry etching has very high processing accuracy, the gate electrode 6 can be formed with almost no dimensional error between the mask 20 and the patterned gate electrode 6. After forming the gate' city pole 6, the 9th gate
As shown in the figure, using the gate electrode 6 as a mask, an n-type impurity 2 is implanted into the main surface of the semiconductor substrate 1 by ion implantation 21.
21 For example, phosphorus (P) or arsenic (As) is introduced. The impurity concentration is set to about lXl0''/ad. This ion implantation can also be used as ion implantation for forming low concentration layers of the source and drain of the N-channel MISFE® with the LDD structure. That is, the source ,
A low-concentration ion implantation process is performed into the clamp MISFET CQn2 region using a deep ion implantation process that forms a low-density layer on the drain. After this, clamp MI
Cover areas other than the SFETCQn2 area with a mask made of a resist film.

Clamp M I S F E T CQ Ions are implanted into the n region to bring the impurity concentration to about lXl0''/aj. After the ion implantation, the mask made of the resist film is removed. After this, the semiconductor substrate 1 is annealed. The impurity 22 is diffused to form the n° type semiconductor region 4. In this way, the n type semiconductor region 4 can be formed in a self-aligned manner with respect to the gate electrode 6. The lateral spread of can be precisely tuned by controlling the annealing temperature and time.

In other words, in terms of the distance between the two n-type semiconductor regions 4, there is little error between the design dimensions and the actual formed distance, and an accurate value can be obtained. The breakdown voltage becomes accurate and a highly reliable clamp MISFET CQn2 can be obtained. Other clamps MI 5FETCQn 1 and 2 shown in FIG.
Clamp M I S F E T CQ n shown in the figure
4 and CQ n 5 are formed in the same manner, so that highly reliable products can be obtained.

As explained above, the clamp M according to the first embodiment of the present invention
According to the I S FET, the M I connected to the external electrode (ponding pad PAD) on the semiconductor substrate 1
S F E T (Q p 1 , Q n 1 or Q
p2゜Qn2) and a protection element (clamp MISFET CQnl, Cqn2 or CQ) that prevents the MISFET from being destroyed by the surge current flowing from the external electrode.
n 4 , CQ n 5), wherein the protection element is provided on the main surface of the semiconductor substrate l and has a conductivity type opposite to that of the semiconductor substrate, and is connected to the external electrode (ponding pad PAD). a first semiconductor region 4 connected to the conductor substrate; and a first semiconductor region 4 connected to the
The power wiring (Vcc
or Vss wiring)
! A4, and the first semiconductor region and the second semiconductor region of the semiconductor substrate.
a region between the semiconductor regions, and the punch-through breakdown voltage between the first semiconductor region and the second semiconductor region is set lower than the junction breakdown voltage between the first semiconductor region and the semiconductor substrate, The surge current flowing from the external electrode is discharged from the first semiconductor region connected to the external electrode to the second semiconductor region connected to the "t+Xg wiring. At this time, the cross section of the channel formed by the punch-through Since the current capacity per m area is large and the cross section of the channel is large, it is possible to protect the internal MISFET from surge current without destroying the protection element itself. The MISFET can be protected from surge current without being damaged, and the reliability of the semiconductor integrated circuit device can be improved.

Further, according to the clamp MISFET of Example H of the present invention, 2
Since the two n' type semiconductor regions 4 are formed by self-alignment, the interval between the two n1 type semiconductor regions 4 can be set accurately. This results in a highly reliable clamp with little variation in punch-through withstand voltage.
can be obtained.

The present invention has been specifically explained above using examples, but
The present invention is not limited to Examples 11 and f,
It goes without saying that various changes can be made without departing from the gist of the invention.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The surge current flowing from the external 'lu electrode is passed through the first electrode connected to the external electrode by punch-through, in which a channel with a large current capacity per unit area and a large cross-sectional area is formed.
It is emitted from the semiconductor region to the second semiconductor region connected to the power supply wiring. Therefore, the M I S FET can be protected from the surge '11i flow without the protection element -r itself being destroyed, and the reliability of the semiconductor integrated circuit device can be improved.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to Embodiment I of the present invention, and FIG. 2 shows an equivalent circuit of an input protection circuit configured in a semiconductor integrated circuit device according to an embodiment of the present invention. Equivalent circuit of the configured output protection circuit. FIG. 3 is a plan view of a protection element that configures the human power protection circuit shown in FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3, FIG. 5 is a plan view of a protection element of a semiconductor integrated circuit device according to Embodiment H of the present invention, and FIG. A sectional view taken along the vr-VI cutting line. Figure 7 shows the clamp MISF shown in Figures 5 and 6.
The cross-sectional views, FIGS. 8 and 9, for explaining the electrical operation when a surge current enters ETCQn2 are the clamp MISFET shown in FIGS. 5 and 6.
It is a sectional view in the manufacturing process of CQ n 2. In the figure, PAD...ponding pad, R1, R2,
...Resistance element, CQ n 1 + CQ n 2 p
CQn3+CQn4. CQn5-Clamp MISF
ET, Qp], +Qp2+Qn1+Qn2=・MISF
E.T. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2,2A...field insulating film, 3.3A...p-type channel stopper region, 4
... n-type semiconductor region, 5... thin silicon oxide film,
6... Gate "11i pole, 9D... Shield layer (aluminum).

Claims (1)

[Claims] 1. MISFE connected to the external electrode on the semiconductor substrate
T and the surge current flowing from the external electrode to the MI
In a semiconductor integrated circuit device including a protection element for preventing SFET from being destroyed, the protection element is provided on a main surface of the semiconductor substrate and has a conductivity type opposite to that of the semiconductor substrate and is connected to the external electrode. a first semiconductor region provided on a main surface of the semiconductor substrate in a different part from the first semiconductor region, a second semiconductor region having a conductivity type opposite to that of the semiconductor substrate and connected to a power supply wiring of a semiconductor integrated circuit device. and a region between the first semiconductor region and the second semiconductor region of the semiconductor substrate, and the punch-through breakdown voltage between the first semiconductor region and the second semiconductor region is the same as that of the first semiconductor region and the semiconductor substrate. 1. A semiconductor integrated circuit device characterized by having a structure in which the breakdown voltage of a semiconductor integrated circuit is set lower than a junction breakdown voltage between the two.