JPH07202009A - Semiconductor device having output circuit of cmos structure - Google Patents

Abstract

PURPOSE:To provide an output circuit of a high density CMOS structure having a resistance element for protection which stably operates when silicide technique is used for high speed operation. CONSTITUTION:An output circuit wherein an output terminal 43, a CMOS, and a resistance element 53 for protection between the output terminal 43 and the CMOS are arranged is formed on a semiconductor substrate 1. The resistance element 53 for protection is constituted of a diffusion layer 6 formed on the semiconductor substrate 1, and a gate electrode 26 of fixed voltage VDD which is formed on the surface region 33 of the diffusion layer 6 via a gate insulating film 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an output circuit having a CMOS structure, and more particularly to a semiconductor device having a protective resistance element provided between a CMOS and an output terminal as an output protection circuit.

[0002]

2. Description of the Related Art A cross section of a semiconductor device as disclosed in Japanese Patent Application Laid-Open No. 1-297855 is disclosed as a prior art in which a protective resistance element as a protective circuit is provided between a CMOS of an output circuit and an output terminal. FIG. 5A shows a sectional view in which a portion of the protective resistance element is enlarged, and FIG. 5B shows a circuit diagram thereof.

A P-channel type insulated gate field effect transistor (hereinafter referred to as PMOSTr) 51 and an N-channel type insulated gate field effect transistor (hereinafter referred to as NMOST).
52) are connected in series, the gates of both MOSTrs are connected to the internal circuit through the input node 42, and the input signal V _IN is applied to the drains 13 of both MOSTrs.
16 is connected to the output terminal 43 via the protective resistance element 60 and outputs the output signal V _OUT . The P ⁺ type source 12 of the PMOS Tr 51 and the N ⁺ type contact region 11 of the N well 4 are connected to the power supply voltage line 41 on the high potential side and fixed to the positive potential V _DD , and the N ⁺ type source 15 of the NMOS Tr 52 and the P substrate 1 are connected. Of the P ⁺ -type contact region 14 is connected to the low-potential-side power supply voltage line 44 and is connected to the ground potential V _GND.
It is fixed to.

Further, in the PMOSTr51, P ⁺
A P ⁺ N junction protection diode 56 is formed between the N type drain 13 and the N type well 4, and an N ⁺ P junction protection diode 55 is formed between the N ⁺ type drain 16 and the P type substrate 1 in the NMOSTr 52. Has been done. The protective resistance element 60 is composed of an N-type well 61 and an N ⁺ -type diffusion region 62 formed therein, and the N ⁺ -type diffusion region 62.
The resistance value between the contact portions 68-69 is used.
Further, in the enlarged cross-sectional view of FIG.
7 are contact holes 64 and 65 formed in the interlayer insulating film 63.
Through the contact portions 68 and 69, respectively.

Surge input (abnormal voltage input) 8 shown in FIG.
When 0 enters from the output terminal 43, the protective resistance element 60
Since this abnormal voltage causes a voltage drop, the waveform of the surge input drops to the level of 90, and the surge input 80 of a high level is directly applied to the PMOSTr51 and the NMOSTr52 forming the output stage. To prevent. Further, this surge can be further absorbed by the PN junction portion of the protection diodes 56 and 55.

FIG. 7 shows another prior art of a protective resistance element for protection.

In FIG. 7, the selective oxidation method (so-called LO
By the COS method), each region is partitioned from the main surface 3 of the semiconductor substrate 1 by a thick silicon oxide film 2 having a total film thickness of 800 nm which is buried by 400 nm. The protective resistance element 70 for protection is an N ^- type formed on the P ⁻ type silicon substrate 1.
The type well 71, the N ⁺ type impurity region 72 connected to the output terminal 43, the N ⁺ type impurity region 73 connected to the drain of the MOSTr to be protected, and the substrate formed between the two regions 72-73. And a thick silicon oxide film 2 which is partially buried, and the resistance value of the protective resistance element is determined by a current path passing through the bottom of the silicon oxide film 2.

[0008]

With the recent increase in speed and miniaturization of CMOS semiconductor devices, salicide technology (salicide process) has come to be used, and miniaturization of margins has become a problem. In salicide technology, in order to increase the speed of MOSTr, a refractory metal film is deposited on the surface of the silicon substrate such as the source and drain or the surface of the silicon gate electrode, and heat treatment is performed to form a silicide thin film on these surfaces in a self-aligned manner. Is a process of lowering the surface resistance.

When the salicide process is applied to the semiconductor device of FIG. 5A for speeding up, the thick silicon oxide film 2 partially buried in the substrate and the side wall 29 on the side wall of the gate electrode serve as a source and a drain. A silicide film 30 is formed in a self-aligned manner on the surface of each P ⁺ type and N ⁺ region, and a silicide film 30 is also formed in a self-aligned manner on the upper surface of the silicon gate electrode by the side wall 29.

However, in this case, the N formed by partitioning into the thick silicon oxide film 2 of the protective resistance element 60 is formed.
^The silicide film 30 is also formed on the surface of the ⁺ type diffusion region 62. For this reason, the resistance value of the N ⁺ type diffusion region 62 is not lowered or electrically separated due to the silicide film 30 formed on the surface thereof, so that a sufficient operation as a protective resistance element can be guaranteed. Becomes difficult,
In order to obtain the required resistance value between the contact portions 68-69, a wide area N ⁺ diffusion region 62 is required, and the degree of integration of the semiconductor device is reduced.

On the other hand, in the prior art shown in FIG. 7, the thick silicon oxide film 2 partially buried in the substrate is formed by the selective oxidation method between the N ⁺ type impurity region 72 and the N ⁺ type impurity region 73. Therefore, the decrease in surface resistance due to the salicide process can be prevented. However, the margin due to the end portion 2'of the thick silicon oxide film 2 becomes large, and a large area for forming the protective resistance element is required, which is also an obstacle to high integration. Further, the end 2'of the silicon oxide film 2
In the case of, thermal stress is large and crystal disorder occurs, and carriers are easily trapped when a charge is applied,
The resistance of the diffusion layer is affected, and stable operation as a protective resistance element becomes difficult.

[0012]

A feature of the present invention is that a CMOS is constructed by forming a PMOSTr and an NMOSTr in series on a semiconductor substrate, and a protection circuit is provided between an output terminal formed on the semiconductor substrate and the CMOS. In a semiconductor device having a protective resistance element that constitutes the protective resistance element, the protective resistance element includes a diffusion layer formed on a semiconductor substrate and a gate electrode having a fixed potential formed on a surface of the diffusion layer via a gate insulating film. And a semiconductor device having an output circuit having a CMOS configuration.

Here, a P-type well forming an NMOSTr on a semiconductor substrate, a first N-type well forming a PMOSTr, and a second N-type well serving as a diffusion layer of a protective resistance element as a protection circuit are provided. Can be provided. Second N
The type well is preferably provided in contact with the P-type well,
In this case, the N-type drain of the NMOSTr is formed between the P-type well and the second N-type well, and the N-type impurity region connected to the output terminal is formed in the second N-type well.
A gate electrode may be formed on the surface of the second N-type well between the type drain and the N-type impurity region via a gate insulating film. The gate electrode of the protective resistance element is preferably fixed to the power supply voltage on the high potential side together with the P-type source of the PMOSTr.

Alternatively, a first P-type well forming an NMOSTr on a semiconductor substrate, a first N-type well forming a PMOSTr, and a second N-type forming a diffusion layer of a first protective resistance element. A well and a third N-type well forming a diffusion layer of the second protective resistance element can be provided. It is preferable to provide the second N-type well in contact with the P-type well. In this case, the N-type drain of the NMOSTr is formed in the P-type well and the second N-type well, and is connected to the output terminal. A first N-type impurity region is formed in the second N-type well, and a first protective resistance element is provided on the surface of the second N-type well between the N-type drain and the first N-type impurity region. Gate electrode of P is formed through a gate insulating film, and P
A second N-type impurity region connected to the P-type drain of the MOSTr and a third N-type impurity region connected to the output terminal are formed in the third well, and the second N-type impurity region and the third N-type impurity region are formed.
The gate electrode of the second protective resistance element may be formed on the surface of the third N-type well between the second N-type impurity region and the N-type impurity region via the gate insulating film. The gate electrode of the first protective resistance element is fixed to the high-potential side power supply voltage together with the P-type source of the PMOSTr, and the gate electrode of the second protective resistance element is fixed to the low-potential side together with the N-type source of the NMOSTr. It is preferably fixed to the power supply voltage.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view including a partial circuit wiring diagram of the first embodiment of the present invention, and FIG. 2 is a circuit diagram of the first embodiment. A P-type well 5 forming an NMOSTr 52 on a P ⁻ type silicon substrate 1 having a flat main surface 3, and a PMOS.
A first N-type well 4 forming the Tr 51 and a second N-type well 6 which is a diffusion layer 6 of the protective resistance element 53 as a protection circuit and is in contact with the P-type well 5 are provided. In addition, by the selective oxidation method (so-called LOCOS method), for example, 400 from the flat main surface 3 into the silicon substrate 1.
Each region is partitioned by a thick silicon oxide film 2 having a total thickness of 800 nm buried therein.

In the PMOSTr 51, the main surface 3 of the substrate
Thus, a P ⁺ type source 12, a P ⁺ type drain 13 and an N ⁺ type substrate contact region 11 are formed in the first N type well 4. A film thickness of 30 nm to 5 is formed on the channel region 31.
A polysilicon gate electrode 22 is formed via a 0 nm gate oxide film 21, and sidewall insulating films 29 are formed on both side surfaces of the gate electrode 22.

In the NMOSTr 52, the main surface 3 of the substrate
In the P type well 5, an N ⁺ type source 15, an N ⁺ type drain 16 and a P ⁺ type substrate contact region 14 are formed. Film thickness of 30 nm to 50 nm on the channel region 32
Through the gate oxide film 23 of the polysilicon gate electrode 2
4 are formed, and side wall insulating films 29 are formed on both side surfaces of the gate electrode 24.

In the protective resistance element 53 as a protection circuit, the second N-type well 6 is diffused and formed simultaneously with the first N-type well 4, and the second N-type well 6 which determines the resistance value of the resistance element is formed. The N-type impurity concentration in the surface region 33 is 1 ×
10 is ¹⁵ / cm ^3, N ⁺ -type impurity region 17 to the second N-type well 6 is a resistive diffusion layer 6 from the major surface 3 is formed, also N formed in a P-type well 5 of NMOSTr53 ⁺ A type drain 16 extends into the second N well 6 and is formed here as an N ⁺ type impurity region 16.
A polysilicon gate electrode 26 is formed on the surface region 33, in which the current of the second N-type well 6 flows as a resistor, with a gate oxide film 25 having a film thickness of 10 to 70 nm interposed therebetween. In addition, sidewall insulating films 29 are formed on both side surfaces of the gate electrode 26.

The P ⁺ type source 12 and the N ⁺ type substrate contact region 11 of the PMOSTr 51 and the gate electrode 26 of the protective resistance element 53 are connected to the power supply line 41 to supply the positive voltage V _DD which is the power supply voltage on the high potential side. To be done. N
The N ⁺ type source 15 and the P ⁺ type substrate contact region 14 of the MOSTr 52 are connected to the power supply line 44 and fixed to the ground potential V _GND which is the power supply voltage on the low potential side.
In addition, the gate electrodes 22 and 24 of both MOSTrs 51 and 52
Is connected to the input node 42 of the CMOS to receive the input signal V _IN from the internal circuit. In addition, PMOSTr51
N of the P ⁺ -type drain 13 and the protective resistance element 53 ⁺
The mold region 17 is connected to the output terminal 43 of this semiconductor device which is the output node of the CMOS to output the CMOS output signal V _OUT . Further, the protection diode 56 shown in FIG.
Is formed by a P ⁺ N junction formed between the P ⁺ type drain 13 of the PMOSTr 51 and the N type well 4, and similarly a protection diode 55 is formed between the N ⁺ type drain 16 of the NMOSTr 52 and the P type well 51. It is composed of an N ⁺ P junction.

Further, the N ⁺ type drain 16 (the left side of the N ⁺ type diffusion region 16 in the figure) and the N ⁺ type source 15 of the NMOSTr 52 are connected with the N ⁻ type region 16 ′ and the N ⁻ type region 15 ′, respectively. Has an LDD structure, and the N ⁺ type impurity region 17 and the N ⁺ type impurity region 16 (right side in the figure of the N ⁺ type diffusion region 16) of the protective resistance element 53 are also N ⁻ type regions 17 ′ and N, respectively. ^The -type region 16 'is connected to form an LDD structure, which smoothes the concentration and relaxes the electric field applied to this portion. The N ⁺ type impurity region, the N ⁺ type source and the drain are formed at the same time, and the N type surface impurity concentration is 5 × 10 ²⁰ / c.
m ³ and the surface impurity concentration of the N ⁻ type region forming the LDD is 1 × 10 ¹⁷ / cm ³ .

Further, a salicide process is applied for speeding up, and the thick silicon oxide film 2 partially buried in the substrate from the main surface and the side wall 29 on the side wall of the gate electrode 29.
By this, a silicide film 30 is formed in a self-aligned manner on the surface of each P ⁺ type and N ⁺ region which will be a source, a drain, etc.,
A silicide film 30 is formed on the upper surface of the silicon gate electrode in a self-aligned manner by the side wall 29.

In the first embodiment, the PMOSTr51
Of the NMOS Tr52 and the NMOS Tr52, the protective resistance element 53 for protection is provided only between the drain 16 of the NMOS Tr52 and the output terminal 43.
Is the output terminal 4 directly without passing through the protective resistance element for protection.
Connected to 3. The reason for this is that the majority carrier of the NMOSTr is an electron, its mobility is large, and the snapback enters and the potential of the P well (sub potential) rises and the ESD
Although the breakdown voltage tends to decrease, on the other hand, in the PMOSTr, since holes are majority carriers, they do not enter snapback, so E
This is because SD is stronger than NMOSTr.

However, the reliability is further improved when the protective resistance element for protection is applied also to the PMOSTr. Therefore, as a second embodiment of the present invention, a case where a protective resistance element for protection is applied to the PMOSTr as in the case of the NMOSTr will be described.

FIG. 3 is a sectional view including a partial circuit wiring diagram of the second embodiment of the present invention, and FIG. 4 is a circuit diagram of the second embodiment. In FIGS. 3 and 4, the same or similar portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and thus the duplicated description will be omitted.

In FIG. 3, a third N-type well 7 which serves as a diffusion layer 7 of the protective resistance element 54 for protecting the PMOSTr 51 is provided.

In the protective resistance element 54 for protection, the third N-type well 7 is diffused and formed simultaneously with the first and second N-type wells 4 and 6, and the N-type impurity concentration in the surface region 34 is It is 1 × 10 ¹⁵ / cm ³ , and N ⁺ type impurity regions 18 and 19 are formed from the main surface 3 into the third N type well 7 which is the resistance diffusion layer 7. A current of the third N-type well 7 is formed on the surface region 34 that functions as a flow resistor, and a polysilicon gate electrode 28 is formed via a gate oxide film 27 having a film thickness of 10 to 70 nm. The sidewall insulating film 2 is formed on both sides of the gate electrode 28.
9 is formed. The N ⁺ type impurity region 18 is connected to the output terminal 43, and the P ⁺ type drain 1 of the PMOSTr 51 is connected.
3 is not connected to the output terminal 43 but is connected to the N ⁺ type impurity region 19 of the protective resistance element 54. The gate electrode 28 of the protective resistance element 54 is connected to the power supply line 44 and fixed to the ground potential V _GND which is the power supply voltage on the low potential side. Further, the silicide film 30 is formed by the salicide process on the surface of each region of the protective resistance element 54 in the same manner as on the surface of other regions, and is formed simultaneously with other N ⁺ type impurity regions, N ⁺ type source and drain. N done
^The surface impurity concentration in the ⁺ type impurity regions 18 and 19 is 5 ×.
10 ²⁰ / cm ³ and other N ⁻ type regions 15 ′ and 16 ′
And 17 'formed simultaneously with surface impurity concentration of 1 × 1
0 ¹⁷ / cm ³ of N ^- type region 18 'and 19' or connected is formed has a LDD structure.

With such a structure, not only the NMOSTr but also the PMOSTr is protected by the protective resistance element.

[0029]

As described above, according to the present invention, when a surge voltage is externally applied to the output terminal, the CM
The protective resistance element connected in series to the drain of the MOSTr in order to prevent electrostatic breakdown of the MOSTr forming the OS is formed on the surface of the diffusion layer and the diffusion layer formed on the semiconductor substrate via a gate insulating film. And a fixed potential gate electrode. Therefore, even if the salicide process is used for speeding up the CMOS, the silicide film is not formed on the surface region of the diffusion layer of the protective resistance element because the gate electrode structure is provided on this surface region. As a result, it is possible to avoid an undesired decrease in the resistance value in the surface region, and it is possible to obtain a predetermined resistance value sufficient for reducing the wave height of the surge voltage with the diffusion layer having a small area. Also,
On the surface area of the diffusion layer of the protective resistance element, 10 nm to
A thin gate insulating film having a thickness of 70 nm is formed, and a thick oxide film for separating element regions formed by the selective oxidation method is not formed. Therefore, the margin at the end of this thick oxide film is reduced (for example, the margin of 0.5 μm on one side is 0).
It enables high integration. Further, the problem of carrier trapping due to crystal disorder at the end of the thick oxide film does not occur.

By maintaining the gate electrode of the protective resistance element at a fixed potential, the protective resistance element has a stable resistance value. That is, an insulating film such as an interlayer insulating film or a passivation film is formed on the surface of the diffusion layer of a general protective resistance element. In this case, electrons in the diffusion layer (when the diffusion layer is N-type) are trapped in an insulating film such as a silicon oxide film, which changes the current flowing through the surface region of the diffusion layer that determines the resistance value, resulting in output characteristics. It fluctuates. On the other hand, in the present invention, such a problem does not occur because the gate electrode is formed on the gate insulating film and the gate electrode is fixed to, for example, V _DD having a positive potential. The film thickness of the gate insulating film of the present invention is determined by the condition that the above-mentioned inconvenience does not occur and the withstand voltage between the gate electrode and the diffusion layer.
It is preferable to determine from the range of nm.

[Brief description of drawings]

FIG. 1 is a sectional view including a partial circuit wiring diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of FIG.

FIG. 3 is a sectional view including a partial circuit wiring diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of FIG.

5A and 5B are views showing a conventional technique, in which FIG. 5A is a sectional view showing a protective resistance element and a CMOS, and FIG. 5B is an enlarged sectional view showing the protective resistance element in FIG. .

FIG. 6 is a circuit diagram of FIG.

FIG. 7 is a sectional view showing another conventional resistance element for protection.

FIG. 8 is a diagram showing a surge voltage waveform.

[Explanation of symbols]

1 P ⁻ Type Silicon Substrate 2 Thick Silicon Oxide Film Partly Embedded from Main Surface of Substrate 2 ′ End of Thick Silicon Oxide Film 3 Main Surface of Silicon Substrate 4 N Type Well (First N Type Well) 5 P Type Well 6 Diffusion layer of protective resistance element (second N-type well) 7 Diffusion layer of protective resistance element (third N-type well) 11 N ⁺ type substrate contact region 12 P ⁺ type source 13 P ⁺ type drain 14 P ⁺ type substrate contact region 15 N ⁺ type source 15 ′, 16 ′, 17 ′, 18 ′, 19 ′ N ⁻ type region 16 N ⁺ type drain (N ⁺ type impurity region) 17, 18, 19 N ⁺ type Impurity regions 21,23 Gate oxide films 22,24 Gate electrodes 25,27 Gate insulating films 26, 28 of protective resistance elements Gate electrodes of protective resistance elements 29 Sidewall insulating films 30 Silicide films 31, 32 Channel regions 3 The surface region 41 of the diffusion layer 34 protective resistance element V _DD supply line 42 input node 43 output terminal 44 V _GND power supply line 51 PMOSTr 52 NMOSTr 53,54 protective resistance element 55 and 56 protection diode 60 for protecting the resistance element 61 N type well 62 N ⁺ type diffusion region 63 Interlayer insulating film 64,65 Contact hole 66,67 Aluminum wiring 68,69 Contact part 70 Protection resistor element 71 N type well 72,73 N ⁺ type impurity region 80 Input to output terminal Waveform of surge voltage 90 Waveform of surge voltage passing through protective resistance element

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/822 27/06 27/08 331 F 9170-4M 9170-4M H01L 27/06 311 A

Claims (8)

[Claims] 1. A CMO is formed by serially connecting a P-channel type insulated gate field effect transistor and an N-channel type insulated gate field effect transistor on a semiconductor substrate.
In a semiconductor device comprising a protective resistance element which constitutes S and which constitutes a protection circuit between an output terminal formed on the semiconductor substrate and the CMOS, the protective resistance element is a diffusion element formed on the semiconductor substrate. A semiconductor device having an output circuit of CMOS structure, characterized in that it has a layer and a gate electrode having a fixed potential formed on the surface of the diffusion layer via a gate insulating film. 2. A P-type well for forming the N-channel type insulated gate field effect transistor on the semiconductor substrate,
A first N-type well forming the P-channel type insulated gate field effect transistor and a second N-type well serving as the diffusion layer of the protective resistance element are provided. 2. A semiconductor device having the output circuit having the CMOS structure according to 1. 3. The second N-type well is provided in contact with the P-type well, and the N-type drain of the N-channel insulated gate field effect transistor is the P-type well and the second N-type. An N-type impurity region formed in a well and connected to the output terminal is formed in the second N-type well, and the second N-type region between the N-type drain and the N-type impurity region is formed. 3. The semiconductor device having an output circuit having a CMOS structure according to claim 2, wherein the gate electrode is formed on the surface of the mold well via a gate insulating film. 4. The gate electrode of the protective resistance element is P of the P channel type insulated gate field effect transistor.
The C according to claim 2 or 3, wherein the power source voltage on the high potential side is fixed together with the mold source.
A semiconductor device having an output circuit having a MOS structure. 5. The N-type source and N-type drain of the N-channel type insulated gate field effect transistor and the N-type impurity region of the protective resistance element have an LDD structure. CMOS described
Semiconductor device having an output circuit having a configuration. 6. A P-type well forming the N-channel type insulated gate field effect transistor on a semiconductor substrate, a first N-type well forming the P-channel type insulated gate field effect transistor, and a first protection. A second N-type well forming the diffusion layer of the protective resistance element and a third N-type well forming the diffusion layer of the second protective resistance element are provided. A semiconductor device having the output circuit having the CMOS structure according to claim 1. 7. The second N-type well is provided in contact with the P-type well, and the N-type drain of the N-channel type insulated gate field effect transistor has the P-type well and the second N-type well. A first N-type impurity region formed in a well and connected to the output terminal is formed in the second N-type well, and between the N-type drain and the first N-type impurity region. A gate electrode of the first protective resistance element is formed on the surface of the second N-type well via a gate insulating film, and is connected to the P-type drain of the P-channel type insulated gate field effect transistor. Second N-type impurity region and a third N-type impurity region connected to the output terminal are formed in the third well, and between the second N-type impurity region and the third N-type impurity region. Of the third
7. The semiconductor device having an output circuit of CMOS structure according to claim 6, wherein the gate electrode of the second protective resistance element is formed on the surface of the N-type well via the gate insulating film. . 8. The gate electrode of the first protective resistance element is fixed to a high-potential-side power supply voltage together with the P-type source of the P-channel insulated gate field effect transistor, and the second protective resistance element is provided. The gate electrode of the resistance element is the N-type of the N-channel insulated gate field effect transistor.
8. The C according to claim 6 or 7, wherein the mold source and the mold source are fixed to a low-potential-side power supply voltage.
A semiconductor device having an output circuit having a MOS structure.