JPH03238919A - Output circuit - Google Patents

Abstract

PURPOSE:To decrease the dispersion in the manufacture by using a resistor to control the time required for the rise and fall of a gate input signal of a transistor(TR) driving an output load. CONSTITUTION:When the channel widths of an N-channel MOS transistor(TR) 7 and a P-channel MOS TR 12 are decided respectively so as to decrease sufficiently the on-resistance of the TRs in comparison with the resistance of resistors 17, 18, the time required for the fall of the signal 6 and the time required for the rise of the signal 6 are respectively decided by the resistance of the resistor 17, the gate capacitance of the P-channel MOS TR 8 and the gate capacitance of the N-channel MOS TR 15 and the resistance of the resistor 18. The dispersion is almost limited in the thickness direction by widening the width of the resistors 17, 18 and the dispersion in the resistance is limited almost to 10% usually. Thus, the dispersion in the manufacture of components is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit used in a semiconductor integrated circuit.

[Prior Art] FIG. 2 is a circuit diagram of a conventional example of the most typical CMOS tri-state output circuit.

This output circuit includes a NOR circuit 3, a NAND circuit IO, and a P
An inverter circuit 4 is composed of a type MOS transistor 5 and an N type MOS transistor, and receives the output of the NOR circuit 3 as an input, a P type MOS transistor 12, and an N type MOS transistor.
An inverter circuit 11 which is composed of a transistor 14 and receives the output of the NAND circuit 1O, a P-type MOS transistor 8 whose source is connected to the power supply and whose gate receives the output of the inverter circuit 4, and whose source is grounded. and an N-type MoS transistor 15 whose gate receives the output of the inverter circuit 11, and a P-type MOS transistor 15.
The drain of the S transistor 8 and the drain of the N-type MOS transistor 15 are connected to form an output 16.

Next, the operation of this output circuit will be explained.

First, the OE signal 2 is at “L” level, and the OE signal 9 is at “H” level.
In the case of level, sense amplifier output 1 remains as signal 6.
When the sense amplifier output l is "H", the output 16 is "L", and when the sense amplifier output 1 is "L", the output 16 is "H".6 Next, the OE signal 2 is "H". When the OE signal 9 is at the "L" level, the signal 6 is fixed at "H" and the signal 13 is fixed at "L" regardless of the sense amplifier output 1, and the P-type MOS transistor 8 and the N-type MOS transistor 15 is turned off, and the output 16 becomes a high impedance state.

[Problems to be Solved by the Invention] The conventional output circuit described above has problems with the power supply line during output transition,
In order to reduce the fluctuation of the GND line and the through current of the power supply = P-type MOS transistor 8 - N-type MOS transistor 15 - GND path, the rise time of signal 6 is made small, the fall time is made large, and signal 13 Because it is necessary to increase the rise time and decrease the fall time of
The method of making S transistor 7 and P-type MOS transistor 14 into high conduction resistance transistors has been most often used.

However, since the variation in transistor manufacturing (the variation in high conduction resistance is usually about 30%) is relatively large, the variation in the fall time of the inverter circuit 4 and the rise time of the inverter circuit 13 is also large, and as a result, the power supply This increases the variation in the effect of reducing fluctuations in the GND line and the GND line, and the effect of reducing through current.

[Means for Solving the Problems] The output circuit of the present invention includes a drain of a first P-type MOS transistor whose source is connected to a power supply, and a first N-type MOS transistor whose source is grounded.
a first inverter circuit with a first resistor connected between the drain of the transistor and the drain of the first P-type MOS transistor as an output; and a second P-type MOS transistor with a source connected to a power supply. A second N-type MOS whose drain and source are grounded
A second inverter circuit, in which a second resistor is connected between the drain of the transistor and the drain of the second N-type MOS transistor as an output; and a source is connected to the power supply, and the output of the first inverter circuit is The third P-type MOS transistor has a third P-type MOS transistor connected to its gate, and a third N-type MOS transistor whose source is grounded and whose gate is connected to the output of the second inverter circuit. The drain of the transistor and the drain of the third N-type MOS transistor are connected to form an output.

[Function] The present invention uses a resistor to control the time required for the rise and fall of a gate signal of a transistor that drives an output load.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an output circuit which is an embodiment of the present invention.

The only difference between this embodiment and the conventional example shown in FIG. 2 is the inverter circuit 4.11 to which a resistor 17.18 is added. Now, if the channel widths of the N-type MOS transistor 7 and the P-type MOS transistor 12 are determined so that the resistance when turned on is sufficiently small compared to the resistors 17 and 18, then the time required for the fall of the signal 6 is The time required for the rise of signal 6 and 6 is the resistance 17
is determined by the gate capacitance of the P-type MOS transistor 8, the gate capacitance of the resistor 18, and the N-type MOS transistor 15. Resistance 17.18 can be realized using polysilicon, a diffusion layer, etc., but in any case, by widening the width, the variation will be almost only in the thickness direction, and the variation in resistance value will usually be suppressed to about 10%. It will be done.

[Effects of the Invention] As explained above, the present invention uses a resistor to control the time required for the rise and fall of the gate input signal of the transistor that drives the output load, thereby reducing manufacturing variations in the time. Therefore, the effect of reducing fluctuations in the power supply line and the GND line during output transition and the through current of the output section can be reduced, and an output circuit with small manufacturing variations can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 5, 8.12...P-type MOS transistor, 7, 14
．． 15...N-type MOS transistor, 17.18...
・Resistance, 3...NOR circuit, IO...NAND circuit, 4.11-...Inverter circuit, 1...Sense amplifier output, 16...Output, 6.13...Signal, 2 ...OE flaw signal 9...OE flaw signal

Claims (1)

[Claims] 1. The drain of a first P-type MOS transistor whose source is connected to a power supply, and the first N-type MOS transistor whose source is grounded.
a first inverter circuit in which a first resistor is connected between the drain of the OS transistor and the drain of the first P-type MOS transistor as an output; and a second P-type MOS transistor whose source is connected to a power supply. A second N-type MOS whose drain and source are grounded
A second inverter circuit, in which a second resistor is connected between the drain of the transistor and the drain of the second N-type MOS transistor as an output; and a source is connected to the power supply, and the output of the first inverter circuit is The third P-type MOS transistor has a third P-type MOS transistor connected to its gate, and a third N-type MOS transistor whose source is grounded and whose gate is connected to the output of the second inverter circuit. An output circuit in which the drain of the transistor and the drain of the third N-type MOS transistor are connected to form an output.