JPH09130232A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately detect leakage current by supplying a voltage formed by two transistors operated in sub-threshold areas to the gate of a leakage current detection transistor. SOLUTION: In order to generate a gate voltage Vbn toward an N channel MOS transistor MLn , without using any resistor, a voltage Vb is formed by two transistors M1n and M2n operated in the sub-threshold areas. In this case, when the drain of the N channel MOS transistor M1n is connected to the substrate terminal of the N channel MOS transistor M2n , the threshold values of both the transistors are almost eliminated, and the leakage current detection magnification of the N channel MOS transistor can be designed by the ratio of channel width between both the transistors M1n and M2n without being affected by the fluctuation of supply voltage or the dispersion of device at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and particularly to a low voltage CMOS LSI.

[0002]

2. Description of the Related Art As an effective method for reducing the power consumption of a CMOS integrated circuit, a method for lowering the power supply voltage has been proposed. However, when the power supply voltage is lowered, the operating speed of the CMOS circuit becomes largely dependent on the threshold value (V _th ) of the MOS transistor. For example, in the case of a 3.3 V power supply, the circuit speed is 5 even if V _th increases by 0.15 V.
% It will be delayed. However, in the case of a 1V power source, the circuit operating speed is twice as high as the above, for the same _Vth fluctuation.
It will be 0% slower.

In consideration of such circumstances, a circuit technique for reducing the variation of V _th has been developed. References: Kobayashi, T. and Sakurai, T., “Self-Adjusti
ng Threshold-Voltage Scheme (SATS) for Low-Voltage
High-Speed Operation. ”Proc. IEEE 1994 CICC, pp.271
The circuit described in -274, May 1994 uses the leak current detection circuit of the LSI and the substrate bias circuit to perform the following operations. That is, when V _th is lower than the target value, the leak current increases above the target value, so the detected leak current becomes higher than the set value. As a result, the substrate bias circuit is activated, the substrate bias is deepened, and V _th is corrected to be high. Conversely, when V _th is higher than the target value, the leak current decreases below the target value, so the detected leak current becomes smaller than the set value. As a result, the operation of the substrate bias circuit stops, the substrate bias becomes shallow, and V _th is corrected to be low. Thus, a MOS manufactured to V _th = ± 0.15 V
The variation in V _th of the transistor is ± 0.05 depending on the circuit technology.
Can be reduced to V.

The drain current of the MOS transistor in the subthreshold region, that is, in the state where it is loosely turned on, is expressed by the following equation.

[0005]

(Equation 1) Here, S in the equation (1) is a so-called S parameter (also called tailing coefficient), and indicates the value of V _GS required to reduce the leak current by one digit. This S
The parameters are

[0006]

(Equation 2) It is expressed as V _TC in equation (1) is the channel width W
the transistor of _o, a V _GS when the constant drain current I _o there begins to flow. From equation (2), it can be seen that S depends on temperature.

Therefore, the leak current of the LSI is expressed by the following equation.

[0008]

(Equation 3) FIG. 13 shows the configuration of a conventional leak current detection circuit.

In this circuit, a drain of a P-channel MOS transistor M _{1p having} a gate grounded and a source connected to a power supply, and an N source serving as a load having a grounded source.
A predetermined voltage V ₀ is applied to the connection point with the drain of the channel MOS transistor M _Ln , and the output voltage V _b of the resistance voltage dividing circuit composed of the resistors R1 and R2 is applied to the gate thereof. The N-channel MOS transistor M _Ln is a leak current detecting transistor. The two transistors on the right side of M _Ln represent the entire LSI equivalently, and a P-channel MOS transistor M _{1pa whose} gate is grounded and whose source is connected to a power supply, and whose gate and source are grounded and whose drain is P It is represented by an N-channel MOS transistor M _LSI connected to the drain of the channel MOS transistor M _1pa .

The leak current detected by the leak current detection circuit is given by the following equation from equation (1).

[0011]

(Equation 4) Here, the input voltage V _b is given by the following equation.

[0012]

(Equation 5) Therefore, the ratio of the leak current of the entire LSI to the leak current detected by the leak current detection circuit (hereinafter referred to as the leak current detection magnification) is as follows.

[0013]

(Equation 6)

[0014]

As is apparent from the equation (6), in the conventional leakage current detection circuit, the leakage current detection magnification depends on the power supply voltage V _DD and the temperature (S depends on the temperature as described above). However, the leak current of the LSI could not be accurately detected.

Further, the leak current detecting MOS transistor M _Ln requires a large channel width (W _{LC M} ).
Therefore, since the capacitance parasitic on the drain of M _Ln is large, while the current (I _Ln.LLCM ) flowing in M _Ln is small, the response time of the leak current detection circuit becomes very long, and the convergence of the above substrate bias control is _reduced . Was not good. Further, since the input voltage _Vb is obtained by resistance voltage division, a resistor having a large resistance value is required to reduce the consumption of the current _Ibn flowing through the resistor. For example, the current I _bn is 1 μ
To set to A, when V _DD = 3V, R1 and R2 are 3MΩ
Need resistance. Generally, a diffusion layer creates resistance,
If the sheet resistance of the diffusion layer is 100Ω, a layout pattern having a width of 1 μm and a length of 30 mm is required, which occupies a large area and violates the request for miniaturization and high integration.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit including a leak current detection circuit having a leak current detection magnification that does not depend on power supply voltage, temperature, or manufacturing variations.

Another object of the present invention is to provide a semiconductor integrated circuit device including a leak current detection circuit which can operate at high speed and can be laid out with a small pattern area.

[0018]

According to the present invention, there is provided a first first conductivity type MOS transistor having a source connected to a first power supply and a drain terminal connected to a second power supply through a load. A second first conductivity type MOS transistor having a drain connected to the gate of the first first conductivity type MOS transistor, a source connected to the first power supply, and a gate connected to the first current source. And a third first-conductivity-type MOS transistor having a source connected to the gate of the first first-conductivity-type MOS transistor, a drain connected to the first current source, and a gate connected to the drain. The absolute value of the difference between the gate potential of the second first conductivity type MOS transistor and the potential of the first power supply is equal to or smaller than the threshold voltage of the second and third first conductivity type MOS transistors. In the Kunar so is characterized in that the said second and third first-conductivity type MOS transistor to drive a sub-threshold region.

In this mode, the two transistors are operated in the sub-threshold region to generate the input voltage _Vb of the leak current detecting transistor. Therefore, the leak current detection magnification depends on the power supply voltage and the temperature. Disappear. Thus, the leak current of the N channel MOS transistor or the P channel MOS transistor of the LSI can be accurately detected. Further, since _Vb can be generated by a transistor without using a resistor, the leak current detection circuit can be laid out with a small pattern area.

According to a second aspect of the present invention, a source is a first first-conductivity-type MOS transistor whose source is connected to a first power supply, and a drain is the first first-conductivity-type MOS transistor.
A second first-conductivity-type MOS transistor connected to the gate of the transistor, having a source connected to the first power supply, and having a gate connected to the first current source; and a source having the first first-conductivity type A third first-conductivity-type MOS transistor connected to the gate of the MOS transistor, the drain thereof connected to the first current source, and the gate thereof connected to the drain; and the source of the first first-conductivity-type MOS transistor. A fourth first-conductivity-type MOS transistor having a gate connected to a second power supply via a load and a gate supplied with a predetermined potential.
The absolute value of the difference between the gate potential of the first conductivity type MOS transistor and the potential of the first power source is equal to or smaller than the threshold voltage of the second and third first conductivity type MOS transistors. Second and third first conductivity type M
The OS transistor is driven in a subthreshold region, and the fourth first conductivity type MOS is provided.
The channel width of the transistor is set to the first conductivity type MO
It is characterized in that it is smaller than the channel width of the S transistor.

In this mode, in addition to the same operation as in the first mode described above, the potential of the drain terminal of the leak current detection MOS transistor is clamped, and the leak current detection MO
The potential at the drain of the S transistor has a small amplitude. As a result, the NMOS transistor of the LSI or PMO
The leak current of the S transistor can be detected at high speed.

Further, according to the third aspect of the present invention, a MOS transistor is used as a load of the leak current detecting circuit, and the gate potential thereof can be freely controlled from outside the chip through an external terminal. Thus, the leakage current detection magnification can be set freely.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, some embodiments of the present invention will be described in detail.

FIG. 1 shows the configuration of the first embodiment of the semiconductor integrated circuit device according to the present invention. This semiconductor integrated circuit device is shown in FIG. 13 in that an N-channel MOS transistor M _Ln is provided for detecting a leak current with respect to an N-channel MOS transistor M _LSI which is equivalent to an LSI.
It is the same as the prior art of. In order to generate the gate voltage V _bn for the N-channel MOS transistor M _Ln ,
Source-grounded N-channel MOS transistor M
And _1n, a current source M _gp is connected to the drain, source is provided and the N-channel MOS transistor M N-channel MOS transistor M _2n connected to the drain of _1n, the gate terminal and the N-channel N-channel MOS transistor M _1n The gate terminal of the MOS transistor M _2n , the drain terminal of M _{2n and} the drain terminal of the current source M _gp are connected, and the connection point between the drain terminal of the N-channel MOS transistor M _1n and the source terminal of the N-channel MOS transistor M _2n is N.
It is connected to the gate of the channel MOS transistor M _Ln .

Here, the N-channel MOS transistor M
_1n and the N-channel MOS transistor M _2n operate in the subthreshold region so that the current value I _bp of the current source M _gp is
The channel widths of the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n are selected. When so set, the potential difference between V _gn , which is the potential of the gate terminal of the N-channel MOS transistor M _1n , and the ground potential GND is N-channel MOS transistors M _1n and N _1.
It is substantially equal to or smaller than the threshold voltage of the channel MOS transistor M _2n .

In the semiconductor integrated circuit device according to the first embodiment of the present invention thus configured, the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n operate in the subthreshold region.
The drain current is expressed by equation (1), and since both are equal,

[0027]

(Equation 7) Becomes

Here, as shown in FIG. 2A, the drain of the N-channel MOS transistor M _1n and the N-channel MO are formed.
When the substrate terminals of the S-transistor M _2n are connected, there is almost no difference between the thresholds of the two transistors. Therefore, the approximation of equation (7) holds. In this case, the LSI N
The leak current detection magnification of the leak current of the channel MOS transistor is

[0029]

(Equation 8) Therefore, the channel widths W1 and W2 of the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n are completely unaffected by the fluctuation of the power supply voltage and the fluctuation of the device.
It can be designed in the ratio of.

However, to enable the circuit connection shown in FIG. 2A, the substrate of the N-channel MOS transistor M _{1n and} the substrate of the N-channel MOS transistor M _2n must be electrically separated. When the two are not electrically separated from each other, the circuit connection is such that the substrate terminals of the both are connected as shown in FIG. In this case, the substrate bias is applied to the N-channel MOS transistor M _2n , so that the N-channel M-transistor is affected by the back gate effect.
The threshold value of the OS transistor M _2n is slightly higher than that of the N-channel MOS transistor M _1n . as a result,
The approximation of equation (7) is no longer valid. Therefore, the leak current detection magnification has a slight temperature dependency. To solve this, reverse bias is applied to the common substrate of the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n as shown in FIG. 2C, and this dependency can be further reduced. .

FIG. 9 shows a simulation result of the V _bn -I _bn characteristic of FIG. As shown in equation (7), the potential difference between the gate potential V _g of the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n and the ground potential GND is the N-channel MOS transistor M _1n and the N-channel MOS transistor.
In the subthreshold region where the threshold voltage V _thn of the transistor M _2n is smaller than V _thn = 0.55 V, V _b has a constant value without depending on the current I _b . That is, _Vb is not affected by the fluctuation of the power supply voltage or the variation of the device at all, and the N-channel MOS transistor M _1n , the N-channel MOS transistor
It is determined only by the channel width ratio W2 / W1 of the transistor M2n.

FIG. 10 shows a result of simulating the characteristics of the V _b N-channel MOS transistor (W2 / W1) of FIG. A case where the substrate potential of the N-channel MOS transistor M _{1n and} the substrate potential of the N-channel MOS transistor M _2n are electrically separated and the substrate bias of the N-channel MOS transistor M _2n is not applied (see FIG. 2A) is indicated by a broken line. Show. On the other hand, the N-channel MOS transistor M _1n
The solid line indicates a case where the substrate potentials of M _2n and M _2n cannot be electrically separated and a substrate bias is applied to M _2n (see FIG. 2B). In the latter case, the threshold value of M _2n becomes a little higher due to the substrate bias effect, the term of (V _TC1 −V _TC2 ) in the equation (7) does not become zero, and takes a negative value, so it is a little lower than the former case. It becomes a value.
Therefore, although it has a slight temperature dependency, the actual use is within a range that has no influence depending on the application.

FIG. 3 shows a second embodiment of the present invention constructed by reversing the conductivity type of the transistor in the configuration of FIG.

A P-channel MOS transistor (M _1p ) whose source is connected to a power supply to generate a gate voltage V _bp for the leak current detection P-channel MOS transistor M _Lp and a current source M _gn are connected to its drain. is a source connected P-channel MOS transistor and (M _2p) is provided on the drain of the P-channel MOS transistor M _1p, gate terminals and M of P-channel MOS transistor M _1p the gate terminal and the P-channel MOS transistor M _2p
The drain terminal of _{2p and} the drain terminal of M _gn are connected, and P
Connection point between the source terminal of the drain terminal and the P-channel MOS transistor M _2p channel MOS transistor M _1p is connected to the gate of the P-channel MOS transistor MLP.

Here, the P-channel MOS transistor M
_1p and the P-channel MOS transistor M _2p operate in the subthreshold region so that the current value of the current source I _bp and P
Channel MOS transistor M _1p and P channel MO
The channel width of the S-transistor M _2p is chosen. When so set, the potential difference between the power supply potential and the potential V _gp of the gate terminal of the P-channel MOS transistor M _1p is _equal to that of the P-channel MOS transistor M _1p and the P-channel M transistor.
It is substantially equal to or smaller than the threshold voltage of the OS transistor M _2p .

Also in this case, the LSI is exactly the same as in the case of FIG.
The leak current of the P-channel MOS transistor can be detected.

Next, FIG. 4 shows the configuration of a third embodiment of the semiconductor integrated circuit device according to the present invention. This semiconductor integrated circuit device _differs from the configuration of FIG. 1 in that an N-channel MOS transistor M _c1n is connected between the drain of the load transistor M _{1p and} the drain of the N-channel MOS transistor M _Ln , and the gate thereof has the source of M _3n . Is connected to GND and the drain and gate are connected to the drain of the N-channel MOS transistor M _c1p which is the second current source.
The gate of the OS transistor M _3n is connected. Here, the channel width of the N-channel MOS transistor M _c1n is made smaller than the channel width of the N-channel MOS transistor M _Ln , and the potential difference between the gate terminal potential V _{cn of} the N-channel MOS transistor M _3n and the ground potential GND is reduced. The N-channel MOS transistor M _3n and the N-channel MOS transistor M _{c1n have} N-channel MOS transistors that are substantially equal to or larger than the threshold voltage.
Transistor M _3n and N-channel MOS transistor M
A channel width of _c1n is chosen. However, N channel MO
If the channel width of the S-transistor M _3n is too small, a problem with accuracy occurs, so it is necessary to maintain an appropriate width.

In the above-described first embodiment, the potential of the drain of M _Ln charged through the load M _1p is taken out as V _o , so that delay occurs in charging the drain capacitance of M _{Ln having} a large channel width.

On the other hand, in the third embodiment, the load M
The source-drain capacitance of M _c1n and the drain capacitance of M _Ln are charged through _1p , and the potential of the drain of M _c1n is taken out as V _o . In this case, the potential of the drain of M _Ln is the potential V of the gate terminal of M _3n due to the clamp action.
_There is no difference between _cn and the threshold value of M _Ln , and the charging time of the drain capacitance of M _Ln is greatly shortened. Moreover, the potential of the drain of M _{c1n having} a channel width smaller than that of M _Ln is set to V _o.
The charging time is quick because it is taken out as. In other words, V _o
Since the capacitance to be charged when looking inside the circuit is the drain capacitance of M _c1n , the response is improved.

Therefore, even if the delay time is the sum of the charging times of the drain capacitances of M _Ln and M _c1n , the speedup can be achieved as compared with the first embodiment.

FIG. 5 shows a modification in which the number of transistors between the load M _1p and the ground is increased by one stage, and the other structure is exactly the same as that in the case of FIG.

This modification solves the problem that it is difficult to increase the gate voltage of the N-channel MOS transistor M _c1n in the case of FIG. 4, and the low gate voltage _limits the charging current. Is. For this reason,
5 is connected to drain and gate to the source of the transistor M _3n to increase the gate voltage, the source has to add another stage transistors M _4n which is grounded, due to the two transistors M _3n and M _4n By the voltage clamping action, the gate voltage of the transistor M _c1n can be increased to further increase the speed.

FIG. 6 shows a fourth embodiment in which the conductivity type of each transistor in the configuration of FIG. 4 is inverted so that the leak current of the P-channel MOS transistor of the LSI can be detected. The configuration and operation are as follows. Since it is almost the same as the case of FIG. 4, detailed description will be omitted.

[0044] Figure 7 shows a modification of the embodiment of FIG. 6, to increase the gate voltage of the transistor M _C1P to be charged in order to output the same manner V _o in the case of FIG. 5, the transistor M _{4p Is} inserted between the power supply and the transistor M _3p to improve the speed.

Next, FIG. 8 shows the configuration of a fifth embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the potential of the gate terminal of the N-channel MOS transistor M _1p which is the load transistor in the first embodiment is not the ground potential GND but the external input terminal PAD so that an arbitrary voltage can be applied from the outside. The leak current can be detected at an arbitrary value according to the external input voltage. FIG. 11 is a chart showing the results of performance comparison between the present invention and the prior art by simulation at V _th = 0.2V. In this chart, VDD dependency is VDD = 3.3V ± 0.3V, temperature dependency is 0 to 7
At 0 ° C., V _thn dependence is V _thn = 0.2 V ± 0.1 V, and what percentage of leakage current detection magnification is under standard conditions
It shows whether it fluctuates. It can be seen that if each of the items adopts the configuration of FIGS. 1 and 4, it will be substantially 1/10, which is a significant improvement. Further, in the configuration of FIG. 4, the response time is reduced to 1/4 as compared with the configuration of FIG. 1 which is equivalent to the conventional circuit. Further, in the present invention, it is understood that the area is reduced to 1/60, because the resistance unlike the conventional circuit is unnecessary.

Various modifications can be made to the above embodiments. For example, although the current sources are all described as active devices, resistors R1 and R1 are used as shown in FIG.
2, R3 can also be used. Further, the configuration of the present invention can be adopted in each well of both conductivity types of the CMOS circuit.

[0047]

As described above, according to the present invention, since the voltage formed by the two transistors operated in the subthreshold region is supplied to the gate of the leak current detecting transistor, the leak current detecting transistor is detected. The magnification does not depend on the power supply voltage or the temperature, and the leak current can be accurately detected.

Further, since it can be generated by a transistor without using a resistor occupying a large area, the leak current detecting circuit can be laid out with a small pattern area.

Further, in the present invention further provided with a structure for clamping the potential of the drain terminal of the leak current detecting MOS transistor, the potential at the drain of the leak current detecting MOS transistor has a small amplitude, so that the leak current detection is speeded up. it can.

Further, in the present invention in which the MOS transistor whose gate potential can be freely controlled from the outside of the chip via the external terminal is used as the load of the leakage current detection circuit, the leakage current detection magnification can be freely set. Is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating how to apply a substrate potential in the configuration of FIG.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a modified example of FIG.

FIG. 6 is a circuit diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a modified example of FIG.

FIG. 8 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

9 is a graph showing a result of simulating the V _bn -I _bn characteristic of FIG. 1.

FIG. 10 is a graph showing the results of simulating the V _bn − (W2 / W1) characteristic of FIG. 1.

FIG. 11 is a chart showing the results of performance comparison between the present invention and the conventional invention by simulation at V _th = 0.2V.

FIG. 12 is a circuit diagram showing a configuration using a resistor as a current source in the first embodiment.

FIG. 13 is a circuit diagram showing a configuration of a conventional leak current detection circuit.

[Explanation of symbols]

M _1n , M _2n , M _3n , M _4n n-channel MOS transistor M _gp , M _gn current source M _1p , M _2p , M _3p , M _4p p-channel MOS transistor _MLp , _MLn leak detection transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H03K 19/094

Claims (36)

[Claims] 1. A first first power source connected to a first power source, and a drain terminal connected to a second power source through a load.
A second conductivity type MOS transistor having a drain connected to the gate of the first first conductivity type MOS transistor, a source connected to the first power supply, and a gate connected to the first current source; A first conductivity type MOS transistor, and a third first conductivity type whose source is connected to the gate of the first first conductivity type MOS transistor, drain is connected to the first current source, and gate is connected to the drain. Type M
An OS transistor, wherein the absolute value of the difference between the gate potential of the second first conductivity type MOS transistor and the potential of the first power supply is the threshold voltage of the second and third first conductivity type MOS transistors. The second and the third so as to be equal to or smaller than
2. A semiconductor integrated circuit device, wherein the first conductivity type MOS transistor is driven in a subthreshold region. 2. The first conductivity type MOS transistor is an N-channel MOS transistor, the first power supply is a low potential power supply, and the second power supply is a high potential power supply. 1. The semiconductor integrated circuit device according to 1. 3. The semiconductor integrated circuit according to claim 2, wherein a substrate potential of the first first-conductivity-type MOS transistor is a P-type well potential which is a conductivity type opposite to the first-conductivity type. apparatus. 4. The first conductivity type MOS transistor is a P-channel MOS transistor, the first power supply is a high potential power supply, and the second power supply is a low potential power supply. 1. The semiconductor integrated circuit device according to 1. 5. The semiconductor integrated circuit according to claim 4, wherein the substrate potential of the first first-conductivity-type MOS transistor is an N-type well potential that is a conductivity type opposite to the first-conductivity type. apparatus. 6. The semiconductor integrated circuit according to claim 1, wherein the substrate terminal of the third first-conductivity-type MOS transistor is connected to the source terminal of the third first-conductivity-type MOS transistor. apparatus. 7. The semiconductor integrated circuit according to claim 2, wherein the substrate terminals of the second and third first-conductivity-type MOS transistors are applied with a potential of the ground power supply or a predetermined potential lower than the potential. Circuit device. 8. The semiconductor integrated circuit according to claim 4, wherein substrate potentials of the second and third first conductivity type MOS transistors are applied with a potential of the power source or a predetermined potential higher than the potential. apparatus. 9. The predetermined potential is provided as a gate output of a fifth first-conductivity-type MOS transistor having a source connected to an installed power supply and a drain and a gate connected to a second current source. The semiconductor integrated circuit device according to claim 7. 10. The fifth device, wherein the predetermined potential is such that a source is connected to a power source and a drain and a gate are connected to a second current source.
9. The semiconductor integrated circuit device according to claim 8, wherein the semiconductor integrated circuit device is provided as a gate output of the first conductivity type MOS transistor. 11. The first current source and the second current source have a gate connected to a ground power supply, a source connected to a power supply, and a drain connected to the third or fifth N-channel M.
10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is a first P-channel MOS transistor connected to the drain of the OS transistor. 12. The first current source and the second current source each have a gate connected to a power supply, a source connected to a ground power supply, and a drain connected to the third or fifth P-channel M.
11. The semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is a first N-channel MOS transistor connected to the drain of the OS transistor. 13. The semiconductor integrated circuit device according to claim 9, wherein the first and second current sources are resistors. 14. The semiconductor integrated circuit device according to claim 10, wherein the first and second current sources are resistors. 15. The load is a second P-channel MOS transistor having a gate connected to the ground power supply, a source connected to the power supply, and a drain connected to the drain of the first or fourth N-channel MOS transistor. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is provided. 16. The load has a gate connected to a power supply,
5. The semiconductor integrated circuit device according to claim 4, wherein the source is a ground power supply and the drain is a second N-channel MOS transistor connected to the drain of the first or fourth P-channel MOS transistor. . 17. A first first-conductivity-type MOS transistor having a source connected to a first power supply, a drain connected to a gate of the first first-conductivity-type MOS transistor, and a source connected to the first A second first-conductivity-type MOS transistor connected to a power source and having a gate connected to a first current source; a source connected to the gate of the first first-conductivity-type MOS transistor; and a drain connected to the first Of the third first conductivity type M connected to the current source of
An OS transistor and a source thereof are connected to a drain of the first first-conductivity-type MOS transistor, a drain thereof is connected to a second power source through a load, and a fourth first gate having a predetermined potential applied to its gate.
A conduction type MOS transistor, wherein an absolute value of a difference between a gate potential of the second first conduction type MOS transistor and a potential of the first power supply is equal to that of the second and third first conduction type MOS transistors. The second and third firsts are set to be equal to or smaller than a threshold voltage.
The conductivity type MOS transistor is driven in the subthreshold region, and the channel width of the fourth first conductivity type MOS transistor is smaller than the channel width of the first first conductivity type MOS transistor. A characteristic semiconductor integrated circuit device. 18. The first conductivity type MOS transistor is N
18. The semiconductor integrated circuit device according to claim 17, wherein the semiconductor integrated circuit device is a channel MOS transistor, the first power source is a low potential power source, and the second power source is a high potential power source. 19. The semiconductor integrated circuit according to claim 18, wherein the substrate potential of the first MOS transistor of the first conductivity type is a P-type well potential which is a conductivity type opposite to the first conductivity type. apparatus. 20. The first conductivity type MOS transistor is P
18. The semiconductor integrated circuit device according to claim 17, wherein the semiconductor integrated circuit device is a channel MOS transistor, the first power supply is a high potential power supply, and the second power supply is a low potential power supply. 21. The semiconductor integrated circuit according to claim 20, wherein a substrate potential of the first first-conductivity-type MOS transistor is an N-type well potential that is a conductivity type opposite to the first-conductivity type. apparatus. 22. The predetermined potential is provided as a gate output of a fifth first-conductivity-type MOS transistor having a source connected to a ground power source and a drain and a gate connected to a second current source. 19. The semiconductor integrated circuit circuit device according to claim 18. 23. A fifth potential of the predetermined potential, the source of which is connected to a power supply and the drain and gate of which are connected to a second current source.
21. The semiconductor integrated circuit circuit device according to claim 20, which is provided as a gate output of the first conductivity type MOS transistor. 24. The substrate terminal of the third MOS transistor of the first conductivity type is connected to the source terminal of the transistor of the MOS transistor of the third first conductivity type.
7. The semiconductor integrated circuit device according to 7. 25. The second and third first conductivity type MOSs
2. A substrate terminal of a transistor is applied with a potential of the ground power source or a potential lower than that.
8. The semiconductor integrated circuit device according to item 8. 26. The second and third first conductivity type MOSs.
21. The semiconductor integrated circuit device according to claim 20, wherein a potential of the power source or a potential higher than that is applied to a substrate terminal of a transistor. 27. The first current source and the second current source each have a gate connected to a ground power supply, a source connected to a power supply, and a drain connected to the third or fifth N-channel M.
23. The semiconductor integrated circuit device according to claim 22, wherein the semiconductor integrated circuit device is a first P-channel MOS transistor connected to the drain of the OS transistor. 28. In the first current source and the second current source, a gate is connected to a power supply, a source is connected to a ground power supply, and a drain is the third or fifth P-channel M.
24. The semiconductor integrated circuit device according to claim 23, wherein the semiconductor integrated circuit device is a first N-channel MOS transistor connected to the drain of the OS transistor. 29. The semiconductor integrated circuit device according to claim 22, wherein the first and second current sources are resistors. 30. The semiconductor integrated circuit device according to claim 23, wherein the first and second current sources are resistors. 31. The load is a second P-channel MOS transistor having a gate connected to the ground power supply, a source connected to the power supply, and a drain connected to the drain of the first or fourth N-channel MOS transistor. 19. The semiconductor integrated circuit device according to claim 18, which is provided. 32. The load has a gate connected to a power supply,
21. The semiconductor integrated circuit device according to claim 20, wherein the source is a ground power source and the drain is a second N-channel MOS transistor connected to the drain of the first or fourth P-channel MOS transistor. . 33. A predetermined potential applied to the gate of the fourth first-conductivity-type MOS transistor is applied as a clamp potential of the first and second power supply voltages by at least two stages of transistors connected in series. The semiconductor integrated circuit device according to claim 17, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 34. A first first-conductivity-type MOS transistor having a source connected to a first power supply and a drain terminal connected to a second power supply through a load; and a drain having the first first conductivity. Second MOS transistor of the first conductivity type, which is connected to the gate of the MOS transistor, the source of which is connected to the first power source, and the gate of which is connected to the current source.
An S-transistor and a third first-conductivity-type MOS transistor having a source connected to the gate of the first first-conductivity-type MOS transistor, a drain connected to the current source, and a gate connected to the drain. The load is a second conductivity type MOS transistor having a gate connected to an external terminal, and the load is a second first conductivity type MO transistor.
The absolute value of the difference between the potential of the gate of the S transistor and the potential of the first power supply is the second and third first conductivity type MOSs.
The second and third first-conductivity-type MOS transistors are driven in the subthreshold region so as to be equal to or smaller than the threshold voltage of the transistor, and the current detection magnification is adjusted by the gate potential set by the external terminal. A semiconductor integrated circuit device characterized by being variable. 35. The load has a source connected to a power supply,
29. The semiconductor integrated circuit device according to claim 28, wherein the drain is a P-channel MOS transistor connected to the drain of the first N-channel MOS transistor. 36. The semiconductor according to claim 35, wherein the load is an N-channel MOS transistor whose source is connected to a ground power source and whose drain is connected to the drain of the first P-channel MOS transistor. Integrated circuit device.