JP3251861B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a low voltage CMOS LSI.

[0002]

2. Description of the Related Art As an effective method of reducing the power consumption of a CMOS integrated circuit, a method of lowering a power supply voltage has been proposed. However, when the power supply voltage is reduced, the operation speed of the CMOS circuit greatly depends on the threshold value (V _th ) of the MOS transistor. For example, in the case of a 3.3V power supply, even if _Vth increases by 0.15V, the circuit speed is 5V.
% Slowdown. However, in the case of a 1 V power supply, the operating speed of the circuit is twice as high as the above, for the same _Vth fluctuation.
0% slows down.

In view of such circumstances, a circuit technique for reducing the variation of _Vth has been developed. For example, references: Kobayashi, T. and Sakurai, T., “Self-Adjusti
ng Threshold-Voltage Scheme (SATS) for Low-Voltage
High-Speed Operation. ”Proc.IEEE 1994 CICC, pp.271
The circuit described in -274, May 1994 performs the following operation using an LSI leak current detection circuit and a substrate bias circuit. That is, when V _th is lower than the target value, the leak current increases beyond the target value, so that the detected leak current becomes higher than the set value. As a result, the substrate bias circuit operates, the substrate bias becomes deep, and _Vth is corrected to be high. Conversely, when V _th is higher than the target value, the leak current decreases below the target value, so that the detected leak current becomes lower than the set value. As a result, the operation of the substrate bias circuit stops, the substrate bias becomes shallow, and _Vth is corrected to be low. Thus, the MOS manufactured at V _th = ± 0.15 V
The variation in _Vth of the transistor is ± 0.05 by circuit technology.
V.

The drain current of a MOS transistor in a sub-threshold region, that is, in a state where it is loosely turned on, is expressed by the following equation.

[0005]

(Equation 1) Here, S in the equation (1) is what is called a so-called S parameter (also referred to as a tailing coefficient), and indicates a value of V _GS required to reduce the leakage current by one digit. This S
The parameters are

[0006]

(Equation 2) It is expressed as V _TC in equation (1) is the channel width W
the transistor of _o, a V _GS when the constant drain current I _o there begins to flow. Equation (2) shows that S depends on the temperature.

Therefore, the leakage current of the LSI is expressed by the following equation.

[0008]

(Equation 3) FIG. 13 shows a configuration of a conventional leak current detection circuit.

In this circuit, the drain of a P-channel MOS transistor _M1p whose gate is grounded and whose source is connected to a power supply, and N as a load whose source is grounded
Predetermined voltage V ₀ is applied to the connection point of the drain channel MOS transistor M _Ln, the output voltage V _b of the resistor divider consisting of resistors R1 and R2 to the gate is provided. This N-channel MOS transistor M _Ln is a transistor for detecting a leak current. The two transistors on the right side of M _Ln equivalently represent the entire LSI, a P-channel MOS transistor M _{1pa whose} gate is grounded and whose source is connected to the power supply, a gate and source are grounded, and a drain is P It is represented by an N-channel MOS transistor M _LSI connected to the drain of the channel MOS transistor M _1pa .

The leak current detected by the leak current detection circuit is given by the following equation from equation (1).

[0011]

(Equation 4) Here, the input voltage _Vb is given by the following equation.

[0012]

(Equation 5) Accordingly, the ratio of the leak current of the entire LSI to the leak current detected by the leak current detection circuit (hereinafter, referred to as a leak current detection magnification) is as follows.

[0013]

(Equation 6)

[0014]

As is apparent from equation (6), in the conventional leak current detection circuit, the leak current detection magnification depends on the power supply voltage _VDD and the temperature (S is dependent on the temperature as described above). ) However, the leak current of the LSI could not be accurately detected.

Further, the MOS transistor M _Ln for detecting a leakage current requires a large channel width (W _{LC M} ).
Therefore, the capacitance parasitic on the drain of M _Ln is large, while the current (I _Ln.LLCM ) flowing in M _Ln is small, so that the response time of the leak current detection circuit becomes very long, and the convergence of the substrate bias control is improved. Was not good. Also, since the input voltage _Vb is obtained by _dividing the resistance, a resistor having a large resistance value is required to reduce the consumption of the current _Ibn flowing through the resistor. For example, if the current I _bn is 1 μm
To make A, when V _DD = 3V, R1 and R2 are 3MΩ
Resistance is required. Generally, a resistor is made with a diffusion layer.
Assuming that the sheet resistance of the diffusion layer is 100Ω, a layout pattern having a width of 1 μm and a length of 30 mm is required, occupying a large area, and contradicting the demand for miniaturization and high integration.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit including a leak current detecting circuit having a leak current detecting magnification which does not depend on a power supply voltage, a temperature, or a manufacturing variation.

Another object of the present invention is to provide a semiconductor integrated circuit device including a leak current detection circuit which can operate at high speed and can be laid out with a small pattern area.

[0018]

According to the present invention, there is provided a first first conductivity type MOS transistor having a source connected to a first power supply and a drain terminal connected to a second power supply via a load. , A drain connected to the gate of the first first conductivity type MOS transistor, a source connected to the first power supply, and a gate connected to the first current source. And a third first conductivity type MOS transistor having a source connected to the gate of the first first conductivity type MOS transistor, a drain connected to the first current source, and a gate connected to the drain. An absolute value of a difference between a gate potential of the second first conductivity type MOS transistor and a potential of the first power supply is equal to or smaller than a threshold voltage of the second and third first conductivity type MOS transistors. In the Kunar so is characterized in that the said second and third first-conductivity type MOS transistor to drive a sub-threshold region.

In this embodiment, since the two transistors are operated in the sub-threshold region to generate the input voltage _Vb of the leakage current detection transistor, the leakage current detection magnification depends on the power supply voltage and temperature. Disappears. This makes it possible to accurately detect the leak current of the N-channel MOS transistor or P-channel MOS transistor of the LSI. Further, since _Vb can be generated by a transistor without using a resistor, the leak current detection circuit can be laid out with a small pattern area.

According to a second aspect of the present invention, a first first conductivity type MOS transistor having a source connected to a first power supply and a drain having the first first conductivity type MOS transistor are provided.
A second first conductivity type MOS transistor connected to the gate of the transistor, the source connected to the first power supply, and the gate connected to the first current source; and the source connected to the first first conductivity type A third first conductivity type MOS transistor connected to a gate of the MOS transistor, a drain connected to the first current source, and a gate connected to the drain, and a source connected to the first first conductivity type MOS transistor And a fourth first conductivity type MOS transistor whose drain is connected to a second power supply via a load and whose gate is given a predetermined potential.
The absolute value of the difference between the potential of the gate of the first conductivity type MOS transistor and the potential of the first power supply is equal to or smaller than the threshold voltage of the second and third first conductivity type MOS transistors. Second and third first conductivity types M
The OS transistor is driven in a sub-threshold region, and the fourth first conductivity type MOS transistor is driven.
The channel width of the transistor is set to the first first conductivity type MO.
The channel width is smaller than the channel width of the S transistor.

In this embodiment, in addition to the same operation as the above-described first embodiment, the potential of the drain terminal of the leakage current detection MOS transistor is clamped, and the leakage current detection MO
The potential at the drain of the S transistor has a small amplitude. This allows the NMOS transistor or PMO of the LSI
The leak current of the S transistor can be detected at high speed.

Further, according to the third aspect of the present invention, a MOS transistor is used as a load of the leak current detecting circuit, and its gate potential can be freely controlled from outside the chip via an external terminal. Thus, the leak current detection magnification can be set freely.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below in detail.

FIG. 1 shows the configuration of the first embodiment of the semiconductor integrated circuit device according to the present invention. This semiconductor integrated circuit device is different from FIG. 13 in that an N-channel MOS transistor M _Ln for detecting a leak current is provided for an N-channel MOS transistor M _LSI equivalently representing an _LSI .
Is the same as the prior art. To generate a gate voltage V _bn for this N-channel MOS transistor M _Ln ,
N-channel MOS transistor M whose source is grounded
And _1n, a current source M _gp is connected to the drain, source is provided and the N-channel MOS transistor M N-channel MOS transistor M _2n connected to the drain of _1n, the gate terminal and the N-channel N-channel MOS transistor M _1n MOS drain terminal of the transistor M _2n drain terminal and the current source M _gp the gate terminal and the M _2n of being connected, the connection point between the source terminal of the drain terminal and the N-channel MOS transistor M _2n of N-channel MOS transistor M _1n is N
It is connected to the gate of the channel MOS transistor M _Ln .

Here, an N-channel MOS transistor M
_1n and the N-channel MOS transistor M _2n operate in the subthreshold region so that the current value I _bp of the current source M _gp is
And the channel widths of N channel MOS transistor M _1n and N channel MOS transistor M _2n are selected. When set as such, the potential difference between V _gn , which is the potential of the gate terminal of N-channel MOS transistor M _1n , and ground potential GND is determined by N-channel MOS transistors M _1n and N ₁
It is almost equal to or smaller than the threshold voltage of the channel MOS transistor M _2n .

In the semiconductor integrated circuit device according to the first embodiment of the present invention, the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n operate in the sub-threshold region.
The drain current is represented by equation (1), and since both are equal,

[0027]

(Equation 7) Becomes

Here, as shown in FIG. 2A, the drain of the N-channel MOS transistor M _1n and the N-channel MOS
When the substrate terminal of the S transistor M _2n is connected, the difference between the threshold values of both transistors is almost eliminated. Therefore, the approximation of Expression (7) holds. In this case, the LSI N
The leak current detection magnification of the leak current of the channel MOS transistor is

[0029]

(Equation 8) Next, not affected at all by the variation of the variation and device of the power supply voltage, the channel width of N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n W1, W2
The ratio can be designed.

However, in order to enable the circuit connection shown in FIG. 2A, the substrate of the N-channel MOS transistor M _1n must be electrically separated from the substrate of the N-channel MOS transistor M _2n . When the two are not electrically separated from each other, a circuit connection is made in which the two board terminals are connected as shown in FIG. In this case, since a substrate bias is applied to the N-channel MOS transistor M _2n , the N-channel MOS transistor M _2n has a back-gate effect.
The threshold value of the OS transistor M _2n is slightly higher than that of the N-channel MOS transistor M _1n . as a result,
The approximation of equation (7) does not hold. Therefore, the leak current detection magnification has a slight temperature dependency. In order to solve this, as shown in FIG. 2C, when a reverse bias is applied to the common substrate of the N-channel MOS transistor M _1n and the N-channel MOS transistor M _2n , this dependency can be further reduced. .

FIG. 9 shows a simulation result of the V _bn -I _bn characteristics of FIG. Wherein the N-channel MOS transistor M _1n as shown in (7), the potential difference between the gate electric potential V _g of the N-channel MOS transistor M _2n and the ground potential GND N-channel MOS transistors M _1n, N-channel MOS
In a sub-threshold region where the threshold voltage V _thn of the transistor M _2n is smaller than 0.55 V, V _b has a constant value independent of the current I _b . That is, _Vb is not affected by the fluctuation of the power supply voltage or the variation of the device at all, and the N-channel MOS transistors M _1n and N ₁
It is determined only by the channel width ratio W2 / W1 of the transistor M2n.

FIG. 10 shows the result of simulating the characteristics of the _Vb N-channel MOS transistor (W2 / W1) shown in FIG. If not to apply N-channel MOS transistor M _1n of the substrate potential and the N-channel MOS transistor M electrically bias the isolation to N-channel MOS transistor M _2n substrate potential of _2n (see FIG. 2 (a)) the dashed line Show. On the other hand, an N-channel MOS transistor M _1n
And indicating if the electrically bias the M _2n can not be separated according to (see FIG. 2 (B)) by the solid line substrate potential of M _2n. In the latter case, the threshold value of M _2n is slightly increased due to the substrate bias effect, and the term of (V _TC1 −V _TC2 ) in equation (7) does not become zero but takes a negative value. Value.
Therefore, it has a slight temperature dependency, but its practical use is within a range that does not affect the application.

FIG. 3 shows a second embodiment of the present invention in which the conductivity type of the transistor in the configuration of FIG. 1 is inverted.

A P-channel MOS transistor (M _1p ) having a source connected to a power supply for generating a gate voltage V _bp for the P-channel MOS transistor M _Lp for detecting leak current, and a current source M _gn connected to a drain. A P-channel MOS transistor (M _2p ) having a source connected to the drain of the P-channel MOS transistor M _1p is provided. The gate terminal of the P-channel MOS transistor M _1p , the gate terminal of the P-channel MOS transistor M _2p , and M
The drain terminal of _{2p and} the drain terminal of _Mgn are connected, and P
Connection point between the source terminal of the drain terminal and the P-channel MOS transistor M _2p channel MOS transistor M _1p is connected to the gate of the P-channel MOS transistor MLP.

Here, a P-channel MOS transistor M
_1p and the P-channel MOS transistor M _2p operate in the subthreshold region so that the current values I _bp and P
Channel MOS transistor M _1p and P channel MO
The channel width of the S transistor _M2p is selected. When set as such, the power supply potential and P-channel MOS transistor M potential difference P-channel MOS transistor with V _gp is the potential of the gate terminal of the _1p M _1p and P-channel M
Approximately equal to or smaller than the threshold voltage of the OS transistor M _2p.

Also in this case, the LSI is the same as in FIG.
Of the P-channel MOS transistor can be detected.

Next, the configuration of a third embodiment of the semiconductor integrated circuit device according to the present invention is shown in FIG. The semiconductor integrated circuit device, to the configuration of FIG. 1, the source of the load transistor M is connected to N-channel MOS transistor M _C1N between drains of N-channel MOS transistor M _Ln of _1p, to the gate M _3n Is connected to GND, and an N-channel MOS transistor whose drain and gate are connected to the drain of an N-channel MOS transistor M _c1p which is a second current source.
The gate of the OS transistor M _3n is connected. Here, the channel width of the N-channel MOS transistor M _c1n is made smaller than the channel width of the N-channel MOS transistor M _Ln , and the potential difference between the potential V _cn of the gate terminal of the N-channel MOS transistor M _3n and the ground potential GND is reduced. An N-channel MOS transistor M _3n and an N-channel MOS transistor M _{c1n so that} the N-channel MOS transistors M _3n and M _c1n have substantially the same or larger threshold voltages.
Transistor M _3n and N-channel MOS transistor M
The channel width of _c1n is chosen. However, N channel MO
If the channel width of the S-transistor M _3n is too small, a problem in accuracy occurs, so it is necessary to maintain an appropriate width.

In the above-described first embodiment, since the potential of the drain of M _Ln charged through the load M _1p is taken out as V _o , a delay occurs in charging the drain capacitance of M _{Ln having} a large channel width.

On the other hand, in the third embodiment, the load M
Charging the drain capacitance of the source-drain capacitance and M _Ln of _M c1n through _1p, so that takes out the potential of the drain of the _M c1n as V _o. In this case, the potential of the drain of M _Ln becomes the potential V ₃ of the gate terminal of M _3n due to the clamping action.
The difference between _cn and the threshold value of M _Ln does not increase, and the charging time of the drain capacitance of M _Ln is greatly reduced. Moreover, the potential of the drain of M _{c1n having} a smaller channel width than M _Ln is set to V _o.
Charging time is fast because it is taken out. In other words, V _o
Since the capacity to be charged when the inside of the circuit is viewed from is the drain capacity of M _c1n , the response is improved.

Therefore, even if the delay time is the sum of the charging times of the drain capacitances of M _Ln and M _c1n , the speed can be increased as compared with the first embodiment.

FIG. 5 shows a modification in which the number of transistors between the load _M1p and the ground is increased by one more stage, and the other configuration is exactly the same as that of FIG.

This modification solves the problem that it is difficult to increase the gate voltage of the N-channel MOS transistor _Mc1n in the case of FIG. 4, and that this low gate voltage _limits the charging current. It is. For this reason,
5 is connected to drain and gate to the source of the transistor M _3n to increase the gate voltage, the source has to add another stage transistors M _4n which is grounded, due to the two transistors M _3n and M _4n The gate voltage of the transistor M _c1n can be increased by the voltage clamping action to further increase the speed.

FIG. 6 shows a fourth embodiment in which the conductivity type of each transistor in the configuration of FIG. 4 is inverted so that the leakage current of the P-channel MOS transistor of the LSI can be detected. Since it is almost the same as the case of FIG. 4, detailed description will be omitted.

[0044] Figure 7 shows a modification of the embodiment of FIG. 6, to increase the gate voltage of the transistor M _C1P to be charged in order to output the same manner V _o in the case of FIG. 5, the transistor M _{4p Is} inserted between the power supply and the transistor _M3p to _achieve higher speed.

FIG. 8 shows the configuration of a fifth embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the potential of the gate terminal of the N-channel MOS transistor _M1p , which is the load transistor in the first embodiment, is set to the external input terminal PAD so that an arbitrary voltage can be applied from outside instead of the ground potential GND. The leak current can be detected at an arbitrary value according to the external input voltage. FIG. 11 is a table showing performance comparison results of simulations of the present invention and the prior art at V _th = 0.2 V. In this chart, the VDD dependency is VDD = 3.3 V ± 0.3 V, and the temperature dependency is 0 to 7
0 ° C., V _thn dependence is V _thn = 0.2 V ± 0.1 V, and the leakage current detection magnification is what percentage compared to the standard condition.
Or fluctuate. In each item, it can be seen that if the configuration of FIG. 1 and FIG. Further, the response time of the configuration of FIG. 4 is reduced to １ ／ compared to the configuration of FIG. 1 which is equivalent to the conventional circuit. Furthermore, since the present invention does not require a resistor like the conventional circuit, it can be seen that the area is reduced to 1/60.

Various modifications are possible in each of the above embodiments. For example, all current sources have been described as active elements, but as shown in FIG.
2, R3 can also be used. Further, the configuration of the present invention can be employed in each of the two conductivity type wells of the CMOS circuit.

[0047]

As described above, according to the present invention, the voltage formed by the two transistors operated in the sub-threshold region is supplied to the gate of the leak current detecting transistor. The magnification does not depend on the power supply voltage or the temperature, and accurate leak current can be detected.

Further, since it can be generated by a transistor without using a resistor occupying a large area, the leak current detection circuit can be laid out with a small pattern area.

Further, according to the present invention further comprising a configuration for clamping the potential of the drain terminal of the leak current detecting MOS transistor, the potential at the drain of the leak current detecting MOS transistor has a small amplitude, so that the leak current can be detected at high speed. it can.

Further, according to the present invention in which a MOS transistor capable of freely controlling the gate potential from outside the chip via an external terminal is used as the load of the leak current detection circuit, the leak current detection magnification can be set freely. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating how to apply a substrate potential in the configuration of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a modification of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a modification of FIG. 6;

FIG. 8 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 9 is a graph showing a result of simulating the V _bn -I _bn characteristics of FIG. 1;

FIG. 10 is a graph showing a result of simulating the V _bn- (W2 / W1) characteristic of FIG. 1;

FIG. 11 is a chart showing performance comparison results of simulations of the present invention and the conventional invention at V _th = 0.2 V;

FIG. 12 is a circuit diagram showing a configuration using a resistor as a current source in the first embodiment.

FIG. 13 is a circuit diagram showing a configuration of a conventional leak current detection circuit.

[Explanation of symbols]

M _1n , M _2n , M _3n , M _4n n-channel MOS transistors M _gp , M _gn current sources M _1p , M _2p , M _3p , M _4p p-channel MOS transistors M _Lp , M _Ln leak detection transistors

Claims (36)

(57) [Claims] A first source connected to a first power source and a drain terminal connected to a second power source via a load;
A second MOS transistor having a drain connected to the gate of the first MOS transistor of the first conductivity type, a source connected to the first power supply, and a gate connected to the first current source; A first conductivity type MOS transistor; a third first conductivity type having a source connected to the gate of the first first conductivity type MOS transistor, a drain connected to the first current source, and a gate connected to the drain; Type M
An OS transistor, wherein an absolute value of a difference between a potential of a gate of the second first conductivity type MOS transistor and a potential of the first power supply is a threshold voltage of the second and third first conductivity type MOS transistors. The second and third so as to be equal to or less than
Wherein the first conductivity type MOS transistor is driven in a sub-threshold region. 2. The power supply according to claim 1, wherein said first conductivity type MOS transistor is an N-channel MOS transistor, said first power supply is a low potential power supply, and said second power supply is a high potential power supply. 2. The semiconductor integrated circuit device according to 1. 3. The semiconductor integrated circuit according to claim 2, wherein the substrate potential of said first first conductivity type MOS transistor is a P type well potential which is a conductivity type opposite to said first conductivity type. apparatus. 4. The power supply according to claim 1, wherein said first conductivity type MOS transistor is a P-channel MOS transistor, said first power supply is a high potential power supply, and said second power supply is a low potential power supply. 2. The semiconductor integrated circuit device according to 1. 5. The semiconductor integrated circuit according to claim 4, wherein the substrate potential of said first first conductivity type MOS transistor is an N-type well potential which is a conductivity type opposite to said first conductivity type. apparatus. 6. The semiconductor integrated circuit according to claim 1, wherein a substrate terminal of said third first conductivity type MOS transistor is connected to a source terminal of said third first conductivity type MOS transistor. apparatus. 7. The semiconductor integrated circuit according to claim 2, wherein a potential of said ground power supply or a predetermined potential lower than said potential is applied to substrate terminals of said second and third first conductivity type MOS transistors. Circuit device. 8. The semiconductor integrated circuit according to claim 4, wherein a potential of said power source or a predetermined potential higher than said potential is applied to substrate terminals of said second and third first conductivity type MOS transistors. apparatus. 9. The predetermined potential is provided as a gate output of a fifth first conductivity type MOS transistor having a source connected to an installation power supply and a drain and a gate connected to a second current source. The semiconductor integrated circuit device according to claim 7. 10. The predetermined potential is a fifth potential having a source connected to a power supply, a drain and a gate connected to a second current source.
9. The semiconductor integrated circuit device according to claim 8, wherein the signal is provided as a gate output of said first conductivity type MOS transistor. 11. The first current source and the second current source have a gate connected to a ground power supply, a source connected to a power supply, and a drain connected to the third or fifth N channel M.
10. The semiconductor integrated circuit device according to claim 9, wherein the first integrated circuit is a first P-channel MOS transistor connected to the drain of the OS transistor. 12. The first current source and the second current source have a gate connected to a power supply, a source connected to a ground power supply, and a drain connected to the third or fifth P channel M.
11. The semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is a first N-channel MOS transistor connected to a drain of the OS transistor. 13. The semiconductor integrated circuit device according to claim 9, wherein said first and second current sources are resistors. 14. The semiconductor integrated circuit device according to claim 10, wherein said first and second current sources are resistors. 15. The load is a second P-channel MOS transistor having a gate connected to the ground power supply, a source connected to the power supply, and a drain connected to the drain of the first or fourth N-channel MOS transistor. 3. The semiconductor integrated circuit device according to claim 2, wherein: 16. The load has a gate connected to a power supply,
5. The semiconductor integrated circuit device according to claim 4, wherein a source is connected to a ground power supply, and a drain is a second N-channel MOS transistor connected to a drain of the first or fourth P-channel MOS transistor. . 17. A first first conductivity type MOS transistor having a source connected to a first power supply, a drain connected to a gate of the first first conductivity type MOS transistor, and a source connected to the first first conductivity type MOS transistor. A second first conductivity type MOS transistor connected to a power supply and having a gate connected to the first current source; a source connected to the gate of the first first conductivity type MOS transistor; and a drain connected to the first first conductivity type MOS transistor. And the third first conductivity type M having a gate connected to the drain.
An OS transistor, a source connected to a drain of the first first conductivity type MOS transistor, a drain connected to a second power supply via a load, and a fourth first MOS transistor having a gate supplied with a predetermined potential.
A conductivity type MOS transistor, wherein an absolute value of a difference between a potential of a gate of the second first conductivity type MOS transistor and a potential of the first power supply is equal to that of the second and third first conductivity type MOS transistors. The second and third first signals are set so as to be equal to or smaller than the threshold voltage.
In the semiconductor device, the conductivity type MOS transistor is driven in the sub-threshold region, and the channel width of the fourth first conductivity type MOS transistor is smaller than the channel width of the first first conductivity type MOS transistor. A semiconductor integrated circuit device characterized by the above-mentioned. 18. The method according to claim 18, wherein the first conductivity type MOS transistor is N-type.
18. The semiconductor integrated circuit device according to claim 17, wherein the first power supply is a low-potential power supply, and the second power supply is a high-potential power supply. 19. The semiconductor integrated circuit according to claim 18, wherein the substrate potential of said first first conductivity type MOS transistor is a P-type well potential which is a conductivity type opposite to said first conductivity type. apparatus. 20. The first conductivity type MOS transistor is a P-type MOS transistor.
18. The semiconductor integrated circuit device according to claim 17, wherein the first power supply is a high-potential power supply, and the second power supply is a low-potential power supply. 21. The semiconductor integrated circuit according to claim 20, wherein the substrate potential of said first first conductivity type MOS transistor is an N-type well potential which is a conductivity type opposite to said first conductivity type. apparatus. 22. The predetermined potential is provided as a gate output of a fifth first conductivity type MOS transistor having a source connected to a ground power supply and a drain and a gate connected to a second current source. The semiconductor integrated circuit device according to claim 18. 23. The fifth potential as claimed in claim 5, wherein a source is connected to a power supply, and a drain and a gate are connected to a second current source.
21. The semiconductor integrated circuit circuit device according to claim 20, wherein the signal is provided as a gate output of said first conductivity type MOS transistor. 24. The semiconductor device according to claim 1, wherein a substrate terminal of said third first conductivity type MOS transistor is connected to a source terminal of said third first conductivity type MOS transistor.
8. The semiconductor integrated circuit device according to 7. 25. The MOS of the second and third first conductivity types.
2. The transistor according to claim 1, wherein a potential of said ground power supply or a potential lower than said potential is applied to a substrate terminal of said transistor.
9. The semiconductor integrated circuit device according to item 8. 26. The second and third first conductivity type MOSs.
21. The semiconductor integrated circuit device according to claim 20, wherein a potential of the power supply or a potential higher than the power supply is applied to a substrate terminal of the transistor. 27. The first current source and the second current source having a gate connected to a ground power supply, a source connected to a power supply, and a drain connected to the third or fifth N channel M.
23. The semiconductor integrated circuit device according to claim 22, wherein the semiconductor integrated circuit device is a first P-channel MOS transistor connected to a drain of the OS transistor. 28. The first current source and the second current source having a gate connected to a power supply, a source connected to a ground power supply, and a drain connected to the third or fifth P channel M.
24. The semiconductor integrated circuit device according to claim 23, wherein the semiconductor integrated circuit device is a first N-channel MOS transistor connected to a drain of the OS transistor. 29. The semiconductor integrated circuit device according to claim 22, wherein said first and second current sources are resistors. 30. The semiconductor integrated circuit device according to claim 23, wherein said first and second current sources are resistors. 31. The load is a second P-channel MOS transistor having a gate connected to the ground power supply, a source connected to the power supply, and a drain connected to the drain of the first or fourth N-channel MOS transistor. 19. The semiconductor integrated circuit device according to claim 18, wherein: 32. The load, having a gate connected to a power supply,
21. The semiconductor integrated circuit device according to claim 20, wherein a source is connected to a ground power supply, and a drain is a second N-channel MOS transistor connected to a drain of the first or fourth P-channel MOS transistor. . 33. A method according to claim 33, wherein a predetermined potential applied to the gate of the fourth first conductivity type MOS transistor is applied as a clamp potential of the first and second power supply voltages by at least two stages of transistors connected in series. 18. The semiconductor integrated circuit device according to claim 17, wherein: 34. A first first conductivity type MOS transistor having a source connected to a first power supply and a drain terminal connected to a second power supply via a load, and a drain connected to the first first conductivity type. Connected to the gate of the MOS transistor, the source is connected to the first power supply, and the gate is connected to the current source.
An S transistor; and a third first conductivity type MOS transistor having a source connected to the gate of the first first conductivity type MOS transistor, a drain connected to the current source, and a gate connected to the drain. The load is a second conductivity type MOS transistor having a gate connected to an external terminal;
The absolute value of the difference between the potential of the gate of the S transistor and the potential of the first power supply is equal to the second and third first conductivity type MOS transistors.
The second and third first conductivity type MOS transistors are driven in a sub-threshold region so as to be equal to or smaller than a threshold voltage of the transistor, and a current detection magnification is determined by a gate potential set by the external terminal. A semiconductor integrated circuit device characterized by being variable. 35. The load, wherein a source is connected to a power supply,
29. The semiconductor integrated circuit device according to claim 28, wherein the drain is a P-channel MOS transistor connected to the drain of the first N-channel MOS transistor. 36. The semiconductor according to claim 35, wherein the load is an N-channel MOS transistor having a source connected to the ground power supply and a drain connected to the drain of the first P-channel MOS transistor. Integrated circuit device.