JPH1126598A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the output offset voltage due to fluctuation in the relative threshold voltage Vth between an NMOS and a PMOS at the time of transmitting a DC voltage. SOLUTION: The semiconductor integrated circuit comprises a first depletion mode N channel MOS transistor 1 where respective gates are connected with the input terminal while respective sources are connected with the output terminal, and a first depletion mode P channel MOS transistor 2. The semiconductor integrated circuit further comprises a second depletion mode N channel MOS transistor 4 of the same W/L as the first depletion mode N channel MOS transistor 1 where the drain is connected with the output terminal while the gate and source are connected together with a low voltage side power supply, and a second depletion mode P channel MOS transistor 3 of the same W/L as the first depletion mode P channel MOS transistor 2 where the drain is connected with the output terminal while the gate and source are connected together with a high voltage side power supply. The 'same W/L' means the value of (channel width)/(channel length) is identical or substantially identical.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an output buffer suitable for a semiconductor integrated circuit device which performs analog signal processing and multi-level signal processing.

[0002]

2. Description of the Related Art A complementary source follower using an NMOS transistor and a PMOS transistor has been widely used as an output buffer for analog signal processing and multi-level signal processing designed using a conventional CMOS process.

FIG. 5 is a circuit diagram showing an example of a conventional complementary source follower. NMOS transistor 40 and P
The gate terminals of the MOS transistors 41 are commonly connected to form an input terminal 5, the source terminals are commonly connected to form an output terminal 6, and the NMOS transistor 4
The drain terminal of 0 is connected to the power supply voltage 7, the drain terminal of the PMOS transistor 41 is connected to the ground potential 8, and a load drive current is supplied from the drain terminal to the source terminal. With this configuration, since both the input terminals 5 are gate terminals, a high-impedance signal is received at the preceding stage, and the output terminals 6 are both source terminals and can drive the subsequent load circuit at low impedance. Further, in order to eliminate the substrate bias effect of the MOS transistor and obtain a linear input / output characteristic, each of the substrate terminal and the source terminal of the NMOS transistor 40 and the PMOS transistor 41 is electrically connected.

FIG. 6 shows another circuit configuration diagram of a conventional complementary source follower. NMOS transistor 50 and PM
The gate terminals of the OS transistors 51 are commonly connected and connected to the input terminal 5, the drain terminal of the NMOS transistor 50 is connected to the power supply voltage 7, the source terminal is connected to the constant current source 54, and It is connected to the gate terminal of the output drive PMOS transistor 53. The drain terminal of the PMOS transistor 51 is connected to the ground potential 8, the source terminal is connected to the constant current source 55, and the NMOS transistor 5 for output drive is connected.
2 gate terminals. NMOS transistor 5
The source terminals of the PMOS transistor 2 and the PMOS transistor 53 are commonly connected to form an output terminal 6, which drives the capacitive load at high speed. The drain terminal of the NMOS transistor 52 is connected to the power supply voltage 7, the drain terminal of the PMOS transistor 53 is connected to the ground potential 8, and a load drive current is supplied from the drain terminal to the source terminal. With this configuration, since both input terminals 5 are gate terminals, they receive the signal of the previous stage with high impedance,
The output terminals 6 are both source terminals and can drive a subsequent load circuit with low impedance. The W / L (W: channel width, L: channel length) of the PMOS transistor 51, 53 pair and the NMOS transistor 50, 52 pair have the same shape, the current values of the constant current sources 54 and 55 are Iss1, Iss2, and Iss = When Iss1 = Iss2, the idling current Ibias passing through the NMOS transistor 52 and the PMOS transistor 53 constituting the output drive stage is Iss
Since the gate-source voltages of the PMOS transistors 51 and 53 and the NMOS transistors 50 and 52 are equal, the input terminal 5 and the output terminal 6 are equal.
No DC level shift occurs during the operation. In order to eliminate the substrate bias effect of the MOS transistor and obtain linear input / output characteristics, the NMOS transistors 50 and 52 are
The substrate terminal and the source terminal of each of the OS transistors 51 and 53 are electrically connected.

Another characteristic of the complementary source follower is that when a current flows from the output terminal to the load,
When the MOS transistor 52 distributes the load driving source current and the current flows from the load toward the output terminal, P
The MOS transistor 53 distributes the load driving sink current, thereby enabling high-speed driving to a large capacity load.

[0006]

However, in the analog processing and the multi-value processing in the complementary source follower circuit, when the accurate transmission of the DC voltage is attempted,
There has been a problem that an output offset voltage is generated due to a variation in a relative threshold voltage Vth between the NMOS and the PMOS.
This problem will be described with reference to the complementary source follower circuit shown in FIG. At the DC operating point of this circuit, the idling current is determined when the drain currents of the NMOS transistor 40 and the PMOS transistor 41 are equal. When the threshold voltage Vth of the NMOS transistor 40 is equal to the threshold voltage Vth of the PMOS transistor 41, a very small drain current flows, and the gate-source voltage Vgs of each MOS transistor is biased to 0V, and no output offset voltage is generated.
However, when a relative variation in Vth occurs between the NMOS and the PMOS, the drain current, which is the idling current, becomes equal between the NMOS transistor 40 and the PMOS transistor 41.
Not equal due to differences in Vth. For example, when the Vth of the NMOS transistor 40 is large, the NMO
When the Vgs of the S transistor 40 also increases, a negative offset occurs in the output. When the Vth of the PMOS transistor 41 is large, the Vgs of the PMOS transistor 41 at the time of idling increases, and a positive offset occurs in the output. I do. NM in manufacturing CMOS process
There is no relative matching element in the Vth characteristic between the OS and the PMOS, and the output offset fluctuates by the Vth variation in manufacturing.

The complementary source follower circuit shown in FIG.
This circuit ideally cancels the relative variation in Vth between the OS and the PMOS, and does not generate an output offset. When W / L between the NMOS transistors 50 and 52 and between the PMOS transistors 51 and 53 are equal, the NMOS transistor 52 and the PMO
Idling current Ibi flowing between S transistors 53
Since as is equal to Iss (= Iss1 = Iss2), the NMOS
Between the transistors 50 and 52 and the PMOS transistor 5
Vgs between 1 and 53 also become equal. At this time, the following relational expression holds.

Vgs50 (Iss1) + Vgs53 (Ibias) = Vg
s51 (Iss2) + Vgs52 (Ibias) As long as the above expression is satisfied, no offset voltage is generated at the output terminal 6 even if there is a relative variation in Vth between the NMOS and the PMOS. However, the current mirror mismatch between the constant current source 54 for flowing Iss1 and the constant current source 55 for flowing Iss2 does not make Iss1 = Iss2, and an offset voltage is generated at the output. Further, in the complementary source follower circuit of FIG. 6, in addition to the output drive MOS transistor, an NMOS source follower including an NMOS transistor 50 and a constant current source 54, and a PMOS source follower including a PMOS transistor 51 and a constant current source 55 And a bias circuit for setting Iss1 and Iss2 is required, and there is a disadvantage that the circuit scale is increased. Further, in addition to the idling current of the output, currents of Iss1, Iss2 and a bias circuit are required, which leads to an increase in current consumption. In addition, the increase in circuit scale increases the chip layout area and power consumption, which causes a temperature gradient in the chip, degrades the Vgs matching characteristics of the MOS transistor, and causes an output offset temperature drift. Was. Due to the occurrence of the output offset, accurate DC-coupling signal processing has been difficult when applied to analog processing. Further, when considering application to a voltage mode multi-valued logic circuit, occurrence of an offset in a buffer extremely deteriorates a noise margin of multi-level signal processing.

[0009]

In order to solve the above problems, the present invention provides a first depletion type in which each gate is connected to an input terminal and each source is connected to an output terminal. An N-channel insulated-gate transistor and a first depletion-type P-channel insulated-gate transistor having the same W / L as the first depletion-type N-channel insulated-gate transistor and having a drain connected to the output terminal And a second depletion-type N-channel insulated-gate transistor whose gate and source are commonly connected to a low-voltage side power supply, and the same W / L as the first depletion-type P-channel insulated-gate transistor, and the drain is A second depletion connected to the output terminal and having the gate and source commonly connected to the high-side power supply And type P-channel insulated gate transistor, to provide a semiconductor integrated circuit having a.

"W / L is the same" means (channel width)
It means that the value of / (channel length) is close to a value that can be considered to be the same or substantially the same. Insulated gate transistors need only have the same value of W / L, and W and L need not necessarily be the same.

That is, according to the present invention, the second depletion type N is biased to 0 V between the gate and the source.
The drain current of the channel insulated gate MOS transistor (constituting the sink type constant current source) biases the gate-source voltage of the first depletion type N-channel insulated gate transistor for output drive to 0V,
In addition, the drain current of the second depletion-type P-channel insulated gate transistor (constituting a source-type constant current source) whose gate-source is biased to 0 V is expressed as follows:
The gate-source voltage of the first depletion-type P-channel insulated gate transistor for output drive is set to 0 V
, The voltage between the gate and the source of the first depletion type N-channel insulated gate transistor and the P-channel insulated gate transistor for the output drive is set to 0 V, and the DC level shift and the offset No complementary source follower can be realized. With the above-mentioned semiconductor integrated circuit, a complementary source follower with no offset can be constructed with a very simple circuit, which can reduce the chip area and further increase the matching accuracy of the device characteristics of the insulated gate transistor. It became. As a result, a highly accurate buffer circuit for analog signal processing and multi-level signal processing can be realized, and the accuracy of signal processing can be significantly improved.

Further, in the semiconductor integrated circuit of the present invention, since the source of each insulated gate transistor is connected to each well diffusion layer, a substrate bias effect is eliminated and linear input / output characteristics are provided. In particular, when a buffer having nonlinear input / output characteristics is used in the voltage mode multilevel signal processing, a noise margin of a multilevel signal level signal is deteriorated. However, the use of the semiconductor integrated circuit of the present invention eliminates a DC offset. By using a buffer having linear input / output characteristics, high-precision multi-level signal processing can be realized.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In FIG. 1, the gate terminals of a depletion type NMOS transistor 1 and a depletion type PMOS transistor 2 are connected in common, connected to an input terminal 5, each source terminal is connected in common, and an output terminal 6 is connected.
Connected to the depletion type NMOS transistor 1
Has a power supply voltage of 7 (becomes a high-side power supply voltage).
Connected to the depletion type PMOS transistor 2
Has a ground potential 8 (becomes the low-voltage side power supply potential).
And a load driving current is supplied from the drain terminal to the source terminal. With this configuration, since both the input terminals 5 are gate terminals, a high-impedance signal is received at the preceding stage, and the output terminals 6 are both source terminals and can drive the subsequent load circuit at low impedance. In order to eliminate the substrate bias effect of the MOS transistor and obtain a linear input / output characteristic, a depletion type NMOS transistor 1 and a depletion type PMOS transistor are used.
Each of the substrate terminal and the source terminal of the transistor 2 is electrically connected. That is, the substrate bias effect is canceled by making the source potential of each MOS transistor equal to the potential of the well diffusion region.

Further, a depletion type NMOS transistor having the same shape as the depletion type NMOS transistor 1 and W / L.
The drain terminal of the S transistor 4 is connected to the output terminal 6, and the gate and source terminals of the depletion type NMOS transistor 4 are commonly connected to the ground potential 8. The depletion type NMOS transistor 4 is a depletion type NMOS transistor whose gate-source is biased to 0V.
The transistor operates as a sink-type constant current source In which outputs the drain terminal of the transistor. The depletion type PMOS transistor W / L has the same shape as the depletion type PMOS transistor 2.
The drain terminal of the MOS transistor 3 is connected to the output terminal 6, and the gate and source terminals of the depletion type PMOS transistor 3 are commonly connected to the power supply voltage 7. A depletion-type PMOS in which the gate and source of the depletion-type PMOS transistor 3 are biased to 0 V
The transistor operates as a source-type constant current source Ip whose output is the drain terminal of the transistor. Depletion type NMOS transistor 4 whose gate-source is biased to 0V
A constant-current source In comprising the source-follower biases the gate-source voltage of the depletion-mode NMOS transistor 1 for output drive to 0 V,
A source-type constant current source Ip comprising a depletion-type PMOS transistor 3 whose gate-source is biased to 0 V biases the gate-source voltage of the output-drive depletion-type PMOS transistor 2 constituting a source follower to 0 V. As a result, the gates of both the depletion type NMOS transistor 1 and the depletion type PMOS transistor 2 for output driving are
Since the voltage between the sources is biased to 0 V, it is possible to configure a complementary source follower having no DC level shift and no offset between the input and output.

When a current flows from the output terminal 6 toward the load by using the complementary source follower configuration, the NMOS transistor 1 supplies a load driving source current, and the current flows from the load toward the output terminal 6. Flows, the PMOS transistor 2 distributes the load driving sink current, so that the transient charge current at the rise and fall of the waveform can be distributed to a large-capacity load. Drive enabled.

The mechanism of canceling the variation of the threshold voltage Vth between the NMOS and the PMOS and preventing the output terminal 6 from generating an offset in this embodiment is shown in FIG.
This will be described with reference to the characteristic diagrams of FIGS. 2A, 2B, and 2C. In the present description, it is assumed that the W / L size of the NMOS and the PMOS is set so that the difference in mobility between the NMOS and the PMOS is adjusted by the W / L size ratio, and gm of both the MOSs becomes equal. Of course, the present invention uses the NMOS-P
The W / L size ratio between MOSs is not limited, and can be realized with an arbitrary W / L size ratio.

The characteristic diagram of FIG. 2A shows that the absolute value of the threshold voltage Vn1 of the depletion type NMOS transistor 1 is equal to the absolute value of the threshold voltage Vp1 of the depletion type PMOS transistor 2, where | Vn1 | = | Vp1 | Is the case. 0 is applied between the gate and source of the depletion type NMOS transistor 4 and the depletion type PMOS transistor 3.
Since they are biased to V, each output drain current is set to In1 = Ip1 shown in FIG. That is, the sink type constant current source In attached to the output terminal 6 is set to In1, and the source type constant current source Ip is set to Ip1, and both current values are equal. In1 is a depletion type NMOS transistor 1
Is determined, and Ip1 is a depletion type PMOS.
The operating point of the transistor 2 is determined. Since the W / L of the depletion type NMOS transistor 1 and the depletion type NMOS transistor 4 have the same shape, the gate-source voltage of the depletion type NMOS transistor 1 biased by In1 is set to 0V. Depletion type PMOS transistor 2 and depletion type PMO
Since the W / L of the S transistor 3 has the same shape, the gate-source voltage of the depletion type PMOS transistor 2 biased by Ip1 is set to 0V. Therefore, the voltage between the input terminal 5 and the output terminal 6 of the complementary source follower circuit in this embodiment is biased to 0V.

FIG. 2B shows that the absolute value of the threshold voltage Vn0 of the depletion type NMOS transistor 1 is smaller than the absolute value of the threshold voltage Vp1 of the depletion type PMOS transistor 2, | Vn0 | < | Vp1 |. Since the gate and source of the depletion type NMOS transistor 4 and the depletion type PMOS transistor 3 are biased to 0 V, the respective output drain currents become In0 <Ip1 shown in FIG. 2B. Since the W / L of the depletion type NMOS transistor 1 and the depletion type NMOS transistor 4 have the same shape, the gate-source voltage of the depletion type NMOS transistor 1 biased by In0 is set to 0V. Since the W / L of the depletion type PMOS transistor 2 and the depletion type PMOS transistor 3 have the same shape, the depletion type PM transistor biased by Ip1
The gate-source voltage of the OS transistor 2 is set to 0V. That is, even if the relative variation of Vth occurs between the NMOS and the PMOS, the voltage between the input terminal 5 and the output terminal 6 of the complementary source follower circuit in this embodiment is 0 V.
Biased.

Similarly, as shown in FIG. 2C, | Vn1 |>
Even if In1> Ip0 at | Vp0 |, the gate of the depletion type NMOS transistor 1 biased at In1
Since the source voltage is set to 0 V and the gate-source voltage of the depletion type PMOS transistor 2 biased by Ip0 is set to 0 V, even if a relative variation of Vth occurs between the NMOS and the PMOS, the present embodiment is used. Input terminal 5 and output terminal 6 of the complementary source follower circuit at
Is biased to 0V during the period.

Thus, as shown in this embodiment, the NMOS-
Even if the relative threshold voltage Vth varies between the PMOSs, no offset voltage is generated at the output terminal 6 of the complementary source follower, and the DC voltage can be accurately transmitted. In the case of the circuit shown in FIG. 6 having the function of canceling the Vth variation between the NMOS and the PMOS, the NMOS transistor 52 forming the output drive stage and the PMO
Idling current Ibias flowing between S transistors 53
Is an NMOS source follower composed of an NMOS transistor 50 and a constant current source 54 having a value of Iss1, and PM
OS transistor 51 and constant current source 5 having the value of Iss2
5 is determined by the DC potential difference between the sources of the two source followers of the PMOS source follower, the currents Iss1 and Iss2 are required in addition to the idling current Ibias. A source-type constant current source Ip having an output from the drain terminal of the PMOS transistor 3 and a sink-type constant current source In having an output from the drain terminal of the depletion type NMOS transistor 4 are directly connected to the circuit of the present embodiment shown in FIG. Since the current becomes an idling current, it is not necessary to supply an extra current, and it is possible to configure an output buffer with low power consumption. The source-type constant current source Ip having the drain terminal of the depletion-type PMOS transistor 3 as an output and the sink-type constant current source In having the drain terminal of the depletion-type NMOS transistor 4 as an output utilize characteristics of the depletion-type MOS transistor. In and Ip can be set only by short-circuiting (0 V) between the gate and the source, and a dedicated bias circuit is not required. In the case of a current source constituted by a conventional current mirror circuit, a current source MOS transistor having a gate common to the current source circuit serving as a reference is required, but the depletion type MOS constant current source employed in this embodiment is Since a constant current source can be constituted by only one transistor without using a bias circuit, the number of circuit elements can be reduced, and further lower power consumption can be realized.

Further, by reducing the circuit scale, the chip layout area is reduced, and the power consumption is suppressed.
The degree of freedom in the arrangement of elements in the chip can be increased, the temperature gradient due to heat generation can be reduced, the Vgs matching characteristics of the MOS transistor can be improved, and the output offset temperature drift can be drastically improved. This makes it possible to stably achieve accurate DC-coupled signal processing when considering application to analog processing, and to suppress the occurrence of offset in buffers when considering application to voltage-mode multi-valued logic circuits. so,
The noise margin of multi-level signal processing has been dramatically improved.

When a large number of circuits in this embodiment are used on one chip, not only the chip size can be reduced due to the reduction in the number of elements, but also the power consumption can be reduced, and the temperature gradient in the chip can be reduced. In addition, the matching characteristics of the device are further improved. For this reason, the MOS V
It is possible to manufacture chips with high yield, covering the variation range of th.

FIG. 3 is a sectional view showing an example of the configuration of a semiconductor device constituting the circuit of this embodiment. In FIG. 3, 1
Reference numeral 8 denotes first and second depletion type NMOS transistors (N-channel insulated gate transistors), and 19 denotes first and second depletion type PM transistors.
OS transistor (to be a P-channel insulated gate transistor), 1 is an N-type semiconductor substrate, 2 is a P well in an NMOS region, 3 is an n ⁺ drain diffusion region, 4 is an n ⁺ source diffusion region, and 5 is a P well region. P ⁺ diffusion region for taking a potential, 22 a channel diffusion region for threshold adjustment, 6 a floating P well of a PMOS region, 7 an N well, 8 a P ⁺ drain diffusion region, and 9 a P ⁺ source diffusion The region 10 is an N ⁺ diffusion region for taking the potential of the N well region, 21 is a channel diffusion region for adjusting a threshold value, 11 is a gate oxide film of each MOS transistor, and 12 is an NMOS.
Transistor gate wiring polysilicon, 20 is PMO
The gate wiring polysilicon of the S transistor, and 17 is a selective oxide film.

The NMOS transistor used in this configuration example,
PMOS transistors eliminate the body bias effect,
Each source potential is set to the same potential as the well potential. That is, the source diffusion region 4 of the NMOS transistor 18 and the P ⁺ diffusion region 5 in the P well constituting the NMOS transistor 18 are connected by the aluminum wiring 14. The source diffusion region 9 of the PMOS transistor 19 and the N ⁺ diffusion region 10 in the N well constituting the PMOS transistor 19 are connected by an aluminum wiring 16.

FIG. 4 is a sectional view showing another example of the configuration of the semiconductor device constituting the circuit of this embodiment. In this configuration example, a circuit is formed on a semiconductor layer provided on an insulating surface. In FIG. 4, reference numeral 100 denotes an insulating substrate, and N
A MOS transistor 112 and a PMOS transistor 113 are formed. In the components of the NMOS transistor 112, 101 and 103 are N ⁺ diffusion regions forming drain / source regions, 102 is a channel formed of P ⁻ silicon, 108 is a gate oxide film, and 107 is gate polysilicon. In the components of the PMOS transistor 113, 104 and 106 are P ⁺ diffusion regions forming drain / source regions, 105 is a channel formed of N ^- silicon, 109 is a gate oxide film, and 110 is a gate polysilicon. 111 is an insulating film, and 114 is a wiring. As the insulating substrate 100, a sapphire substrate, a silicon oxide film (SiO ₂ ), or the like is used.

[0027]

As described above, according to the present invention,
The output terminal of the complementary source follower circuit composed of a depletion type transistor is connected between the gate and source having the same W / L as the N-channel insulated gate transistor and the P-channel insulated gate transistor constituting the complementary source follower. Is a constant current source N biased to 0V.
By connecting a channel insulated gate transistor and a P-channel insulated gate transistor, the input / output of the complementary source follower circuit is biased to 0V, realizing a voltage buffer with no DC level shift, and accurate DC voltage information. Analog signal processing and multi-level signal processing circuits that can be transmitted are made possible.

Further, a complementary source follower having no direct current level shift is constituted by a very simple circuit, so that an insulated gate transistor can be formed in accordance with a reduction in chip area and a decrease in temperature gradient due to heat generation in the chip due to low power consumption. This makes it possible to further improve the matching accuracy of the element characteristics, thereby realizing a high-precision buffer circuit for analog signal processing and multi-level signal processing, and significantly improving the accuracy of signal processing.

Further, the connection to the source of each insulated gate transistor and each well diffusion layer eliminates the substrate bias effect and enables linear input / output characteristics.
As a result, by using a buffer having a linear input / output characteristic without a DC offset, the signal noise margin of the multilevel signal processing can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a DC characteristic of the embodiment.

FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device forming the circuit of the embodiment.

FIG. 4 is a cross-sectional view showing another configuration example of the semiconductor device forming the circuit of the embodiment.

FIG. 5 is a circuit configuration diagram of an example of a conventional complementary source follower.

FIG. 6 is another circuit configuration diagram of a conventional complementary source follower.

[Explanation of symbols]

 Reference Signs List 1 depletion type NMOS transistor 2 depletion type PMOS transistor 3 depletion type PMOS transistor 4 depletion type NMOS transistor 5 input terminal 6 output terminal 7 power supply voltage 8 ground potential 40 NMOS transistor 41 PMOS transistor 50 NMOS transistor 51 PMOS transistor 52 NMOS transistor 53 PMOS transistor 54 Constant current source 55 Constant current source

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tadahiro Omi 2-1-17-301 Yonegabukuro, Aoba-ku, Sendai, Miyagi Prefecture (72) Inventor Naoshi Shibata 1-3-4-1 Ecchujima, Koto-ku, Tokyo 16-411 issue

Claims (4)

[Claims] 1. A first depletion type N-channel insulated gate transistor and a first depletion type P-channel insulated gate transistor each having a gate connected to an input terminal and a source connected to an output terminal. And a second depletion-type transistor having the same W / L as the first depletion-type N-channel insulated-gate transistor, a drain connected to the output terminal, and a gate and a source commonly connected to a low-voltage side power supply. An N-channel insulated-gate transistor having the same W / L as the first depletion-type P-channel insulated-gate transistor, a drain connected to the output terminal, and a gate and a source commonly connected to a high-voltage side power supply And a depletion-type P-channel insulated gate transistor. Circuit. 2. The method according to claim 1, wherein the first depletion type N-channel insulated gate transistor has a gate-source voltage of zero.
Biasing with the drain current of the second depletion-type N-channel insulated-gate transistor set to V, and setting the first depletion-type P-channel insulated-gate transistor to the second depletion-type N-channel insulated-gate transistor whose gate-source voltage is set to 0 V 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is biased by a drain current of the two depletion-type P-channel insulated gate transistors. 3. The first and second depletion type N
2. The semiconductor according to claim 1, wherein respective sources of the channel insulated gate transistor and the first and second depletion-type P-channel insulated gate transistors are connected to respective well diffusion layers. Integrated circuit. 4. A semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed in a semiconductor layer on an insulating surface.