JPH0490619A - Tristate output circuit - Google Patents

Abstract

PURPOSE:To individually set the rising/falling characteristics of output by providing resistors against delay MOS on the side of turning ON at the time of changing the output against two MOSes. CONSTITUTION:Two output signals INH<->, IN<-> are received, and an output signal OUT is obtained from the connection point between a P-channel MOS transistor (PMOS10) and an N-channel MOS transistor (NMOS)12. In this case, resistor R1 adjusting the transient characteristics when the PMOS10 is changed from OFF to ON, and resistor R2 adjusting the transient characteristics when the NMOS12 is changed from OFF to ON, are independently provided. Thus, the operation characteristics of an output signal OUT can be independently adjusted at the time of rising and falling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a tri-state output circuit that obtains an output signal from a connecting portion of two series-connected MOS transistors in accordance with input signals from two signal input terminals. Regarding.

[Conventional technology] Conventionally, P channel MOS transistor (2MO5)
Complementary MO5 circuits (CMO8 circuits) that use a combination of an N-channel MO5I-transistor (NMOS) and an N-channel MO5I-transistor (NMOS) are widely used.

Figure 7 shows the most basic CMO5 circuit, in which PMO5IO1NMO512 connects power supply VCC and ground GN.
are connected in series between D. And PMO5IO1
Signal IN is manually applied to the gate of NMOS 12, and PMO
A signal OUT is output from the connection point of 5IO1NMO812.

In this circuit, if the input signal IN is L, the PMO
SIO turns on, NMO512 turns off, output signal OU
T becomes Vcc. On the other hand, when the input voltage is H, P
MOSIO is turned off, NMOS12 is turned on, and the output signal OUT becomes L. Therefore, it is possible to obtain an output signal according to the state of the input signal. However, in a CMOS circuit, when the input signal IN switches between L and H, G is output from Vcc through PMOS 10 and NMOS 12.
A through current flows to the ND.

On the other hand, Japanese Unexamined Patent Publication No. 62-254520 discloses a CMOS circuit that can reduce through current. In this example, as shown in FIG. 8, the input terminal of the input signal IN and the PMO
PMOS14 between the gate of 5IO1NMO812,
An NMOS 16 and a resistor R are inserted.

According to this circuit, when the input signal IN rises to L-H, NMO and S16 are turned on, the gate of NMOS12 is connected to GND, and NMOS12 is immediately turned off. On the other hand, the gate of PMOSIO has resistors R, NM
Since it is connected to GND via O816, the time it turns on is delayed depending on the size of the resistor R. Therefore, PMO3
It is possible to eliminate the time when both IO1NMOS12 are turned on at the same time, and generation of through current can be prevented.

In addition, by changing the value of the resistor R, the PMOSI
The time it takes for O to turn on (rise time) can be adjusted.

When the input signal IN falls (H-L), the PMO 514 is turned on, so the PMOSIO is immediately turned off and the NMOS 12 is turned on later. Therefore, as in the case described above, through current can be prevented.

Note that the configuration for reducing through current is disclosed in Japanese Unexamined Patent Application Publication No. 1986-62.
No. 254521, Japanese Unexamined Patent Publication No. 1-161916, etc.

[Problems to be Solved by the Invention] As described above, even in conventionally proposed circuits, the switching characteristics of the circuit can be adjusted without increasing the through current.

However, the above technique cannot be applied to a tristate CMO3 output circuit that obtains not only two outputs, H and L, but also a high impedance output.

That is, in order to obtain a high impedance output in the tri-state output circuit, it is necessary to keep the gate power of P M 0810 at H, the gate power for NMOS12 at L, and turn off both PMOSIO and NMOS12. However, as in the conventional example shown in Figure 8,
If a resistor R is placed between two gate input paths, both will be short-circuited through the resistor R. Therefore,
This circuit has a problem in that it is only possible to obtain a high impedance output.

An object of the present invention is to provide a tristate output circuit that can obtain a high impedance output and reduce through current.

[Means for solving the problem] In order to achieve the above object, the present invention provides a P-channel MO
A first resistor for signal delay inserted in the signal input path to the gate of the S transistor, and an N-channel MO5
) A second resistor for delaying the H signal inserted in the H signal input path to the gate of the transistor.

[Operation] When the input signal rises, the potential of the gate of PMO8 immediately becomes H, and PMOS is turned off. On the other hand, since a delay resistor is placed in the H signal input path to NMO5, the rise of the gate potential of NMO5 is delayed by this resistor, and the time that NMOS is turned on is as follows:
This occurs after PMOS is turned off.

On the other hand, when the input signal falls, the NMO 8 is immediately turned off, but the PMOS is turned on after a predetermined period of time due to a resistor inserted into the L signal input path.

Therefore, when the input signal rises and falls, one MOS turns off and then the other MOS turns on, and both transistors do not become conductive at the same time, so that through current can be suppressed.

Furthermore, since the rise characteristics of both MOs 5 are determined separately by the resistors placed in the respective gate signal input paths, the rise and fall characteristics of the output can be set separately.

[Example] Hereinafter, a tristate output circuit according to the present invention will be explained based on the drawings.

First Embodiment FIG. 1 is a block diagram of the first embodiment, in which two input signals I
It receives NH- and IN- and obtains an output signal OUT from the connection point between PMOSIO and NMOS12.

For this purpose, the signal INH is connected to the PMO 820 and NMOS
The signals IN and INH are input to the gate of 22, and the signals IN and INH are input to the gate of 2MO332 and NMOS34 via the Nant gate 30.
．． It is input to the gates of PMO336 and 8MO838.

Also, PMOS32. NMOS22. NMOS34 is connected in series between power supply VCC and ground GND, and PM
A resistor R1 is inserted between the OS 32 and the NMOS 22. And the drain of PMO820 is PM
It is connected to the connection point between O532 and resistor R1, and this connection point is connected to the gate of PMOSIO.

On the other hand, PMOS 36 and 8MO838 are connected to VCC and GND.
A resistor R2 is inserted between both MOS transistors 36 and 38. The connection point between this resistor R2 and NMOS38 is connected to the gate of NMOS12.

Next, the operation of the circuit of this embodiment will be explained based on FIG. 2.

When the mass and signal INH are fixed at H, PM
O520 is off and NMOS22 is on.

Further, in this state, if the signal IN is high, the signal IN-, which is the output of the Nant gate 30, is low. Therefore, PMOS32.36 is turned on and NMOS34
．． 38 or off.

Since the PMOS 32 is on and the NMOS 34 is off, the signal PI is H and PMOSIO is off. Also, NMOS38 is off and PMO
Since S36 is on, signal NI becomes H, and NMO
S12 is on. Therefore, the output signal OUT
becomes L.

Here, when the signal IN- changes from H to L, the signal IN-, which is the output of the Nant gate 30, changes from L to H. As a result, the NMOS 38 is turned on and the PMO 536 is turned off, and the signal N1 becomes L, so that the NMOS 12 is immediately turned off.

On the other hand, as the signal IN- becomes H, the PMO53
2 is turned off, and NMOS34 is turned on. Therefore, the connection point between PMOS 32, which determines the potential of signal PI, and resistor R1 is connected to resistor R1, NMOS 22, NMOS
It will be connected to GND via S34. Therefore,
A current flows toward GND, and the potential of the signal PI shifts to L.

However, since this amount of current is regulated by the resistor R1, a delay time occurs depending on the resistance value of the resistor R1, and the potential of the signal PI gradually decreases with a predetermined slope as shown in FIG. . Since PMOSIO is gradually turned on in accordance with its gate potential (potential of signal PI), output signal OUT gradually becomes H as shown in FIG.

Therefore, the resistor R1 is
By adjusting the magnitude of the output signal OUT, it is possible to reduce the through current from Vcc to GND via the PMOS 10 and NMOS 12 when the output signal OUT rises. Also,
By adjusting the size of the resistor R1, it is possible to adjust the transient characteristics when the PMOSIO turns from off to on.

On the other hand, in a steady state, the current supply capacity from the output terminal that outputs the output signal OUT is determined only by the drive capacity of the PMO510 alone, so providing the resistor R1 has no adverse effect on the DC characteristics of the output circuit. .

Next, while the signal INH- is fixed at H, the signal IN
Consider the case where changes from L to H. In this case, the signal IN-, which is the output signal of the Nant gate 3o, becomes L, which turns on the PMO 532, and
NMOS34 is turned off. Therefore, the signal PI immediately becomes H, and PM0S10 is turned off.

On the other hand, since the signal IN- becomes L, the PMO836
turns on and NMOS38 turns off, but resistor R2
Due to the action of , the signal NI gradually changes from L to H.

Therefore, NMOS12 is gradually turned on and the output signal O
UT also gradually changes from H to L. Therefore, the through current can be reduced as in the case described above.

Next, consider a case where the signal INH is fixed at L.

In this case, PMO520 is turned on and Nantes Gate 3
The output signal IN- of 0 is fixed at H.

Therefore, the NMOS 22 is turned off and the PMO320 is turned on, so the signal PI is fixed at H, and the PMO3I
O is turned off. On the other hand, since the signal IN- becomes H, P
MO836 is turned off and NMOS38 is turned on.

Therefore, the signal NI becomes L, and the PMO 312 is turned off.

In this way, PMO3IO and NMOS1 connected in series
Since both of 2 and 2 are turned off, the impedance seen from the output terminal of the signal OUT becomes 7\i impedance state.

As understood from the above explanation, if the signal INH is high, the signal IN-, which is the output of the Nant gate 30, is still high regardless of whether the signal IN is high. The same operation is performed instead.

As described above, according to this embodiment, the resistor R1 adjusts the transient characteristics when the PMO 310 changes from off to on.
and a resistor R2 that adjusts the transient characteristics at the rise when the NMOS 12 changes from off to on are independently provided, and the operating characteristics of the output signal OUT can be adjusted independently at the rise and fall. .

Second Embodiment In this embodiment, a Noah gate 40 is used in place of the Nant gate 30 of the first embodiment, and a PMO 520, an NMOS 2
2, NMOS 50 and PMO 852 are used. And Noah Gate 40, NMOS 50, PMO
552 is supplied with a signal INH.

The operation of this circuit will be as shown in Figure 4.
Except for the fact that the signal INH is used instead of the signal INH in the case of FIG. 2, the other operations are exactly the same, and the same effect can be obtained.

Third Embodiment According to this embodiment, PMO360 is connected in series to generate a signal PI for driving PMO3IO.
, resistor R1, NMOS 62, NMOS 64, and PMO
It has PMO866 connected in parallel to S60,
In order to generate the signal NI that drives NMOS12, P
It has an MO 370, a PMO 872, a resistor R2, and an NMOS 74 connected in series, and an NMOS 76 connected in parallel to the NMOS 74.

And the signal IN is PMO860, NMOS64, PM
O370, NMOS74 are supplied, and the signal INH is PM
The signal INH is supplied to the NMOS 76 and the signal INH is inverted by the inverter 80.
62, is supplied to PMO366.

Therefore, as in the case of the above-mentioned embodiment, generation of through current can be prevented with respect to the rising and falling edges of the signal IN when the signal INH is fixed at L, and the rising and falling characteristics of the output can be adjusted independently. Furthermore, a high impedance output can be obtained when the signal INH is fixed to H.

[Effects of the Invention] As explained above, according to the tri-state output circuit according to the present invention, when the output changes, the MOS on the side that turns on can be delayed, and the through current can be suppressed. I can do it. Also, the resistor for this delay is connected to two MO
Since it is provided independently for S, its delay time can be set separately. Furthermore, since both MO3 can be turned off, the impedance seen from the output side can be maintained at a high level.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the first embodiment, FIG. 3 is a configuration diagram of a second embodiment, and FIG. Figure 5 is a timing chart of the second embodiment, Figure 5 is a configuration diagram of the third embodiment, Figure 6 is a timing chart of the third embodiment, Figure 7 is a configuration diagram of a conventional output circuit, and Figure 8 is a diagram of the configuration of the conventional output circuit. FIG. 2 is a configuration diagram of another conventional configuration example. 10... PMO3 12... NMO3 1)l l;! , every A complete

Claims (1)

[Scope of Claims] A P-channel MOS transistor connected in series between a power supply and ground, and from which an output signal is taken out from the connection point;
In a tri-state circuit that includes an N-channel MOS transistor and supplies H and L signals from two signal input terminals to the gates of both MOS transistors to obtain an output signal according to the states of the two input signals, the P-channel A first resistor for L signal delay is inserted in the L signal input path to the gate of the MOS transistor, and a second resistor for H signal delay is inserted in the H signal input path to the gate of the N channel MOS transistor. A tri-state output circuit comprising: a resistance; and a tri-state output circuit.