JPH03127511A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To control an output signal through-rate by devising a conduction timing delay means to make two transistors(TRs) of a poststage circuit section conductive with a prescribed time from an input signal so as to suppress a through-current at a change in the output signal. CONSTITUTION:An output signal of a NOR gate 16 keeps an L level till a pre-stage PMOS TR 7 and a post-stage PMOS TR 10 are turned off and a pre-stage PMOS TR 8 is turned off and a potential at an output terminal 2 changes from an H level so far to the L level, and the output signal of the NOR gate 18 changes to the H level after the level of the output terminal 2 reaches an L level. Then a post-stage NMOS TR 11 on the other hand is not turned on before the output signal of the NOR gate 16 is not changed to the H level. Then the through-current is suppressed and the output signal through-rate is controlled by adjusting the size of the pre-stage NMOS TR 8 and the post-stage NMOS TR 11 properly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit that is capable of suppressing an output buffer through current when an output signal changes, and also capable of controlling an output signal slew rate value.

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional output buffer 7 circuit.

In the figure, internal signal input terminal 1 is a terminal for receiving an internal signal sent from inside the system including this output buffer 7 circuit, and output terminal 2 is a terminal for taking out an output signal corresponding to the above internal signal to the outside. It is a terminal. A P-channel type MO3tli field effect transistor (hereinafter referred to as PMO5+
- transistor 4.5 is connected in series with an N-channel MO5 field effect transistor (hereinafter referred to as NMO5 transistor) 5, and the output terminal 2 is connected to the connection point of these transistors 4.5. has been done. Further, the internal signal input terminal 1 is connected to the input terminal of an inverter 6, and the output terminal of the inverter 6 is connected to the gates of the PMOS transistor 4 and the NMO transistor 5, respectively.

In the above C output buffer circuit, internal signal input terminal 1
The internal signal applied to is inverted by an inverter 6, and the inverted signal is applied to the gates of PMO3) transistor 4 and NMOS) transistor 5.

When the internal signal changes from L level to H level, PMO
3) The signal applied to the gate of transistor 4 changes from H level to L level, and PMOS transistor 4 changes from OFF state to ON state.

At this time, the signal applied to the gate of NMOS transistor 5 also changes from H level to L level, so NMOS
The OS transistor 5 changes from an on state to an off state. By this operation, the potential of the output terminal r2 changes from the ground potential (L level) to the potential of the power supply 3 (H level). When the internal signal No. 13 changes from H level to L level, the potential of output terminal 2 changes from H level to L level by the operation opposite to the above case. In this way, the internal signal applied to internal signal input terminal 1 is
A corresponding signal is taken out from the output terminal 2.

[Problem to be solved by the invention]

However, in the conventional output buffer time v3 mentioned above, P
Since the output signal of the inverter 6 is simultaneously applied to the gates of the MO5) transistor 4 and the NMo5 transistor 5, when the output signal of the inverter 6 changes from the H level to the L level or from the L level to the H level, the PMO
3) A timing occurs when both the transistor 4 and the NMOS transistor 5 are turned on, and at this timing, a through current flows from the power supply 3 to the ground via the PMO transistor 4 and the NMOS transistor 5.

Normally, the PMO transistor 4 and the NMOS transistor 5 are large in size to drive an external load, so the through current in this case becomes a large value. Therefore, there is a problem in that noise is generated in the power supply 3 and the ground due to the above-mentioned through-current, leading to malfunction of the circuit.

Furthermore, since the output signal changes abruptly, the output ringing level due to the inductance component of the load increases, causing a problem in that the next-stage element connected to the output terminal 2 malfunctions.

The present invention has been made to solve these problems, and an object of the present invention is to provide an output buffer circuit that can suppress the through current when the output signal changes and also control the output signal slew rate value.

[Means to solve the problem]

The output buffer circuit according to the present invention includes a first transistor that conducts in response to a first logic level of an input signal and a second logic level i of an input signal, which is connected between a high potential power source and a low potential power source.
a second transistor that conducts in response to the 1p level and connected in series in this order, and a connecting point of these first and second transistors connected to an output terminal; and a high potential power source. and a low potential power supply, a third transistor conductive in response to the first logic level of the human input signal, and a fourth transistor conductive in response to the second logic level of the human input signal. A second stage circuit section in which the third and fourth transistors are connected in series and the connection point of the third and fourth transistors is connected to the output terminal, and the conduction timing of the third transistor is set to a predetermined time relative to the conduction timing of the first transistor. The transistor is configured to include a first conduction timing delay means that delays the conduction timing of the fourth transistor by a predetermined period of time than the conduction timing of the second transistor.

[Effect]

In this invention, since the timing of conduction of the third and fourth transistors in the second stage circuit section is delayed by a predetermined time from the human input signal, yiJff! Current is suppressed.

Further, the output Jolt current and the output slew rate value are adjusted by adjusting the sizes between the first and second transistors of the first stage circuit section and the third and fourth transistors of the second stage circuit section. Ru.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention.

In FIG. 1, internal signal input terminal -F1. The output terminal r2 and the power supply 3 are the same as in the conventional circuit described above. That is, internal signal input terminal 1 is a terminal for receiving an internal signal sent from inside a system consisting of an LSI including this output/gutsfer circuit, and output terminal 2 is a terminal for receiving an output signal corresponding to the internal signal. This is a terminal for taking out to the outside, and a constant voltage of positive potential is supplied from the power supply 3.

Between the power supply 3 and the ground, there are a front-stage PMO5) that turns on when a logic level L signal is applied to its gate, and a front-stage NMOS transistor that turns on when a logic level H signal is applied to its gate. 8 are connected in series from the power supply 3 side to the ground side in this order, and the connection point of these two transistors 7.8 is connected to the output terminal P2 to form the pre-stage circuit section 9. .

Apart from this, between the same power supply 3 and ground, there is a P for the latter stage.
The MOS transistor 1o and the NMOS transistor 11 for the subsequent stage are connected in series from the power supply 3 side to the ground side in this order, and the connection point of these two transistors 10 and 11 is connected to the output terminal 2 for the subsequent stage. A circuit section 12 is configured.

On the other hand, the internal signal input terminal 1 is connected to the input terminal of the first inverter 13 and the input terminal r of the second inverter 14,
The output terminal of the first inverter 13 is connected to the gate of the PMOS transistor 7 for the front stage, and the output terminal of the second inverter 14 is connected to the gate of the NMOS transistor 8 for the front stage.

Further, the internal signal input terminal 1 and the output terminal 2 are connected to a two-man NAND gate 15 as a first conduction timing delay means.
, and also connected to each input terminal of a two-man power NOR gate 16 as a second conduction timing delay means. The output terminal of the two-man NAND gate 15 is connected to the gate of the PMOS transistor 10 for the subsequent stage, and the output terminal of the two-man NOR gate 16 is connected to the gate of the NMOS transistor 11 for the subsequent stage.

Next, the operation of the output buffer circuit will be explained.

In the initial state, if the internal signal (No. 8) input manually to the internal signal input terminal r-1 is at L level, then the
3. The output signals of 14 both become H level, and the P for the previous stage
MO3h Langstuff is off, NMOSl- for the front stage
The transistor 8 is turned on, and the potential at the connection point of these transistors 7.8, that is, the output terminal 2 becomes the ground potential (L level). At this time, since the output signal of the NAND gate 15 is also at L level, the output signal of the NAND gate 15 is at H level, and the downstream PMO3) transistor 10 is in the off state, and the output signal of the NOR gate 16 is also at L level, so the NOR The output signal of the gate 16 is at H level, and the NMO transistor 11 for the subsequent stage is in the on state.

When the internal signal changes from the L level to the H level, the output signals of the inverters 13 and 14 change from the H level to the L level, the pre-stage PMO 9 + - Langstaff is turned on, and the pre-stage NMOS transistor 8 is turned off.

On the other hand, the output signal of the NAND gate 15 is
After the S transistor 7 is turned on and the pre-stage NMOS transistor 8 is turned off, the potential at the connection point of these transistors 7.8 is held at the H level until the potential changes from the L level to the H level. 8
It changes to L level only when the potential at the connection point reaches H level.

Then, the rear stage PMO3) transistor 10 is a NAND
It turns on for the first time when the output signal of the gate 15 changes to L level. On the other hand, the output signal of the NOR gate 16 changes from H level to L level at the same time as the internal signal changes from L level to H level.
MO3) transistor 11 is turned off at the same time as NMO3) transistor 8 for the previous stage.

Therefore, when the internal signal changes from the L level to the H level, the turn-on time of the rear-stage PMO8) transistor 10 is determined by the charging time of the output terminal 2 performed via the front-stage PMO3) transistor and the turn-on time of the NAND gate 15. The turn-off time of the front-stage NMOS transistor 8 and the rear-stage NMOS transistor 11 is delayed by the sum of the propagation delay time required for the output signal to change from the H level to the L level.

From this, by adjusting in advance the size of the front-stage PMO3I transistor 10 so that it is smaller than the size of the rear-stage PMO8) transistor 10, the through-JTI current can be suppressed compared to the case of conventional circuits. .

In addition, by turning on the front-stage PMOS transistor 10, the output terminal 2 is first changed from L level to H level, and then by turning on the rear-stage PMOS transistor 10, a large current is supplied to the output terminal J''2. Since current drive can be assisted, the output signal slew rate value can be controlled by appropriately adjusting the sizes of the front-stage PMOS transistor 7 and the rear-stage PMOS transistor 5), and the output buffer circuit is capable of driving a large current. can do.

Next, when the internal signal changes from H level to L level, the output signals of inverters 13 and 14 change from L level to H level, turning off the PMOS transistor 7 for the front stage and turning on the NMOS +- transistor 8 for the front stage. do.

On the other hand, the output signal of NOR game I・16 is
3) Langistoru and post-stage PMO 3) Langister 1
0 is turned off, the pre-stage NMOS transistor 8 is turned on, and the potential of the output terminal T2 remains at the L level until it changes from the H level to the L level, and the potential of the output terminal T-2 changes. It changes to H level only after reaching L level. And NMO5) transistor 1 for the rear stage
1 turns on for the first time when the output signal of the NOR gate 16 changes to H level.

Therefore, the turn-on time of the rear-stage NMOS transistor 11 when the internal signal changes from the H level to the L level is the discharge time from the output terminal 2 via the front-stage NMOS transistor 8 and the output of the NOR gate 16. The turn-off 1 of the front-stage PMOS transistor 10 and the rear-stage PMOS transistor 10 is calculated by the amount of propagation delay time required for the signal to change from L level to H level.
It will take more than 1 yoma.

Therefore, in this case as well, by adjusting in advance the size of the NMOS transistor 8 for the front stage so that it is smaller than the NMOS transistor 11 for the rear stage, the through current can be suppressed compared to the case of the conventional circuit. become.

Also, by turning on the NMOS transistor 8 for the front stage, the output terminal 2 is first changed from H level to L level, and then, by turning on the NMOS transistor 11 for the rear stage, a large current is driven to suck a large current from the output terminal 'f2. By appropriately adjusting the size of the NMOS transistor 8 for the front stage and the NMOS transistor 11 for the rear stage, the output buffer circuit can be made capable of controlling the output signal slew rate value and capable of driving a large current. Can be done.

Note that in the above embodiment, an output buffer circuit for driving an external load connected to a system consisting of an LSI has been described, but the output buffer circuit according to the present invention is not limited to this, and can be applied to large-capacity devices such as clock lines inside an LSI. It can also be applied to a clock driver for driving a load.

〔Effect of the invention〕

As described above, according to the present invention, the output stage has a two-stage configuration of the front-stage circuit section and the rear-stage circuit section, and the two transistors in the rear-stage circuit section are turned on with a predetermined time delay from the input signal by the conduction timing delay means. With this configuration, it is possible to suppress the through current in the output stage, and also to control the output signal slew rate value and suppress the output signal ringing level.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional output buffer circuit. In the figure, 1 is the internal signal input terminal r, 2 is the output terminal,
3 is a power supply, 7 is a PMOS transistor for the front stage, 8 is an NMO3) transistor for the front stage, 9 is a front stage circuit section, 10 is a PMOS transistor for the rear stage, 11 is an NMOS transistor for the rear stage, 12 is a rear stage 1111 circuit section, 13.14 is an inverter, 15 is a 2-man powered NAND gate, 16 is a 2-man powered NO
This is the R gate. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Between a high potential power source and a low potential power source, a first transistor conductive in response to a first logic level of an input signal and a second transistor conductive in response to a second logic level of the input signal. a first stage circuit section in which the first and second transistors are connected in series in this order, and a connection point between the first and second transistors is connected to an output terminal; a third transistor that conducts in response to the first logic level of the input signal and a fourth transistor that conducts in response to the second logic level of the input signal are connected in series in this order; and a second stage circuit section in which the connection point of these third and fourth transistors is connected to the output terminal; An output buffer circuit comprising: a first conduction timing delay means for delaying the conduction timing; and a second conduction timing delay means for delaying the conduction timing of the fourth transistor by a predetermined period of time from the conduction timing of the second transistor.