JPH0575433A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To provide the input buffer circuit for a semiconductor integrated circuit in which input-output voltage characteristics has less difference in spite of a high/low supplied power voltage. CONSTITUTION:The input buffer circuit is provided with a P-channel MOS transistor(TR) 1 and an N-channel MOS TR 2 being components of an ESD protection circuit, a P-channel MOs TR 3, N-channel MOS TRs 4, 5 connecting to an external terminal 51 via a resistor 9 and forming a inverter a P-channel MOS TR 7 and an N-channel MOS TR 8 forming an inverter of an output stage, and an N-channel MOS TR 6 connected between a power supply terminal and a gate of the N-channel MOS TR 5 and controlling and adjusting an on- resistance of the N-channel MOS TR 4 in response to the high/low power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit, and more particularly to an input buffer circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional input buffer circuit of this type is
As shown in FIG. 2, a P-channel MOS transistor 1 having a source and a gate connected to a power supply terminal and a drain connected to the external terminal 52 corresponding to the external terminal 52.
0, the drain is connected to the external terminal 52, the N-channel MOS transistor 11 whose gate and source are connected to the ground point, the resistor 16 connected between the external terminal 52 and the node E, and the source is the power supply terminal. A P-channel MOS transistor 12 having a gate connected to node E and a drain connected to node F; a drain connected to node F, a gate connected to node E, and a source connected to ground. And an N-channel MOS transistor 13 having a source connected to a power supply terminal, a gate connected to a node F, and a drain connected to an internal circuit.
It is configured to include a transistor 14 and an N-channel MOS transistor 15 having a drain connected to an internal circuit, a gate connected to a node F, and a source connected to a ground point.

In FIG. 2, the P-channel MOS transistor 10 and the N-channel MOS transistor 11 are
A circuit for ESD protection is formed, and the external terminal 52
The input signal is level-inverted via the resistor 16 by the inverter formed by the P-channel MOS transistor 12 and the N-channel MOS transistor 13 and output to the node F, and the P-channel MOS transistor 14 and the N-channel MOS transistor are output. The signal is level-inverted again via the output stage inverter formed by 15 and is sent to the internal circuit.

In this conventional example, the W / L ratio corresponding to the channel width (W) and the channel length (L) of the P-channel MOS transistors 12 and 14 and the N-channel MOS transistors 13 and 15 is used. Is adjusted to realize an input buffer circuit that performs a TTL operation and a CMOS operation corresponding to the input signal level from the external terminal 52.

Incidentally, the node F corresponding to the circuit configuration of FIG.
An example of the input / output voltage characteristic in is shown by the reference numeral in FIG. It should be noted that FIG. 3 shows the characteristics in two cases where the power supply voltage is high and low.

[0006]

In the above-mentioned conventional input buffer circuit, by adjusting the W / L ratio of the P-channel MOS transistor and the N-channel MOS transistor forming the inverter, the TTL input level can be set by the CMOS transistor. Alternatively, a method of guaranteeing operation at the CMOS input level is used, but for various operating power supply voltages (2.5 to 6 V) used,
In order to guarantee the TTL input level or the CMOS input level, as in the conventional case, a MOS forming an inverter is used.
In the design method to adjust the W / L ratio of the transistor,
When the input voltage is high or low, the required specifications are not satisfied, and there is a drawback that it cannot support a wide range of operating power supply voltage.

[0007]

According to the input buffer circuit of the present invention, in a semiconductor integrated circuit, an input buffer circuit has a first P-channel MOS having a source and a gate connected to a power supply terminal and a drain connected to an external terminal. A transistor, a first N-channel MOS transistor having a drain connected to the external terminal, a gate and a source connected to a ground terminal, a source connected to a power supply terminal, and a gate connected to the external terminal via a predetermined resistor. A second P-channel MOS transistor connected to the second P-channel MOS transistor, a drain connected to the drain of the second P-channel MOS transistor, and a gate connected to the gate of the second P-channel MOS transistor. MOS
The transistor and the drain are the second N-channel MO
A third N-channel MOS transistor connected to the source of the S-transistor and having a drain connected to the ground terminal, and a semiconductor for controlling and adjusting the ON resistance value of the third N-channel MOS transistor in accordance with the power supply voltage level. The on-resistance value control circuit and the source are connected to the power supply terminal,
A third P-channel MOS transistor having a gate connected to the drain of the second P-channel MOS transistor, a drain connected to an internal circuit, a drain connected to the internal circuit, and a gate connected to the third circuit. P
A fourth N-channel MOS transistor connected to the gate of the channel MOS transistor and having a source connected to the ground terminal.

The semiconductor ON resistance value control circuit is
It may be formed by a fifth N-channel MOS transistor whose drain and gate are connected to the power supply terminal and whose source is connected to the gate of the third N-channel MOS transistor.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, the external terminal 51
Corresponding to, P-channel M whose source and gate are connected to the power supply terminal and whose drain is connected to the external terminal 51.
The OS transistor 1, an N-channel MOS transistor 2 having a drain connected to the external terminal 51 and a gate and a source connected to the ground point, a resistor 9 connected between the external terminal 51 and the node A, and a source A P-channel MOS transistor 3 connected to a power supply terminal, a gate connected to node A, a drain connected to node B, a drain connected to node B, a gate connected to node A, and a source connected to node C. An N-channel MOS transistor 4 connected thereto, and an N-channel MO whose drain is connected to the node C, the gate is connected to the node D, and the source is connected to the ground point.
An S-channel transistor 5, an N-channel M whose drain and gate are connected to a power supply terminal and whose source is connected to a node D
An OS transistor 6, a P-channel MOS transistor 7 having a source connected to a power supply terminal, a gate connected to a node B and a drain connected to an internal circuit; and a drain connected to an internal circuit and a gate connected to the node B. , N-channel MOS transistor 8 whose source is connected to the ground point
And is configured.

In FIG. 1, P-channel MOS transistor 1 and N-channel MOS transistor 2 are ES
A circuit for D protection measures is formed, and the signal input from the external terminal 51 is transmitted through the resistor 9 to the P channel MOS.
Transistor 3 and N-channel MOS transistor 4
Is input to the gate. A voltage obtained by subtracting the threshold voltage V _TN of the N-channel MOS transistor 6 from the power supply voltage is applied to the gate of the N-channel MOS transistor 5. The signal level at the node A is inverted and output at the node BN, and then inverted again via the inverter formed by the P-channel MOS transistor 7 and the N-channel MOS transistor 8 and output to the internal circuit.

In this case, the W / L ratio of each of the P-channel MOS transistors 3 and 7 and the N-channel MOS transistors 4, 5 and 8 is adjusted by adjusting this value to obtain an input signal from the external terminal 52. An input buffer circuit that implements TTL operation and CMOS operation corresponding to the level has been realized.

Corresponding to the circuit configuration of FIG.
An example of the input / output voltage characteristic in is shown by the reference numeral in FIG. It should be noted that FIG. 3 shows characteristic examples of the two cases where the power supply voltage is a high voltage and a low voltage as described above.

As is clear from the characteristic example of FIG.
When the power supply voltage is high, the voltage obtained by subtracting the threshold voltage V _TN of the N-channel MOS transistor 6 is
Although it is applied to the gate of the N-channel MOS transistor 5, since the power supply voltage is a high voltage, it is not affected by the decrease in the voltage level due to the subtraction of the threshold voltage V _TN. The characteristic example in the conventional example shows substantially the same characteristic. However, when the power supply voltage is low, the power supply voltage is low and the effect of the subtraction due to the threshold voltage V _TN becomes large,
The on-resistance of N-channel MOS transistor 5 is increased, whereby the logic threshold value is expanded as compared with the case of the conventional input buffer circuit. Thus, by controlling and adjusting the ON resistance value of the N-channel MOS transistor 5 via the N-channel MOS transistor 6 according to the level of the supplied operating power supply voltage, as shown in FIG. Compared to the example, it is possible to obtain a characteristic in which the difference in the input / output voltage characteristic corresponding to the level of the power supply voltage is compressed. That is, an input buffer circuit that can handle a wider range of operating power supply voltage is realized.

[0015]

As described above, according to the present invention, the N-channel MOS transistor is inserted and connected between the source of the N-channel MOS transistor included in the inverter and the ground point, and the on-resistance of the N-channel MOS transistor is connected. By controlling and adjusting the value according to the level of the power supply voltage, it is possible to reduce the difference in the input / output voltage characteristics due to the difference in the level of the power supply voltage, and to cope with a wide range of operating power supply voltage. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a diagram showing input / output voltage characteristics of an input buffer circuit.

[Explanation of symbols]

1, 3, 7, 10, 12, 14 P-channel MOS transistors 2, 4-6, 8, 11, 13, 15 N-channel MO
S transistor 9, 16 resistance

Claims (2)

[Claims] 1. An input buffer circuit according to a semiconductor integrated circuit, wherein a source and a gate are connected to a power supply terminal, a drain is connected to an external terminal, and a drain is connected to the external terminal. A first N-channel MOS transistor having a gate and a source connected to a ground terminal, and a second P-channel MOS transistor having a source connected to a power supply terminal and a gate connected to the external terminal through a predetermined resistor.
A transistor and a drain connected to the drain of the second P-channel MOS transistor, and a gate connected to the second P-channel M
A second N-channel MOS transistor connected to the gate of the OS transistor; a third N-channel MOS transistor whose drain is connected to the source of the second N-channel MOS transistor and whose drain is connected to the ground terminal; A semiconductor on-resistance value control circuit for controlling and adjusting the on-resistance value of the third N-channel MOS transistor according to a power supply voltage level, a source connected to a power supply terminal, and a gate for the second P-channel MOS transistor. A third P-channel MOS transistor having a drain connected to the internal circuit and a drain connected to the internal circuit; and a drain connected to the internal circuit and a gate connected to the third circuit.
And a fourth N-channel MOS transistor connected to the gate of the P-channel MOS transistor and having a source connected to the ground terminal. 2. The semiconductor on-resistance value control circuit is formed by a fifth N-channel MOS transistor having a drain and a gate connected to a power supply terminal and a source connected to the gate of the third N-channel MOS transistor. The input buffer circuit according to claim 1, wherein