JP2544796B2 - Input circuit of semiconductor integrated circuit device - Google Patents

Description

The present invention relates to an input circuit for a semiconductor integrated circuit device, and more particularly to an input circuit whose state is controlled by a clock signal.

[Prior Art] Conventionally, as an input circuit of this type, there is one shown in FIG. 2, for example. This input circuit is composed of an input protection resistor 1 having a resistance value of several KΩ and an input first stage circuit 2. The input protection resistor 1 is connected between the input terminal 3 for inputting an external signal and the input section of the input first stage circuit 2. The input first-stage circuit 2 becomes active when the clock signal φ input through the clock input terminal 4 is high, and an internal circuit (not shown) receives an input signal externally input through the input terminal 3 and the input protection resistor 1. It is to be sent to. The input first-stage circuit 2 includes a P-channel MOS transistor 5 and an N-channel MOS transistor 7 which form a CMOS inverter, a P-channel MOS transistor 6 which is connected in parallel with the P-channel MOS transistor 5 and whose conduction is controlled by a clock signal φ, and a CMOS. It is composed of an N-channel MOS transistor 8 connected in series with the inverter to selectively activate the input first stage circuit 2 based on the clock signal φ, and an inverter 9 provided at the output of the CMOS inverter. That is, P channel MOS
The source of the transistor 5 is the power supply V _DD , and its gate is N
Together with the gate of the channel MOS transistor 7, it is connected to one end of the input protection resistor 1 and serves as an input portion of the input initial stage circuit 2. The source of the P-channel MOS transistor 6 is connected to the power source V _DD together with the source of the transistor 5, and the gate thereof is the N-channel MOS transistor 8
Of the clock signal φ and the input terminal 4 to which the clock signal φ is input. The drain of the N-channel MOS transistor 7 is connected to the drains of the P-channel MOS transistors 5 and 6, and the gate thereof is connected to one end of the input protection resistor 1 together with the gate of the P-channel MOS transistor 5 described above. The source of the N-channel MOS transistor 8 is grounded, and its drain is the N-channel MOS transistor 7
Of the P channel MOS transistor 6 and the gate of the P channel MOS transistor 6 described above are connected to the input terminal 4. The input part of the inverter 9 is connected to the drains of the P-channel MOS transistors 5 and 6 and the N-channel MOS transistor 7, and its output part is connected to the input parts of other circuits as the output part of the input initial stage circuit 2. ing.

Next, the operation of the conventional input circuit thus configured will be described.

When the clock signal φ is at a high level (hereinafter referred to as “H”), the P-channel MOS transistor 6 is turned off and the N-channel MOS transistor 8 is turned on, so that the input first stage circuit 2 operates as a buffer (active). State), an external signal input via the input terminal 3 is taken into the inside of the semiconductor integrated circuit by the input first stage circuit 2.

When the clock signal φ is low level (hereinafter referred to as “L”), the P-channel MOS transistor 6 is turned on and the N-channel MOS transistor 8 is turned off, so that the output of the input first stage circuit 2 is fixed at L. Is performed (standby state). Therefore, in this case, the external signal input to the input first stage circuit 2 via the input terminal 3 is ignored and is not taken into the inside of this semiconductor integrated circuit.

[Problems to be Solved by the Invention] In the conventional input circuit described above, when the external signal input through the input terminal 3 becomes indefinite when the input initial stage circuit 2 is in the active state, the P-channel MOS transistor 5
The conduction states of the N-channel MOS transistor 7 and the N-channel MOS transistor 7 become indefinite, and a through current flows from the power supply V _DD to the ground through the P-channel MOS transistor 5 and the N-channel MOS transistor 7 and the N-channel MOS transistor 8 immediately in the conduction state. There is a problem. And in this case,
Since the output of the input first-stage circuit 2 is not fixed, the operating states of other circuits are not fixed, and the current consumption of the circuit increases.

The present invention has been made in view of the above problems, and provides an input circuit of a semiconductor integrated circuit device in which a circuit state is stable even when an external signal becomes indefinite and which does not cause an increase in current consumption. The purpose is to provide.

[Means for Solving the Problems] An input circuit of a semiconductor integrated circuit device according to the present invention is a CM for transmitting an input signal input through an input terminal to an internal circuit.
An OS inverter circuit, a first transistor interposed between the CMOS inverter circuit and at least one of a positive power source and a negative power source and controlled to be conductive by a clock signal, an input terminal of the CMOS inverter circuit, and a positive power source or a negative power source. A second transistor connected to a power source and turned on when the first transistor is turned on is controlled by the clock signal, and a resistor connected in series with the second transistor.

[Operation] In the present invention, the series circuit of the second transistor and the resistor is connected between the input portion of the CMOS inverter circuit for inputting an external signal and the positive power supply or the negative power supply, and the conductive state of the second transistor is provided. Are selected by a clock signal that controls the state of the input first-stage circuit. Therefore, when the first transistor connected in series with the CMOS inverter circuit is in the conductive state, that is, when the input first-stage circuit is in the active state, the input signal from the outside becomes undefined and the input of the CMOS inverter circuit becomes unstable. Even when the end is in a floating state, the second transistor is conductive, so that the input end is pulled up or pulled down to the positive power supply or negative power supply side. Therefore, according to the present invention, even if the input signal from the outside becomes indefinite, it is possible to provide the input section of the input first-stage circuit with a signal having a fixed logical value. Therefore, the circuit state can be always stabilized, and a semiconductor integrated circuit with low current consumption can be provided.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is different from the conventional example in that a series circuit of a resistor 10 and an N-channel MOS transistor 11 is newly connected between the input end of the input first stage circuit 2 and the ground. That is, one end of the resistor 10 is connected to one end of the input protection resistor 1 and the commonly connected gates of the P-channel MOS transistor 5 and the N-channel MOS transistor 7 forming the CMOS inverter, and the other end of the resistor 10 is connected to the N-channel MOS transistor 11. It is connected to the drain. N-channel MOS transistor 11
Is grounded, and its gate is connected to the input terminal 4 to which the clock signal φ is input. here,
The resistance 10 is designed to have a resistance value sufficiently larger than that of the input protection resistance 1, for example, a relatively high resistance value of about several MΩ.

Next, the operation of the input circuit according to this embodiment configured as described above will be described.

When the clock signal φ input through the input terminal 4 is L, the N-channel MOS transistor 8 is turned off, so that the input first stage circuit 2 is in the standby state. At this time, the N-channel MOS transistor 11 is turned off,
This input circuit functions exactly as in the case where L is input as the clock signal φ in the conventional input circuit.

When the clock signal φ is H, the N channel MO
Since the S transistor 8 is turned on, the input first stage circuit 2 becomes active. At this time, N-channel MOS
Since the transistor 11 is turned on, the P channel MOS
The gates of the transistor 5 and the N-channel MOS transistor 7 are connected to the ground through the resistor 10 and the on-resistance of the N-channel MOS transistor 11. In such a state, the voltage of the external signal applied to the input section of the input first-stage circuit 2 is the voltage of the external signal at the input terminal 3 when the output impedance of the circuit that outputs the external signal is ignored. 10 and N channel MOS transistor 1
It is a value divided by the on resistance of 1. However, as described above, the resistance value of the input protection resistor 1 is several KΩ.
On the other hand, the resistance value of the resistor 10 is several MΩ, which is sufficiently larger than that of the input protection resistor 1. Therefore, the voltage applied to the input section of the input first stage circuit 2 is the input terminal 3 The voltage of the input signal is substantially equal to the voltage of the external signal at, and this input circuit can function as a conventional input circuit.

Further, when the output of the external circuit that generates the external signal when the clock signal φ is H is in the high impedance state, the external signal input through the input terminal 3 becomes indefinite, but the input first-stage circuit The gate potentials of the P-channel MOS transistor 5 and the N-channel MOS transistor 7 that form part 2 are pulled down to the ground potential via the resistor 10 and the N-channel MOS transistor 11. As a result, the P-channel MOS transistor 5 and the N-channel MOS transistor 7
Are turned on and off, respectively, and H is applied to the input part of the inverter 9. The output of the inverter 9 which is also the output of the input first stage circuit 2 is fixed to L, and the circuit state becomes stable. Also, the output L of the input first stage circuit 2
The state of other circuits that input is also stable.

As described above, in the present embodiment, even if the external signal becomes indefinite when the input initial stage circuit 2 is in the active state, the circuit state can be stabilized. Therefore, it is possible to eliminate the current consumption of the circuit caused by the indeterminate external signal.

[Effects of the Invention] As described above, according to the present invention, when the input circuit is in a state of taking in an external signal, the input portion of the CMOS inverter circuit is pulled up or pulled up to the extent that the logical amplitude of the external signal is not affected. Pull down. Therefore, the input level of the CMOS inverter circuit is fixed even if the external signal becomes undefined,
Since the circuit state of the input circuit can be stabilized, an input circuit with low current consumption can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention,
FIG. 2 is a circuit diagram showing a conventional input circuit. 1; Input protection resistor, 2; Input first stage circuit, 3, 4; Input terminal, 5, 6;
P-channel MOS transistor, 7,8,11; N-channel MOS transistor, 9; Inverter, 10; Resistor

Claims (1)

(57) [Claims] 1. A CMOS inverter circuit for transmitting an input signal input via an input terminal to an internal circuit, and conduction control by a clock signal interposed between this CMOS inverter circuit and at least one of a positive power supply and a negative power supply. And a second transistor connected between the input terminal of the CMOS inverter circuit and a positive power supply or a negative power supply and being controlled by the clock signal when the first transistor is conductive. And an input circuit for a semiconductor integrated circuit device, comprising: a resistor connected in series with the resistor;