JPS58219771A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS58219771A JPS58219771A JP10261482A JP10261482A JPS58219771A JP S58219771 A JPS58219771 A JP S58219771A JP 10261482 A JP10261482 A JP 10261482A JP 10261482 A JP10261482 A JP 10261482A JP S58219771 A JPS58219771 A JP S58219771A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bypass
- power source
- power supply
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims 1
- 238000009877 rendering Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路に関するものであシ、特に非動作時に
非導通状態となし、消費電力の低減を計ったMO8集積
回路の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit, and more particularly to an improvement of an MO8 integrated circuit which is rendered non-conductive during non-operation to reduce power consumption.
MO8集積回路の発展は従来バイポーラ技術を用いてい
たアナログ集積回路へも浸透し始めている。これは回路
設計技術およびプロセス技術の開発に伴ない、アナログ
回路の基本特性の−っである入力オフセット電圧の低減
等が可能となったためであろう。またアナログ回路とデ
ジタル回路が混在する集積回路の開発要求が強まり、従
来デジタル回路に応用されていたMO8集積回路をアナ
ログの分野でも利用することが増加しつつある。The development of MO8 integrated circuits is beginning to penetrate analog integrated circuits that traditionally used bipolar technology. This is probably because, with the development of circuit design technology and process technology, it has become possible to reduce the input offset voltage, which is one of the basic characteristics of analog circuits. Furthermore, there is an increasing demand for the development of integrated circuits in which analog and digital circuits coexist, and MO8 integrated circuits, which have been conventionally applied to digital circuits, are increasingly being used in the analog field.
このようにアナログ回路を内蔵したMO8集積回路にお
いては正負の2電源および接地端子が必要となる。この
2 t、源を使用するため、非動作時に非導通状態とす
る制御が複雑となる。通常、非導通状態とするためには
、外部電源端子よυMOSトランジスタを通して内部の
動作回路へ電1圧を供給するのが一般的である。前記M
O8)ランジスタは動作時にゲート電極をON状態とな
る様に構成される。例えばNチャネルMO84積回路に
おいては正電源側に前記非導通手段を有し、MOSトラ
ンジスタのゲート電極を動作時は正電源に接続し、非動
作時には負電源側に接続することになる。このように動
作状態において、導通争非動通を制御することは消費電
力の低減に寄与し、装置設計上の利点となることは明ら
かであろう。In this way, an MO8 integrated circuit incorporating an analog circuit requires two positive and negative power supplies and a ground terminal. Since this 2t source is used, control to make it non-conductive during non-operation becomes complicated. Normally, in order to make the device non-conductive, one voltage is generally supplied to the internal operating circuit through the external power supply terminal and the υMOS transistor. Said M
O8) The transistor is configured so that the gate electrode is in the ON state during operation. For example, in an N-channel MO84 product circuit, the non-conducting means is provided on the positive power supply side, and the gate electrode of the MOS transistor is connected to the positive power supply during operation, and to the negative power supply during non-operation. It is clear that controlling conduction and non-conduction in the operating state contributes to a reduction in power consumption and is an advantage in device design.
しかしながら、正負2電源を使用するMOS集積回路に
おいては、前記非導通手段において欠点を有していた。However, a MOS integrated circuit using two positive and negative power supplies has a drawback in the non-conducting means.
例えばNチャネルMOS集積回路を一例として考えると
、第1図の如き回路が考えられる。第1図において、1
は正電源、2は負電源端子、3は接続端子であり、正電
源端子1と内部回路5の間にMOS)ランジスタ4を挿
入してのゲート電極端子6の電圧を制御することによυ
内部回路5への非導通、導通を制御している。かかる回
路においてM”OSトランジスタ4の制御電圧は、正お
よび負電源が接続されている際は問題ないが負の電源が
開放状態となシ、ゲート電極6の電位が接地電位となる
と、MOSトランジスタ4の制御端子であるゲート電極
6は接地される。For example, considering an N-channel MOS integrated circuit as an example, a circuit as shown in FIG. 1 can be considered. In Figure 1, 1
is a positive power supply, 2 is a negative power supply terminal, and 3 is a connection terminal. By inserting a MOS transistor 4 between the positive power supply terminal 1 and the internal circuit 5 and controlling the voltage of the gate electrode terminal 6, υ
It controls non-conduction and conduction to the internal circuit 5. In such a circuit, there is no problem with the control voltage of the M''OS transistor 4 when the positive and negative power supplies are connected, but when the negative power supply is in an open state and the potential of the gate electrode 6 becomes the ground potential, the MOS transistor Gate electrode 6, which is the control terminal of 4, is grounded.
通常、MOS)ランジスタ4はテプリーシせン形を用い
ており、このしきい値電圧は負であるため、MOSトラ
ンジスタ4のソース電極、即ち内部回路5の電圧は正と
なる。とのたゆ内部回路5の牛で正電源と接地間で動作
する部分にMOSトランジスタ4を介して電圧が印加さ
れてしまい誤動作を生じることがあった。これはMOS
)ランジスタ4が準しきい値領竣で動作し、内部にお・
いても準しきい像領域で動作すれば内部動作が不モ分の
ままデジタル出力が行なわれてし壕うためである。Normally, the MOS transistor 4 uses a Teplissian transistor, and its threshold voltage is negative, so the voltage of the source electrode of the MOS transistor 4, that is, the internal circuit 5, is positive. Voltage was applied via the MOS transistor 4 to a portion of the internal circuit 5 that operated between the positive power supply and the ground, sometimes resulting in malfunction. This is MOS
) The transistor 4 operates at the semi-threshold level, and the internal
This is because, even if the device operates in the quasi-threshold region, digital output will be performed while the internal operation remains unresolved.
本発明の目的はかかる誤動作を除き、非動作時における
非導通状態を安定にし、誤動作のなシ尋40S集積回路
を提供することにある。An object of the present invention is to eliminate such malfunctions, stabilize the non-conducting state during non-operation, and provide a 40S integrated circuit that does not malfunction.
以下に図面を用いて本発明の実施例を詳細に説明する。Embodiments of the present invention will be described in detail below using the drawings.
第2図は本発明の詳細な説明図であシ、第1図と同じ個
所には同じ番号を用いている。FIG. 2 is a detailed explanatory diagram of the present invention, and the same numbers are used for the same parts as in FIG.
第2図において、第1図との相異点はλ108トランジ
スタ4のソース電極と負電源2間にバイパス回路17を
接続しておる点である。バイパス回路17は負電源2が
開放となり接地型1位となった時に、MOSトランジス
タ4のバイパス回路として動作し、内部回路5に誤動作
を生じさせない動きを有している。このバイパス回路1
7により負電源が開放とたった時でもMOS集積回路は
安定して動作するためその効果は有用である。The difference between FIG. 2 and FIG. 1 is that a bypass circuit 17 is connected between the source electrode of the λ108 transistor 4 and the negative power supply 2. The bypass circuit 17 operates as a bypass circuit for the MOS transistor 4 when the negative power supply 2 is opened and becomes the first ground type, and has a function that prevents the internal circuit 5 from malfunctioning. This bypass circuit 1
7 allows the MOS integrated circuit to operate stably even when the negative power supply is open, so this effect is useful.
第3図(a)〜(C)にバイパス回路の例を示す。第3
図(a)はゲートを端子2に接続したディプレッジ冒ン
MO8)う/ジスタを用いた場合を、同図伽)はケート
をドレインに接続したエンノ・ンスMOSトランジスタ
を、同図(C)は抵抗を用いた場合である。Examples of bypass circuits are shown in FIGS. 3(a) to 3(C). Third
Figure (a) shows the case where a depletion transistor is used with the gate connected to terminal 2, Figure (c) shows the case of using an encoder MOS transistor with the gate connected to the drain. This is the case when a resistor is used.
なお本実施例はNチャネル形MO8集積回路を一例とし
て説明しであるが、これはPチャネル形でも同様であシ
、正負の電源を逆とし制御電圧を逆極性とすれば容易に
考えられるものであ石ことは明白である。なおバイパス
回路17はMOS)ランジスタ4のソース電極電圧を十
分に開放された負電源2に近ずけるものであれば何でも
良い。Although this embodiment is explained using an N-channel type MO8 integrated circuit as an example, the same applies to a P-channel type, and can be easily considered by reversing the positive and negative power supplies and making the control voltage have the opposite polarity. It's obvious that it's hard. Note that the bypass circuit 17 may be any circuit as long as it can bring the voltage of the source electrode of the MOS transistor 4 sufficiently close to the open negative power supply 2.
以上、図面を用いて詳細に説明した如く、本発明を用い
れば非動作時に非導通状態とするMOS集積回路を誤動
作たく設計できるため、MOS集積回路のデジタル・ア
ナログ回路混在形の実現に非常に有効である。As described above in detail with reference to the drawings, the present invention allows MOS integrated circuits that are non-conductive during non-operation to be designed to prevent malfunctions. It is valid.
第1図は従来回路図の説明図、第2図は本発明の詳細な
説明図をそれぞれ示す。第3図(a)〜(C)はバイパ
ス回路の例を示す図である。
1・・・・・・正電源、2・・・・・・負電源、3・・
・・・・接地端子、4・・・・・・MOS)ランジスタ
、5・・・・・・内部回路、6・・・・・・制御端子、
17・・・・・・バイパス回路。
躬−1局
82図
躬3図
to) (b)4≦
(CジFIG. 1 is an explanatory diagram of a conventional circuit diagram, and FIG. 2 is a detailed explanatory diagram of the present invention. FIGS. 3(a) to 3(C) are diagrams showing examples of bypass circuits. 1...Positive power supply, 2...Negative power supply, 3...
...Ground terminal, 4...MOS) transistor, 5...Internal circuit, 6...Control terminal,
17... Bypass circuit. (b) 4≦ (C di
Claims (1)
O8集積回路を非導通状態とする手段を一方の電源側に
有し、該非導通手段の出力と他方の電源間にバイパス手
段を設けたことを特徴とする集積回路。In MO8 integrated circuits using dual power supplies, M
1. An integrated circuit comprising means for rendering the O8 integrated circuit non-conductive on one power supply side, and bypass means provided between the output of the non-conducting means and the other power supply.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10261482A JPS58219771A (en) | 1982-06-15 | 1982-06-15 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10261482A JPS58219771A (en) | 1982-06-15 | 1982-06-15 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58219771A true JPS58219771A (en) | 1983-12-21 |
Family
ID=14332118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10261482A Pending JPS58219771A (en) | 1982-06-15 | 1982-06-15 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58219771A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0375037A2 (en) * | 1988-12-20 | 1990-06-27 | Koninklijke Philips Electronics N.V. | Protection of power integrated circuits against load voltage surges |
-
1982
- 1982-06-15 JP JP10261482A patent/JPS58219771A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0375037A2 (en) * | 1988-12-20 | 1990-06-27 | Koninklijke Philips Electronics N.V. | Protection of power integrated circuits against load voltage surges |
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