JP3939041B2 - CMOS buffer circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a buffer circuit having a so-called CMOS (Complementary MOS) transistor, and more particularly to a circuit that suppresses a through current and saves power.
[0002]
[Prior art]
Conventionally, as this type of circuit, for example, there is one having a configuration as shown in FIG.
The configuration and operation of the CMOS buffer circuit will be generally described below with reference to FIG. 1. First, the CMOS buffer circuit includes first and second NOR gate portions 31 and 32, and first and second NAND gates. The parts 33 and 34 are roughly divided into the parts.
The first NOR gate 31 is configured by using first and second P-channel CMOS transistors MP1 and MP2 and first and second N-channel CMOS transistors MN1 and MN2, and outputs thereof. The signal is input to the second NAND gate unit 34.
[0003]
The second NAND gate portion 34 is configured by using third and fourth P-channel CMOS transistors MP3 and MP4 and third and fourth N-channel CMOS transistors MN3 and MN4. The output signal of the second NAND gate 34 is applied to the gate of the ninth P-channel CMOS transistor MP9, which is one of the output stage transistors, and to the first NAND gate 33. It has become.
[0004]
The first NAND gate 33 is configured by using fifth and sixth P-channel CMOS transistors MP5 and MP6 and fifth and sixth N-channel CMOS transistors MN5 and MN6, and outputs thereof. The signal is applied to the second NOR gate unit 32.
The second NOR gate portion 32 is configured by using seventh and eighth P-channel CMOS transistors MP7 and MP8 and seventh and eighth N-channel CMOS transistors MN7 and MN8. The output signal of the second NOR gate section 32 is applied to the gate of the ninth N-channel CMOS transistor MN9, which is the other output stage transistor, and also applied to the first NOR gate section 31. It has become.
[0005]
The first control terminal 43 is connected to the gate of the third N-channel CMOS transistor MN3 and the gate of the fourth P-channel CMOS transistor MP4, and the eighth P-channel CMOS transistor MP8 and the eighth N-channel are connected. A second control terminal 44 is connected to the CMOS transistor MN8 and serves as a terminal for inputting a signal for controlling the operation state of the buffer circuit. That is, in a state where a signal corresponding to the logical value High is applied to the first control terminal 43 and a signal corresponding to the logical value Low is applied to the second control terminal 44, the buffer circuit includes the input terminal 41. A signal is output to the output terminal 42 in accordance with the input signal.
On the other hand, when the signal corresponding to the logic value Low is applied to the first control terminal 43 and the signal corresponding to the logic value High is applied to the second control terminal 44, the buffer circuit Both the P-channel CMOS transistor MP9 and the ninth N-channel CMOS transistor MN9 are turned off. Therefore, the impedance at the output terminal 42 is a so-called high impedance, and this buffer circuit can be used as a so-called tristate buffer circuit.
[0006]
In this configuration, the buffer circuit has an input terminal in a state where a signal corresponding to the logical value High is applied to the first control terminal 43 and a signal corresponding to the logical value Low is applied to the second control terminal 44. 41, when a signal corresponding to the logical value High is applied to the output terminal 42, a signal corresponding to the logical value Low is applied to the output terminal 42, and when a signal corresponding to the logical value Low is applied to the input terminal 41. The output terminal 42 can obtain signals corresponding to the logical value High.
This buffer circuit suppresses a so-called through current in the ninth P-channel CMOS transistor MP9 and the ninth N-channel CMOS transistor MN9 which are output stage transistors, and is applied to an integrated circuit. This is excellent in preventing malfunction of the circuit due to the occurrence of the through current, suppressing unnecessary power consumption in the output transistor, and the like.
[0007]
[Problems to be solved by the invention]
However, in the case of the conventional buffer circuit described above, the total number of P and N channel CMOS transistors is 18 and the number of parts is large, and particularly when used in an integrated circuit, the number of parts is smaller and the same function is achieved. What you want to do is desired.
In addition, although a so-called through current in the output transistor is small, there is a problem in that the current consumption of the entire buffer circuit is not reduced so much because there is a through current in the CMOS transistor constituting the preceding logical operation circuit.
[0008]
The present invention has been made in view of the above circumstances, and provides a buffer circuit capable of suppressing a through current of a transistor in an output stage with a simple circuit configuration. Another object of the present invention is to provide a CMOS buffer circuit that consumes less current and can suppress a through current of a transistor in an output stage.
[0009]
[Means for Solving the Problems]
  In order to solve the above problem, a CMOS buffer circuit according to the present invention is a CMOS buffer circuit in which an output stage is configured by a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power source and a ground. The first P-channel CMOS transistor for input control and the second P-channel CMOS transistor as the transfer switch element are directly connected between the gate and the input terminal of the P-channel CMOS transistor constituting the output stage. A first N-channel CMOS transistor for input control and a second N-channel as a transfer switch element are provided between the gate and the input terminal of the N-channel CMOS transistor that are connected and constitute the output stage. CMOS transistors connected in series The gate of the second P-channel CMOS transistor is connected to the gate of an N-channel CMOS transistor constituting the output stage, and the gate of the second N-channel CMOS transistor constitutes the output stage. A third P-channel CMOS transistor and a third N-channel CMOS transistor are connected in series between the power source and the ground, and are connected to the gate of the P-channel CMOS transistor. The gate of the channel CMOS transistor is connected to the gate of the second N-channel MOS transistor, and the gate of the third N-channel CMOS transistor is connected to the gate of the second P-channel CMOS transistor. Said third P-cha The drains of the N-channel CMOS transistor and the third N-channel CMOS transistor are connected to the gate of the fourth P-channel CMOS transistor and the gate of the fourth N-channel CMOS transistor. The power supply voltage is applied, while the drain is connected to the gate of a P-channel CMOS transistor constituting the output stage, the source of the fourth N-channel CMOS transistor is connected to ground, and the drain is connected to the output Connected to the gate of the N-channel CMOS transistor constituting the stage, the drain and the source of the P-channel CMOS transistor constituting the output stage, and the source and the source of the P-channel CMOS transistor constituting the output stage, respectively. The connected fifth P-channel CMOS transistor for output control, the drain connected to the gate of the N-channel CMOS transistor constituting the output stage, and the source connected to the source of the N-channel CMOS transistor constituting the output stage, respectively. The output control fifth N-channel CMOS transistor is provided, and the input control first N-channel CMOS transistor and the output control fifth P-channel CMOS transistor are the first control. The operation state of the first P-channel CMOS transistor for input control and the fifth N-channel CMOS transistor for output control are controlled by the signal applied to the second control terminal by the signal applied to the terminal, respectively. It is configured to be possible.
[0012]
In such a configuration, in particular, the second P-channel CMOS transistor and the second N-channel CMOS transistor are used as transfer switch elements for transmitting input signals to the gates of the P-channel CMOS transistor and the N-channel CMOS transistor constituting the output stage. Each channel CMOS transistor is provided and connected to each other so that the gate voltage of the transistor of the other output stage is fed back, so that so-called through current of the output stage can be suppressed.
That is, the gate voltage of the CMOS transistor constituting the other output stage is fed back to the respective gates of the second P-channel CMOS transistor and the second N-channel CMOS transistor as transfer switch elements. Therefore, the two CMOS transistors constituting the output stage become conductive at the same time, and the other becomes non-conductive. Unlike the conventional case, the period in which the two CMOS transistors constituting the output stage are simultaneously turned on is extremely short. Therefore, the through current is suppressed.
Further, an input control CMOS transistor is provided between the second P-channel CMOS transistor as the transfer switch element and the input terminal, and between the second N-channel CMOS transistor as the transfer switch element and the input terminal. On the other hand, a P-channel CMOS transistor and an N-channel CMOS transistor for output control are provided, and by applying a signal from the outside to the gates of the input control CMOS transistor and the output control CMOS transistor, the operation state is changed. Since the output stage can be set to a so-called high impedance state regardless of the state of the input signal, it can be used as a so-called tristate buffer circuit.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the configuration of the buffer circuit (hereinafter referred to as “the present circuit”) shown in FIG. 1 will be described.
In this circuit, the output stage includes a sixth P-channel CMOS transistor (denoted as “MP6” in FIG. 1) 6 and a sixth N-channel CMOS transistor (denoted as “MN6” in FIG. 1) 16. Thus, a so-called push-pull output circuit is configured. A sixth P-channel CMOS transistor (hereinafter referred to as “sixth PMOS”) 6 is a first and second P-channel CMOS transistor (indicated as “MP1” and “MP2” in FIG. 1, respectively). 1 and 6, a sixth N-channel CMOS transistor (hereinafter referred to as “sixth NMOS”) 16 is connected to first and second N-channel CMOS transistors (in FIG. 1, “MN1”, “ The input signals applied to the input terminals 21 are input via the input terminals 11 and 12, respectively, and the operation state as described later is set in accordance with the input signals. Yes.
[0014]
That is, the drains of the sixth PMOS 6 and the sixth NMOS 16 are connected to the output terminal 22, while the power supply voltage VDD is applied to the source of the sixth PMOS 6, and the source of the sixth NMOS 16 is grounded. The sixth PMOS 6 and the sixth NMOS 16 are directly connected between the power supply and the ground.
On the other hand, an input signal to this circuit is applied to the input terminal 21, and a first P-channel CMOS transistor for input control (hereinafter referred to as “first PMOS”) is applied to the input terminal 21. The source of 1 is connected to the drain of a first N-channel CMOS transistor (hereinafter referred to as “first NMOS”) 11 for input control.
The gate of the first NMOS 11 is connected to the first control terminal 23 together with the gate of a fifth P-channel CMOS transistor (denoted as “MP5” in FIG. 1) 5 described later, while the gate of the first PMOS 1 Are connected to the second control terminal 24 together with the gate of a fifth N-channel CMOS transistor (indicated as “MN5” in FIG. 1) 15 described later. The first and second control terminals 23 and 24 are for controlling the operation state of the circuit. As will be described in detail later, the first and second control terminals 23 and 24 correspond to the application state of logic signals to the control terminals 23 and 24, respectively. The operation state of this circuit can be controlled.
[0015]
The drain of the first PMOS 1 is the source of a second P-channel CMOS transistor (indicated as “MP2” in FIG. 1) 2 as a transfer switch element, and the source of the first NMOS 11 is also the transfer switch element. Are connected to the drains of second N-channel CMOS transistors (denoted as “MN2” in FIG. 1) 12 respectively.
The drain of the second P-channel CMOS transistor (hereinafter referred to as “second PMOS”) 2 is connected to the gate of the sixth PMOS 6 and the second N-channel CMOS transistor (hereinafter referred to as “second PMOS”). Is connected to the gate of a third P-channel CMOS transistor (denoted as “MP3” in FIG. 1) 3 described later, and the source of the second NMOS 12 is The gate of the sixth NMOS 16 is connected to the gate of the second PMOS 2 and the gate of a third N-channel CMOS transistor (denoted as “MN3” in FIG. 1) 13.
[0016]
Thus, the second PMOS 2 is fed back to the gate of the second PMOS 2 with the gate voltage of the sixth NMOS 16 paired with the sixth PMOS 6 constituting the output stage to which the drain is connected. Is configured to connect.
The second NMOS 12 is connected so that the gate voltage of the sixth PMOS 6 paired with the sixth NMOS 16 constituting the output stage to which the source is connected is fed back to the gate of the second NMOS 12. It is configured.
[0017]
On the other hand, a third P-channel CMOS transistor (hereinafter referred to as “third PMOS”) 3 and a third N-channel CMOS transistor (hereinafter referred to as “third NMOS”) 13 are connected between the power source and the ground. Are connected in series. That is, the drain of the third PMOS 3 and the drain of the third NMOS 13 are connected to each other, and the gate of the fourth P-channel CMOS transistor (denoted as “MP4” in FIG. 1) 4 and the fourth It is connected to the gate of an N-channel CMOS transistor (denoted as “MN4” in FIG. 1) 14.
The source of the third PMOS 3 is supplied with the power supply voltage VDD, while the source of the third NMOS 13 is connected to the ground.
[0018]
A fourth P-channel CMOS transistor (hereinafter referred to as “fourth PMOS”) 4 has a source of a fifth P-channel CMOS transistor (hereinafter referred to as “fifth PMOS”) 5 for output control at its source. While the power supply voltage VDD is applied, the drain thereof is connected to the gate of the sixth PMOS 6 together with the drain of the fifth PMOS 5.
On the other hand, the drain of the fourth N-channel CMOS transistor (hereinafter referred to as “fourth PMOS”) 14 is the drain of the fifth N-channel CMOS transistor (hereinafter referred to as “fifth NMOS”) 15 for output control. In addition, the source of the fourth NMOS 14 is connected to the ground together with the source of the fifth PMOS 15 while being connected to the gate of the sixth NMOS 16.
[0019]
Next, the operation in this configuration will be described.
First, in a state where a signal corresponding to the logical value High is applied to the first control terminal 23 and a signal corresponding to the logical value Low is applied to the second control terminal 24, the logical value Low is applied to the input terminal 21. The operation when a signal corresponding to is input will be described.
Here, as a combination of the applied signals to the first and second control terminals 23 and 24, when one of the signals corresponding to the logical value High is applied, the other corresponds to the logical value Low. It is assumed that signals are input, both of which are applied with signals corresponding to the logical value High, and neither of which are applied with signals corresponding to the logical value Low.
[0020]
First, when a signal corresponding to the logical value High is applied to the first control terminal 23, the first NMOS 11 is turned on, while the fifth PMOS 5 is turned off. Further, when a signal corresponding to the logic value Low is applied to the second control terminal 24, the first PMOS 1 is turned on, while the fifth NMOS 15 is turned off. Therefore, the fifth PMOS 5 and the fifth NMOS 15 have no influence on the operating states of the sixth PMOS 6 and the sixth NMOS 16 constituting the output stage.
On the other hand, assuming that the line connecting the drain of the second PMOS 2 and the gate of the sixth PMOS 6 (indicated as “PGATE” in FIG. 1) is at a voltage level corresponding to the logical value High in this state. As a result, the third PMOS 6 and the sixth PMOS 6 are turned off, while the second NMOS 12 is turned on.
[0021]
Due to the conduction of the second NMOS 12, the line connecting the source of the second NMOS 12 and the gate of the sixth NMOS 16 (denoted as “NGATE” in FIG. 1) has the same level as the input terminal 21, that is, the logical value Low. It becomes the level corresponding to. As a result, the third NMOS 13 and the sixth NMOS 16 become non-conductive, while the second PMOS 2 becomes conductive. As a result, a line connecting the drain of the second PMOS 2 and the gate of the sixth PMOS 6 ( (Hereinafter referred to as “line PGATE”) has a level corresponding to the same logical value Low as that of the input terminal 21.
Therefore, the operation of each CMOS transistor that has been set to be conductive / non-conductive on the assumption that the line PGATE is at a level corresponding to the logical value High is as follows.
[0022]
That is, the second NMOS 12 is turned off, while the third PMOS 3 and the sixth PMOS 6 are both turned on.
Since the third PMOS 3 becomes conductive, the drain voltage becomes substantially the power supply voltage VDD, so that the fourth PMOS 4 becomes non-conductive while the fourth NMOS 14 becomes conductive. Due to the conduction of the fourth NMOS 14, a line connecting the source of the second NMOS 12 and the gate of the sixth NMOS 16 (hereinafter referred to as “line NGATE”) is held at the ground potential. It becomes a non-conductive state.
Therefore, the logical value High is output from the output terminal 22.
[0023]
In the above-described operation analysis, it is first assumed that the line PGATE is the logical value High, but the case where the line PGATE is assumed to be the logical value Low will be briefly described below. The PMOS 3 and the sixth PMOS 6 are turned on, while the second NMOS 12 is turned off.
Due to the conduction of the third PMOS 3, the fourth PMOS 4 becomes non-conductive, while the fourth NMOS 14 becomes conductive, and the line NGATE is held at the ground potential. Therefore, the sixth NMOS 16 is in a non-conductive state, while the second PMOS 2 is in a conductive state.
Due to the conduction of the second PMOS 2, the line PGATE is held at the logic value Low similarly to the input terminal 21, and eventually, the output terminal 22 is in the state of the logic value High.
[0024]
Further, in the above-described operation analysis, it is assumed that the line PGATE is initially the logical value High or the logical value Low. However, it is also assumed that the line NGATE is in the state of the logical value High or the logical value Low. As a result, the line PGATE has the same voltage level as that of the input terminal 21, the line NGATE has a voltage level corresponding to the logical value Low, and the output terminal 22 is in the state of the logical value High. There will be no change.
[0025]
Next, as for the case where a signal corresponding to the logical value High is applied to the input terminal 21, a temporary logical state of the line PGATE or the line NGATE is set in the same manner as described above, and each CMOS transistor corresponding thereto is set. By following the operation state, the operation state of each CMOS transistor can be finally determined. As a result, the output terminal 22 obtains the result that the logic value is Low. In this case, the line PGATE is held substantially at the level of the power supply voltage VDD, and the line NGATE is held at a voltage level corresponding to the same logical value High as that of the input terminal 21.
[0026]
Here, regarding the change in the output signal at the output terminal 22 with respect to the change in the input signal at the input terminal 21, the following can be said.
First, when the voltage of the input terminal 21 is increased from zero v to 5 v, the line PGATE increases in the same manner as the voltage change of the input terminal 21 with the circuit operation as described above, while the line NGATE is It remains at the level corresponding to the value Low. The line PGATE gradually approaches the cutoff voltage of the third PMOS 3 and the sixth PMOS 6 as the voltage at the input terminal 21 rises, and when the line PGATE becomes a voltage for conducting the second NMOS 12, the line NGATE Will rise to the same voltage as the input terminal 21.
[0027]
As the voltage of the line NGATE rises, the second PMOS 2 is turned off, the third and sixth NMOSs 13 and 16 are turned on, and the fourth PMOS 4 is turned on.
Due to the conduction of the fourth PMOS 4, the line PGATE rises to the power supply voltage VDD. As a result, the sixth PMOS 6 becomes non-conductive and the output terminal 22 becomes the logic value Low.
Thus, immediately before the output terminal 22 is switched from the logic value High level to the logic value Low level, the line PGATE has reached a voltage at which the sixth PMOS 6 is substantially cut off, and the sixth NMOS 16 Since the sixth PMOS 6 is in a non-conducting state at the same time as conduction is established, there is no through current flowing through the sixth PMOS 6 and the sixth NMOS 16.
[0028]
Conversely, when the voltage at the input terminal 21 is lowered from 5v to zero v, the voltage at the line NGATA falls in the same manner as the voltage change at the input terminal 21, while the line PGATE has a level corresponding to the logical value High. It remains.
Then, when the voltage of the line NGATE becomes a voltage for making the second PMOS 2 conductive, the line PGATE becomes the same voltage as the input terminal 21, and thereby the third PMOS 3 becomes conductive.
Further, due to the conduction of the third PMOS 3, the fourth NMOS 14 becomes conductive, and the line NGATE is lowered to the ground potential.
Then, the sixth PMOS 6 becomes conductive, and the output terminal 22 is in the state of the logical value High. Also in this case, since the sixth NMOS 6 becomes conductive and the sixth NMOS 16 is in a non-conductive state, there is no through current flowing through the sixth PMOS 6 and the sixth NMOS 16.
For this reason, the noise level of the earth line is very small. In particular, when this buffer circuit is used in an integrated circuit, the malfunction of the integrated circuit due to the noise is prevented and the power consumption current is reduced. It will be.
[0029]
Next, contrary to the operation state described above, a signal corresponding to the logic value Low was applied to the first control terminal 23 and a signal corresponding to the logic value High was applied to the second control terminal 24, respectively. The case will be described.
In this case, the first NMOS 11 is turned off by the signal applied to the first control terminal 23, while the fifth PMOS 5 is turned on. In addition, the first PMOS 1 is turned off by the signal applied to the second control terminal 24, while the fifth NMOS 15 is turned on.
Therefore, the non-conduction between the first PMOS 1 and the first NMOS 11 interrupts the transmission of the input signal at the input terminal 21 to the first PMOS 1 and the first NMOS 11 and thereafter. Further, since the sixth PMOS 6 is turned off by the conduction of the fifth PMOS 5 and the sixth NMOS 16 is turned off by the conduction of the fifth NMOS 15, the state of the signal applied to the input terminal 21 is connected to the output terminal 22. Regardless of this, no signal is output and a so-called high impedance state is obtained.
[0030]
Eventually, the present circuit applies to the output terminal 22 when a signal corresponding to the logical value High is applied to the first control terminal 23 and a signal corresponding to the logical value Low is applied to the second control terminal 24, respectively. The signal output according to the input signal to the input terminal 21 is obtained. That is, when the input signal is at a level corresponding to the logic value Low, the output terminal 22 has a logic value High. When the input signal is at a level corresponding to the logic value High, the output terminal 22 has a logic value Low. Each will be output.
On the other hand, when the signal corresponding to the logic value Low is applied to the first control terminal 23 and the signal corresponding to the logic value High is applied to the second control terminal 24, the output terminal 22 is connected to the input terminal 21. Regardless of the state of the input signal, it becomes a so-called high impedance state, and this circuit can be used as a so-called tri-state buffer circuit in which three kinds of output states can be set.
[0031]
【The invention's effect】
As described above, according to the present invention, unlike the conventional case, the input signal is applied to the transistors constituting the output stage without going through the arithmetic element, so that the parts can be compared with the conventional case. The number of points can be reduced.
In particular, an input signal is applied to each of the two CMOS transistors constituting the output stage via the transfer switch element, and the two transfer switch elements include the CMOS constituting the output stage to which each is connected. By adopting a configuration in which the gate voltage of the other CMOS transistor paired with the transistor is fed back, it is possible to avoid the timing at which the two CMOS transistors constituting the output stage become conductive at the same time. Therefore, it is possible to achieve the effects of reducing the current consumption and improving the reliability of the circuit operation.
Further, an input control CMOS transistor is provided between the second P-channel CMOS transistor as the transfer switch element and the input terminal, and between the second N-channel CMOS transistor as the transfer switch element and the input terminal. On the other hand, a P-channel CMOS transistor and an N-channel CMOS transistor for output control are provided, and by applying a signal from the outside to the gates of the input control CMOS transistor and the output control CMOS transistor, the operation state is changed. Since the output stage can be set to a so-called high impedance state regardless of the state of the input signal, it can be used as a so-called tristate buffer circuit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit configuration of a buffer circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a conventional circuit configuration.
[Explanation of symbols]
1... First P-channel CMOS transistor
2 ... Second P-channel CMOS transistor
3 ... Third P-channel CMOS transistor
4 ... Fourth P-channel CMOS transistor
5 ... Fifth P-channel CMOS transistor
6 ... Sixth P-channel CMOS transistor
11: First N-channel CMOS transistor
12 ... Second N-channel CMOS transistor
13 ... Third N-channel CMOS transistor
14 ... Fourth N-channel CMOS transistor
15 ... Fifth N-channel CMOS transistor
16: Sixth N-channel CMOS transistor
21 ... Input terminal
22 ... Output terminal
23. First control terminal
24 ... Second control terminal

Claims (1)

The output stage is a CMOS buffer circuit configured by a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power source and a ground,
A first P-channel CMOS transistor for input control and a second P-channel CMOS transistor as a transfer switch element are directly connected between the gate and input terminal of the P-channel CMOS transistor constituting the output stage. Provided,
Between the gate and the input terminal of the N-channel CMOS transistor forming the output stage, a first N-channel CMOS transistor for input control, the second N-channel CMOS transistor as the transfer switch element connected in series Provided,
The gate of the second P-channel CMOS transistor is connected to the gate of an N-channel CMOS transistor constituting the output stage, and the gate of the second N-channel CMOS transistor is a P-channel CMOS transistor constituting the output stage. While connected to the gate of
A third P-channel CMOS transistor and a third N-channel CMOS transistor are connected in series between a power supply and ground, and the gate of the third P-channel CMOS transistor is connected to the second N-channel CMOS transistor. A gate of the MOS transistor and a gate of the third N-channel CMOS transistor are respectively connected to a gate of the second P-channel CMOS transistor;
The drains of the third P-channel CMOS transistor and the third N-channel CMOS transistor connected to each other are connected to the gate of the fourth P-channel CMOS transistor and the gate of the fourth N-channel CMOS transistor,
The power supply voltage is applied to the source of the fourth P-channel CMOS transistor, while the drain is connected to the gate of the P-channel CMOS transistor constituting the output stage,
The source of the fourth N-channel CMOS transistor is connected to ground, while the drain is connected to the gate of the N-channel CMOS transistor constituting the output stage,
A fifth P-channel CMOS transistor for output control, in which a drain is connected to a gate of a P-channel CMOS transistor constituting the output stage, and a source is connected to a source of the P-channel CMOS transistor constituting the output stage; A fifth N-channel CMOS transistor for output control, in which the drain is connected to the gate of the N-channel CMOS transistor constituting the output stage, and the source is connected to the source of the N-channel CMOS transistor constituting the output stage; And
The first N-channel CMOS transistor for input control and the fifth P-channel CMOS transistor for output control are applied by a signal applied to the first control terminal,
The first P-channel CMOS transistor for input control and the fifth N-channel CMOS transistor for output control are configured such that their operation states can be controlled by a signal applied to a second control terminal, respectively. A CMOS buffer circuit characterized by the above.

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