JPH01272229A - Cmos input circuit - Google Patents

Abstract

PURPOSE:To prevent bad influence upon a circuit in the next stage by turning on a second MOS transistor TR by a control signal in case of an unfixed input voltage level to fix the potential of the output terminal of a CMOS inverter to a prescribed potential level and turning off a first MOS TR in this case to prevent flow of an unnecessary through current. CONSTITUTION:When a switch 3 is temporarily opened because of the power reduction of power consumption to stop the supply of the power supply voltage to a circuit 1 in the preceding stage, the voltage level of an output terminal 7 becomes unfixed, and the voltage level of an input terminal 11 of a CMOS input circuit 14 becomes unfixed. At this time, the potential of a line L1 goes to the ground level because of the existence of a pull-down resistance 4, and the potential of a control terminal 10 of the CMOS input circuit 14 goes to the ground level also. Then, a PMOS TR P3 is turned on to forcibly fix the potential of an output terminal 13 to the high level, and an NMOS TR N2 is turned off to completely cut off the current path between a power source and the ground, thereby preventing flow of an unnecessary through-current. Thus, bad influence upon the circuit in the next stage is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a CMO3
The present invention relates to an input circuit of the configuration.

[Conventional technology]

Conventionally, this type of CMOS input circuit is shown in FIGS. 3 and 4.
As shown in the figure, a PMOS transistor P5OS transistor N receives a signal input to an input terminal 49.
5, a power supply terminal 48 connected to a power supply 47, a ground terminal 50, and an input terminal 49.
It is comprised of a pull-down resistor 52 or a pull-up resistor 53 for fixing the level of the input signal so as not to adversely affect subsequent circuits when the potential of the input signal becomes unstable.

[Problem that the invention attempts to solve]

The conventional CMOS input circuit described above requires a pull-up resistor or a pull-down resistor for each input terminal, which increases the chip area and price when integrating this circuit on a semiconductor chip. The presence of the pull-up resistor and pull-down resistor lowers the input impedance, and when a signal is input to the input terminal, a current flows through the input terminal, resulting in an increase in current consumption.

[Means for solving problems]

A CMOS input circuit of the present invention includes: an input terminal; a control terminal to which a control signal is input that is output in response to a situation in which the voltage level of an input signal at the input terminal becomes unstable; MOS transistor of conductivity type and Mo3 of second conductivity type
a CMOS inverter that inverts and outputs the voltage level of an input signal applied to the input terminal; the MOS transistor of the first conductivity type and the MMOS transistor of the second conductivity type;
A first MOS transistor, which has a source/drain path interposed between it and the OS transistor, and becomes non-conductive when a control signal is input to the control terminal, and a predetermined DC potential and the output of the CMOS inverter. A source/drain path is interposed between the second MOS transistor and the second MOS transistor, which becomes conductive when a control signal is input to the control terminal.

(Function) When the voltage level of the input terminal becomes unstable, the second MOS transistor is turned on by the control signal, fixing the potential of the output terminal of the CMOS inverter to a predetermined potential level, and the first MOS transistor is turned off. By preventing unnecessary through-current from flowing, it is possible to prevent an adverse effect on the next stage circuit, and also to prevent an increase in current consumption.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a CMOS input circuit of the present invention.

The CMOS input circuit 14 of this embodiment has a gate commonly connected to the input terminal 11 to which the output signal of the output stage CMOS inverter 2 of the previous stage circuit 1 is input, the ground terminal 12, and the input terminal 11, and the CMOS inverter. Configuring PMOS
It consists of a transistor P2, an NMOS transistor N3, a control terminal 10 to which a control signal is input, an enhancement type PMOS transistor P3 and an enhancement type NMO5 transistor N2 whose gates are connected to the control terminal 10, and a power supply terminal 9.

Further, a power supply 5 is connected to the power supply terminal 6 of the front-stage circuit 1 and the control terminal 10 of the CMOS input circuit 14 via a switch 6 and a line L1, and a pull-down resistor 4 is connected between the line L1 and the ground. ing. Also, CMO
The power supply 5 is directly connected to the power supply terminal 9 of the S input circuit 14, and power supply voltage is always supplied thereto.

Next, the operation of this embodiment will be explained.

The switch 3 is closed, and the power terminal 6 of the front circuit 1 is closed.
When the power supply voltage is supplied to the pre-stage circuit 1, the pre-stage circuit 1 performs a predetermined signal processing operation and sends an output signal from the output-stage CMOS inverter 2 to the input terminal 11 of the CMOS input circuit 14. At this time, the control terminal lO of the CMOS input circuit 14
Since a power supply voltage is applied to through the line Ll, the PMOS transistor P3 is turned off and the NMOS transistor N2 is turned on. The signal from the previous stage circuit 1 input to the input terminal 11 is transmitted to the PMOS transistor P2.
The level of the signal is inverted by a CMOS inverter composed of an NMOS transistor N2 and an NMOS transistor N2, and the signal is outputted from an output terminal 13 to a next stage circuit (not shown). Next, in order to reduce power consumption, when the switch 3 is temporarily opened and the power supply voltage supply to the preceding stage circuit 1 is stopped, the voltage level of the output terminal 7 becomes undefined, and the voltage level of the CMOS input circuit 14 becomes unstable. The voltage level of the input terminal 11 also becomes unstable. At this time, the potential of line L1 is
Due to the presence of pull-down resistor 4, it becomes ground level,
The potential of the control terminal IO of the CMOS input circuit 14 also becomes the ground level. Then, the PMOS transistor P3 turns on, forcibly fixing the potential of the output i13 at a high level, and the NMOS transistor N2 turns off, completely cutting off the current path between the power supply and the ground, and eliminating unnecessary through-current. prevent from flowing.

In this way, even if the voltage level of the input terminal 11 becomes unstable, the potential of the output terminal 13 is fixed at a high level by the PMOS transistor P3, so that an adverse effect on the next stage circuit is prevented. By turning off the NMOS transistor N2, a through current is prevented from flowing.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

The CMOS input circuit 18 of this embodiment includes a plurality of input circuits shown in FIG. 1 (represented as two-input NAND gates in FIG.
6, a common emitter bipolar output stage transistor 20
The output signals of front-stage circuits 15 to 17 each having a load resistor 19 are input thereto, and interlocking switches 26 and 27 are provided so that when one circuit is open, the other circuit is closed. Note that the power supply voltage is supplied to the power supply terminal 53 of the CMOS input circuit 18 from the power supply 38, and the power supply voltage is supplied to the power supply terminal 53 of the CMOS input circuit 18.
is grounded.

When the switch 26 is closed, the front circuits 15 to 1
A signal input to each input terminal 23 of 7 is inverted in level by an NPN transistor 20 whose emitter is grounded via a terminal 25, and output from each output terminal 24 to an input terminal 30, 31, 32 of the CMOS input circuit 18. be done. At this time, the voltage level of the control terminal 29 is the same as that of the power supply 28, and the two-input NAND gates 34 to 36 send output signals corresponding to the input signals to the next stage circuit (not shown). On the other hand, when the switch 26 is opened, the switch 27 is closed in conjunction with this, and the voltage level of the control terminal 29 becomes the ground level. Then, the 2-input NAND gate 34~
The output of 36 is fixed at a high level regardless of the state of the input signal, thereby preventing malfunction of the next stage circuit.

〔Effect of the invention〕

As explained above, the present invention enables the control signal to control the CMO when the input level of the three CMO circuit is in an undefined state.
Turning on the MOS transistor connected to the output end of the MOS inverter to fix the potential at the output end to a predetermined level, and turning off the MOS transistor whose source-drain path is interposed between complementary transistors constituting the CMOS inverter. This has the effect of preventing adverse effects on the next stage circuit and preventing unnecessary through current from flowing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the CMO5 input circuit of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of a conventional example. 1.15, 16.17...Pre-stage circuit, 2...CM
OS inverter, 3, 26.27... Switch, 4... Pull-down resistor, 5, 28.38... Power supply, 6, 9.22.53... Power supply terminal, 7... Output terminal, 8, 12, 25.54...Ground terminal, 10, 29.
...Control terminal, 11, 23, 30, 31.32 ...Input terminal, 13
...Output end, 14.18---CMO3 input circuit, 34.35.36...2 input NAND gate, P2. P
3...PMOS transistor, N2, N3-
--NMOS transistor, Ll...line.

Claims (1)

[Claims] An input terminal; a control terminal into which a control signal is output in response to a situation in which the voltage level of an input signal at the input terminal becomes unstable; and a first conductivity type. MOS transistor and second conductivity type MOS
a CMOS inverter that inverts and outputs the voltage level of an input signal applied to the input terminal; the MOS transistor of the first conductivity type and the MMOS transistor of the second conductivity type;
A first MOS transistor, which has a source/drain path interposed between it and the OS transistor, and becomes non-conductive when a control signal is input to the control terminal, and a predetermined DC potential and the output of the CMOS inverter. a second MOS transistor having a source/drain path interposed between the terminal and the second MOS transistor, which becomes conductive when a control signal is input to the control terminal.