JPS60182217A - Signal input circuit - Google Patents

Abstract

PURPOSE:To prevent an output signal from being changed in a state change between the active and inactive states by disconnecting an inner node and an output node before a switch means inserted to a power voltage supply path is turned off. CONSTITUTION:When a selection signal changes from L to H, a transfer gate 30 is turned off before a signal CE1' is changed, the internal node 3 is disconnected from the output node 23 of an inverter 20. A signal Out of the node 3 after the disconnection is set to the original level by a latch signal of a latch circuit 5. Then the signal CE1' changes from L to H and an MOSFET24 is turned off. Even when a selection signal changes from H to L, the gate 30 is turned on before the signal CE1' is changed. Then the signal CE1' changes from H to L, the FET24 is turned on, and a signal of the node 23 corresponds to a signal in response to the input signal In. When the level of the signal at the node 23 and of the circuit 5 is the same, the level of the output Out is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an integrated circuit, and particularly to a signal input circuit provided at an input stage of an integrated circuit that is placed in two states, an active state and an inactive state.

[Technical background of the invention]

As a signal input circuit provided at the input stage of an integrated circuit,
Conventionally, the one shown in FIG. 1 is well known. The signal input circuit shown in FIG. 1 is used in an integrated circuit using a 0M08 circuit, and the signal input circuit 10 is activated in response to a selection signal CE that controls the active and inactive states of the circuit.
operation is controlled. That is, the input signal In supplied to input terminal 1 is input to each of the two P-channel MO8Fs.
ET 11, 12 and N-channel MO8FET 13
．． The signal is supplied to the inverter 2 via a program code input circuit 10 consisting of 14 circuits. The output signal Ou of this inverter 2
Furthermore, the signal Out of this internal node 3 is supplied to the internal circuit, such as a signal change detection circuit (
STD) 4. This signal change detection circuit 4 detects a change in the signal Out at the internal node 3 and generates a pulse signal φ, and the operation of other internal circuits is controlled by this signal φ.

In this circuit, the selection signal CE is now set to 'L',
When the internal circuit is activated, in the signal input circuit 10, the P-channel MO8F'ET 11 is turned on and the N-channel MO8FET J4 is turned off by the signal CF. Therefore, the signal input circuit 10 acts as a mere inverter and inverts the input signal In.

At this time, the signal O of the internal node 3 corresponds to the input signal In.
ut changes, which causes the signal detection circuit 4 to generate a pulse signal φ and other internal circuits to be controlled.

On the other hand, when the signal CE is set to 'H' and the internal circuit is inactivated, the signal input circuit is
The channel MO8FET 11 is turned off, thereby cutting off the supply path of the power supply voltage Vcc, and the N-channel MO8FET 14 is turned on by the signal CE, thereby causing the output node 15 of the signal input circuit
is set to "L". At this time, the input signal In is disconnected from the internal node 3, and the internal circuits including the signal change detection circuit 4 do not operate at all, thus achieving low power consumption. .

[Problems with background technology]

In the circuit shown in FIG. 1, when the signal CE is set to "L", the signal Out of the internal node 3 corresponds to the input signal In.
As a result, power is inevitably consumed in other internal circuits including the signal input circuit 10 and the signal change detection circuit 4.

However, when the signal d changes from “L” to “H#”,
If the input signal In is ``L#'', the signal input circuit 1
The signal at the 0 output node 15 changes from "H1" to "L", and the signal at the internal node 3 also changes from "H" to "L".

Then, the power consumption of the internal circuit driven by the signal Out of the internal node 3 and the 4th pulse signal φ increases, which becomes an obstacle to reducing power consumption. A particular problem is when the signal i changes smoothly from "L" to "H#".If the slope of the signal plane is relatively small, the signal d changes from "L" to "H#".
N-channel MO8FET 14 is not on at the intermediate level of output node 1.
5 signal falls to 1L#. Then, a current flows in the signal change detection circuit 4 and the internal circuit driven by the signal Out of the internal node 3, and noise is multiplied in the power supply line, especially the Vll supply line (earth line), and the Van supply line slightly increases. Sometimes it floats. Then, signal C
If the intermediate level of E is effectively the level of 1L,
The N-channel MO8FET 14 is inverted to the OFF state, and the signal at the output node 15 returns to 1H'', which causes current to flow through the signal change detection circuit 4 and the internal circuit again.The level of the signal CE continues to rise sequentially. Therefore, the signal CE is again regarded as @H" and the signal at the output node 15 is again @"
This causes a current to flow through the signal change detection circuit 4 and internal circuits. This is an extremely serious problem in so-called battery backup systems that supply power from a battery when inactive.

6- [Object of the Invention] This invention has been made in consideration of the above circumstances, and its purpose is to provide a method for changing the state from an active state to an inactive state or vice versa. The object of the present invention is to provide a signal input circuit in which the output signal does not change.

[Summary of the invention]

In order to achieve the above object, the present invention includes a first r-) circuit which receives an input signal, and a first r-) circuit which is interposed in the power supply voltage supply path of the first gate circuit and which selects activation or inactivation. a transistor whose conduction is controlled according to a control signal;
a second dart circuit inserted between the output node of the first dart circuit and the internal node and controlled by a second control signal; a latch circuit that latches a signal at the internal node; and a transistor in a conductive state. When the transistor is in the non-conducting state, the second dirt circuit is activated, and when the transistor is in the non-conducting state, the second dirt circuit is inactive, and the transistor is changed from the conducting state to the non-conducting state. In order to maintain a relationship such that the date circuit of chain 2 changes from the active state to the inactive state before this transistor becomes non-conductive. A signal input circuit is provided that includes a control signal generation circuit that generates a second control signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the signal input circuit of the present invention. Input signal I supplied to input terminal 1
n is inverter L! supplied to This inverter U consists of P-channel MO8FET j J and N-channel M
It is constructed by inserting O8FET 22 in series between the power supply voltage Vac application point and the ground point, and the above MO8FET
2 J.

The above input signal is input in parallel to 22 darts! A signal corresponding to Y is output from the output node 23, which is the series connection point. Furthermore, the P channel M of the inverter 20
A P-channel MO8FET is connected between the O8FET 21 and the voltage Vcc application point. (is inserted, this M
A control signal CE1 is supplied to the dart of OSFET 24. A transfer circuit 30 is inserted between the output node 23 of the inverter 20 and the internal node 3, and is constructed by connecting a P-channel MO8FET 31 and an N-channel MO8FET 32 in parallel. P channel MO8IT 3 in this transfer tree
Control signal CE2 is applied to dart No. 1, and N channel MO8F
The dart of ET32 has a control signal CE that is complementary to this.
2 are supplied respectively. In addition, the above internal node 3
A latch circuit 5 is connected to which latches the signal Out of the internal node 3 and supplies the latch signal to the internal node 3 again. Furthermore, in FIG. 2, 40 is a control signal generation circuit that generates the above-mentioned signals CE1 and CF2゜i, and includes six inverters 41 to 46 connected in series.
is for forming the above-mentioned control signal amount from the selection signal i that selects activation or inactivation of this circuit, and the two inverters 9-47 and 48 connected in series This is for forming the control signal CE2 and the signal.

In the signal input circuit having the above configuration, the selection signal C
When E is set to "L", the control signal i1 obtained as the output signal of the inverter 46 becomes 1L', and the control signal CE2 obtained as the output signal of the inverter 47 becomes 1H.
``, the control signal CE2 obtained as the output signal of the inverter 48 is set to ``L2,'' respectively. Therefore, MO8FET2 controlled by the above control signal cg1
4 is turned on, and the inverter 20 inverts the input signal In and supplies it to the output node 23.

On the other hand, the transfer gate 30 controlled by the control signal CE2*CF2 is also turned on, and the signal at the output node 23 of the inverter 20 is supplied to the internal node 3 via the transfer gate 30. The signal Out of this internal node 3 is then latched by the child circuit 5. Also, contrary to the above, if the selection signal CE is @H
”, the control signals CE1, CF2
, CF2 are set to "H", 'L', and 'H', respectively.

Therefore, at this time, MOSFET 24 and transfer gate 30 are turned off, and signal Out at internal node 3 is held at its original level by the latch signal of latch circuit 5.

Next, assume that the selection signal CE changes smoothly from the L# state to 'H'.When the signal CF changes from 'L' to 'H', the signal CE1 changes first. , the signal CE2 changes from H# to @L# and the signal CE2 changes from "
The transfer dart 30 is turned off and the internal node 3 is disconnected from the output node 23 of the internal node 23.The signal Out of the internal node 3 after being disconnected is is set to the original level by the latch signal of the latch circuit 5. After that, the signal C
E1 changes from 1L" to 1H" and MOSFET x
4 is turned off, and the power consumption of the internal circuitry is reduced. When the upper We MOSFET 24 is turned off, the output node 23 of the inverter LA has already been disconnected from the internal node 3, so the signal Out at the internal node 3 is latched regardless of the signal at the output node 23. It is held constant by circuit 5.

Next, the selection signal CF gradually changes from the "H" state to "
In this case, too, the signal CE2 changes from 'L#' to "H" before the signal CE1 changes, and the signal CE2 changes from "H" to "L". As a result, the transfer gate 30 that has been in the off state is turned on.After this, the signal CE1 becomes 1H.
The MOSFET 24 is turned on by changing from "to L", and the signal at the output node 23 is made to correspond to the input signal In. At this time, if the signal at the output node 23 changes to a different level from the latch signal of the latch circuit 5, the signal Out at the internal node 3 naturally changes, but if the levels of both signals are the same, the level of Out changes. do not.

In this way, according to the above embodiment circuit, the MOSFET 2 is used to supply the power supply voltage to the inverter 20 that receives the input signal In.
4, and before turning off this MOSFET 24 according to the selected signal plane, the transfer gate inserted between the output node 23 of the indirection and the internal node 3 is turned off, and the internal node 3 is turned off. Output node 23
After disconnecting, signal 01 of internal node 3
Since the level setting of 1t is performed by the latch circuit 5, it is possible to prevent the output signal from changing when transitioning from an active state to an inactive state or vice versa. Therefore, no wasteful current flows through the internal circuit whose operation is controlled by the signal Out of the internal node 3, so that low power consumption can be achieved, and applications such as battery packs and devices can be facilitated.

FIG. 3 is a circuit diagram showing a configuration according to another embodiment of the present invention. The difference between this embodiment circuit and the one in FIG. 2 is that an N-channel MO8FET 25 to which the control signal CE1 is input to f-) is connected between the output node 23 of the indirection and the ground point. and
A dirt circuit -SO is connected between the output node 23 of the inverter 20 and the internal node 3 in place of the transfer gate.
It is at the point where is inserted.

The above-mentioned dirt circuit includes an inverter 5B-, which is configured by inserting a P-channel MO8F'ET51 and an N-channel MO8FET 52 in series between the power supply voltage vcc application point and the ground point, and the P-channel MO8F' of this inverter 53. ET 51 and voltage ■. . A P-channel MO8FET 54 is inserted between the control signal CE2 and the voltage application point and is supplied with the control signal CE2.

In this embodiment circuit, the signal CE1 changes from "L" to "H".
When it changes to 1, MOSFET 2a is in the off state,
MOSFET 25 is in the on state, inverter 20
The signal at the output node 23 of is @ regardless of the input signal In.
It is set to L'. As a result, the P-channel MO8FET 5J in the r-.circuit 50 is turned on, but before the signal at the output node 23 is brought to @L'', the other MO8FET in the f-) circuit 50 is turned on by the signal CE2. Two P-channel MO8
Since FET 5a is turned off, the level of signal Out at internal node 3 does not change.

14- On the other hand, when CEL changes from 'H# to 'L#,
MOSFET 25 is in the off state, MOSFET 24
is turned on and the inverter is activated. Further, the signal CE2 changes from 'H' to 'L' before CEl, and the inverter is activated in advance, so that the signal at the output node 23 corresponding to the input signal In becomes the latch signal of the latch circuit 5. If they change to different levels, the signal -@Out of the internal node 3 naturally changes, but if both levels are the same, the level of Out does not change.

FIG. 4 is a circuit diagram showing one specific configuration of the latch circuit 5 used in each of the above embodiment circuits. This circuit is Vc
c P-channel MO8FETs 61 and 62 inserted in series between the application point and the ground point, respectively, and the N-channel MO
This is a flip frozzo circuit using two inverters each consisting of 8FETs 63 and 64. In this latch circuit, the current supply capability to the internal node 3 of the inverter whose output terminal is connected to the internal node 3 is different from that of the transfer dart u in the embodiment circuit of FIG. It is necessary to set it smaller than that of the ff-) circuit U in the example circuit shown in the figure. The reason for this is that when the inverter is active, it is necessary to freely set the signal Out at the internal node 3 according to the signal at the output node 23.

FIG. 5 is a circuit diagram showing another specific configuration of the latch circuit 5. This circuit has P between the vcc application point and the ground point.
Channel MO8FET 71 and two N-channel M
A first series circuit 74 formed by inserting O8FETs 72 and 73 in series, and a MOSFET 7 in this series circuit LJ.
P-channel MO8FET 76 connected between the series connection point 75 of J, 72 and the vcc application point, and the voe
P-channel MO8FET 7 between application point and ground point
7 and two N-channel MO8F'ET 78,7
9 inserted in series, and a second series circuit 80 in which MO8FET 71 is inserted in series.

The signal Out of the internal node 3 is supplied to the dart of MOSFET 72, the control signal CE2 is supplied to the dart of MOSFET 73 and 76, and the MO8F'ET 77 is supplied with the control signal CE2.
.

The signal at the series connection point 75 in the first series circuit 74 is supplied to the dart 78, and the r-
The control signal CE1 is supplied to the internal node 3, and the signal at the series connection point 81 of the MOSFETs 77 and 78 in the second series circuit is supplied to the internal node 3.

The latch circuit having such a configuration has the control signal CE1
e When CF2 is set to "L" and the inverter 20 etc. are activated, the MOSFET 76 is turned on, and the signal at the series connection point 75 in the first series circuit unit becomes the signal Out at the internal node 3. It is set to 'H' regardless of the condition.

Therefore, the P-channel MO8 in the second series circuit 80
FKT 77 is turned off. At this time, the signal CE
1, the j5N channel MO8FET 79 is also turned off, so the series connection point 8 in the second series circuit LJ, which is the output end of this latch circuit, is in a floating state.

Therefore, in this case, the signal Out of the internal node 3 can be freely set by the inverter 20 in FIG. 2 or 3. Next, before the signal CEl17- changes from “L” to “H#”, the signal amount changes to “L”.
” to “L”, MOSFET 73 is turned on, MOSFET 76 is turned off, and the level of the signal at the series connection point 75 of the first series circuit 7 is set according to the signal Out of the internal node 3. Then, by setting the signal CE1 to 1H", the MOSFET
79 is turned on, which causes the first. A latched state is entered by the second series circuit 74.80.

Therefore, there is no need to set the current supply capacity as in the case of FIG.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the embodiment circuit shown in FIG.
(After turning off the transfer adder 7 and deactivating the inverter 20, first turn on the transfer adder) and then activate the inverter. control may be performed so that the transfer adapter is turned on and then the transfer adapter is turned on.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a signal input circuit in which the output signal does not change when transitioning from an active state to an inactive state or vice versa.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional signal input circuit, FIG. 2 is a circuit diagram of one embodiment of the present invention, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIGS. 4 and 5 are Figures 2 and 3 respectively
FIG. 2 is a circuit diagram specifically showing a latch circuit used in the circuit shown in FIG. DESCRIPTION OF SYMBOLS 1... Input terminal, 3... Internal node, 5... Latch circuit, 20... Inverter, 23... Output node, 24... P channel MO8FET, J O...
Transfer gate, 40... control signal generation circuit, 5
0...Dirt circuit. 19- Figure 3 Figure 4 Figure 5 2 VSS Vss

Claims (5)

[Claims] (1) a first dart means that is supplied with an input signal and outputs a signal corresponding to the input signal from an output node;
an internal node to which the signal of the output node of the dart means is applied; a first switch means interposed in the power supply voltage supply path of the first dart means and switch-controlled in accordance with a first control signal; a second dart means inserted between the output node of the first dart means and the internal node and controlled by a second control signal; and a second dart means that holds the signal of the internal node and supplies the held signal to the internal node. a latch circuit that operates when the first switch means is changed from a conductive state to a non-conductive state by a first control signal; The above-mentioned 1. A signal input circuit comprising: control signal generating means for generating a second control signal. (2) The signal input circuit according to claim 1, wherein the second dart means is constituted by a transfer dart. (3) The second dart means is comprised of an inverter and a second switch means that is interposed in the power supply voltage supply path of the inverter and whose conduction is controlled by the second control signal. The signal input circuit according to item 1. (4) The signal input circuit according to claim 1, wherein the current supply capacity of the latch circuit to the internal node is set to be smaller than that of the second dart means. (5) The signal according to claim 1, wherein the child circuit is configured to hold the signal of the internal node when the first control signal is inactivated. input circuit.