JPH09161486A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and inexpensively mount on a board without any malfunction due to input noise. SOLUTION: When input signals are at high and low levels, an NMOS transistor 111 and a PMOS transistor 113 are respectively turned on and an input node A is fixed to each level. When an external input terminal IN is in floating state, an internal signal S1 becomes a low level and an NMOS transistor 109 is turned off and an output node B and a node C are separated and the NMOS transistor 111 is turned on by a pull-up resistor 107 and a power supply potential is given to the input node A, thus internally forcing to fix the node A to a high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device forming an input circuit that outputs a signal input to an internal circuit.

[0002]

2. Description of the Related Art When the number of external input terminals (input pins) of an input circuit of a semiconductor integrated circuit is about 100 pins or more, each wiring on a mounting board becomes difficult. However, although the address input / output pins and data input / output pins must be connected,
Many of the signal pins in the special mode are generally fixed at H (logical high) level or L (logical low) level according to the board specifications. For example, a burst sequence in a high-speed operation mode and a data input / output output method are examples.

It is in proportion to the number of pins on the board that the external input terminals are operated in a floating (unconnected) state without connecting them on the board to terminals for giving H level or L level. This is advantageous in that the assembly cost can be reduced and the defect rate such as wiring can be reduced.

Therefore, as shown in FIGS. 7 and 8 below, a pull-up resistor or a pull-down resistor is used to set the H level or L when the external input terminal is in a floating state.
The input signal of the level is given to the input node of the inverter which is the input buffer.

7 and 8 are circuit diagrams showing an example of an input circuit of a conventional semiconductor integrated circuit device.

Referring to FIG. 7, an input circuit 1100 includes an external input terminal IN and an inverter 11 which is an input buffer.
The pull-up resistor 107 is connected to the input node A of 01. The pull-up resistor 107 applies an H-level potential to the input node A even in a floating state in which a specific potential is not applied to the external input terminal IN, and an N-channel MOS transistor (hereinafter abbreviated as an NMOS transistor) of the inverter 1101. ) 121
Is turned on, and the potential of the output node B becomes L level.

Referring to FIG. 8, an input circuit 1200 includes an external input terminal IN and an inverter 11 which is an input buffer.
The pull-down resistor 207 is connected to the input node A of 01. The pull-down resistor 207 applies an L-level potential to the input node A even in a floating state in which a specific potential is not applied to the external input terminal IN, and the P-channel MOS transistor of the inverter 1101 (hereinafter abbreviated as a PMOS transistor). 119
Is turned on, and the potential of the output node B becomes H level.

FIG. 9 is a circuit diagram of an input circuit of a conventional semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 3-107213.

Referring to FIG. 9, an input circuit of a conventional semiconductor integrated circuit device is a latch circuit (2-4, T4, T5) controlled by a reset signal RST between an input terminal 100 and an input buffer 1. Are connected.

When the input terminal 100 is in a floating state or is at H level, the reset signal RST output from the CPU is at H level for a predetermined time, the NMOS transistor T5 of the latch circuit is turned off, and the PMOS transistor T5 is turned off.
The transistor T6 is turned on, an H level potential is applied to the input terminal 100, and the input terminal 100 is held at the H level.

When the input terminal 100 is at the L level, when the reset signal RST becomes the L level, the PMOS transistor T6 is turned off, the NMOS transistor T5 is turned on, the L level is given to the input terminal 100, and the input terminal 1
00 is held at the L level.

Therefore, even when the system is in a floating state at the time of system start-up or during system operation, the PMOS transistor T1 in the input buffer 1 is
Since the through current flowing from VDD connected to the source electrode of the NMOS transistor to the GND connected to the source electrode of the NMOS transistor T2 can be suppressed, low power consumption is achieved.

[0013]

However, when the pull-up resistor 107 is connected as in the input circuit 1100 of the conventional semiconductor integrated circuit device shown in FIG. 7,
When an L level input signal is input, pull-up resistor 1
There is a problem that a leak current flows from the power source Vcc to the external input terminal IN via 07.

Further, like the input circuit 1200 of the conventional semiconductor integrated circuit device shown in FIG. 8, the pull-down resistor 20 is used.
When 7 is connected, there is a problem that when an H-level input signal is input, a leak current flows from the external input terminal IN to the ground via the pull-down resistor 207.

In the normal input circuit, an H level or L level input signal is always input, but this occurs when the output signal changes after the input signal is input for a certain time or when the selection device changes. There is a problem that the semiconductor integrated circuit may malfunction by picking up input noise such as spike noise.

The input circuit of the conventional semiconductor integrated circuit shown in FIG. 9 has the number of branch circuit elements of the latch circuit as compared with the case where a pull-up resistor is connected as shown in FIG. 11 or a pull-down resistor is connected as shown in FIG. Therefore, if this input circuit is required for each input pin, the occupied layout area becomes large.

Further, like the input circuits 1100 and 1200 of the conventional semiconductor integrated circuit device of FIGS. 7 and 8, when an input signal having a phase opposite to the level of the data latched by the latch circuit is input from the input terminal. However, there has been a problem that a leak current flows between the input terminal and the output node of the latch circuit instantaneously.

The present invention has been made to solve the above problems, and leaks current from a potential supply means such as a power supply to an external input terminal, or from an external input terminal to a potential supply means such as a ground. Prevent the leakage current of
An object of the present invention is to provide a semiconductor integrated circuit device capable of preventing malfunction of the semiconductor integrated circuit due to input noise such as spike noise and switching of the input level.

Since a predetermined output level can be stably maintained even when the external input terminal is in a floating state, a semiconductor integrated circuit device which is easy and inexpensive to mount on a board even when it has a large number of input pins. provide.

[0020]

According to another aspect of the semiconductor integrated circuit device of the present invention, an input buffer that outputs an output signal in response to an input signal input from an external input terminal, and one conductive electrode is connected to a power supply. And the first N-channel MOS transistor, one conduction electrode is grounded, and the other conduction electrode is N
A first P-channel MO connected to the other conduction electrode of the channel MOS transistor and the input node of the input buffer.
A potential supply means for supplying a power supply potential or a ground potential to the gate electrodes of the S transistor, the N channel MOS transistor and the P channel MOS transistor, the output node of the input buffer, the first N channel MOS transistor and the first P channel. First switching means connected between the gate electrode of the MOS transistor and turned on when an input signal is applied to the external input terminal and turned off when the input signal is not applied to the external input terminal Is.

A semiconductor integrated circuit device according to a second aspect is the semiconductor integrated circuit device according to the first aspect, further comprising second switching means for connecting an external input terminal and an input node of the input buffer in response to an activation signal. It is provided.

A semiconductor integrated circuit device according to a third aspect is the semiconductor integrated circuit device according to the first or second aspect, in which a resistance element is provided in the potential supply means, the input buffer is provided, and one conduction electrode is connected to a power supply. P-channel MOS transistor, and one conduction electrode is grounded, and the other conduction electrode is the second
Connected to the other conduction electrode of the P channel MOS transistor and the output node, and the gate electrode of the second P channel M transistor.
A second N-channel MOS transistor connected to the gate electrode of the OS transistor is provided, and the resistance value of the resistance element is 1 of the ON resistance of the second N-channel MOS transistor.
It has a size of 0 times or more.

A semiconductor integrated circuit device according to a fourth aspect is the semiconductor integrated circuit device according to the first or second aspect, in which a resistance element is provided in the potential supply means, the input buffer is provided, and one conduction electrode is connected to a power supply. P-channel MOS transistor, and one conduction electrode is grounded, and the other conduction electrode is the second
Connected to the other conduction electrode of the P channel MOS transistor and the output node, and the gate electrode of the second P channel M transistor.
A second N-channel MOS transistor connected to the gate electrode of the OS transistor is provided, and the resistance value of the resistance element is 10 times or more the ON resistance of the second P-channel MOS transistor.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor integrated circuit device of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a circuit diagram of an input circuit 103 according to a first embodiment of a semiconductor integrated circuit device of the present invention.

Referring to FIG. 1, the input circuit 103 includes an input buffer 105, a pull-up resistor 107, and an NMOS.
It includes transistors 109 and 111 and a PMOS transistor 113. The input buffer 105 is the inverter 1
15, 117, and the inverter 115 includes PM
OS transistor 119 and NMOS transistor 121
The inverter 117 further includes a PMOS transistor 123 and an NMOS transistor 125.

In input buffer 105, inverter 115 and inverter 117 are connected in series at node D, and the connection node between the gate electrode of PMOS transistor 119 of inverter 119 and the gate electrode of NMOS transistor 121 is the input node of input buffer 105. A, and the PMOS transistor 123 of the inverter 117
A connection node between the drain electrode of the input buffer 105 and the drain electrode of the NMOS transistor 125 is the output node B of the input buffer 105.

Here, the input buffer 105 may be a NOR logic circuit or the like. NMOS transistor 109
The drain electrode of is the output node B of the input buffer 105.
Connected to the source electrode of the NMOS transistor 111
And the gate electrode of the PMOS transistor 113 is connected to the node C, and the gate electrode becomes H level when the input signal input from the external input terminal IN is L or H level, and when the external input terminal IN is in a floating state. An internal signal S1 of L level is applied to. The pull-up resistor 107 is further connected to the node C.

The drain electrode of the NMOS transistor 111 is connected to the power supply Vcc, the source electrode is connected to the source electrode of the PMOS transistor 113, and the drain electrode of the PMOS transistor 113 is grounded.

Next, the operation of the input circuit 103 will be described.
When an H level input signal is input to the external input terminal IN, the node D in the input buffer 105 becomes L level and the output node B becomes H level. Here, the NMOS transistor 109 to which the H-level internal signal S1 is applied is turned on, and the node C is at the H level by the pull-up resistor 107, so the NMOS transistor 111 is turned on and the power supply is turned on. A power supply voltage is supplied from Vcc to the input node A through the NMOS transistor 111, and the input node A is forcibly fixed to the H level inside the input circuit.

On the other hand, when an L level input signal is input to the external input terminal IN, a node D in the input buffer 105 is input.
Becomes H level, and the output node B becomes L level. here,
The NMOS transistor 109 to which the H-level internal signal S1 is applied is turned on, and the pull-up resistor 107
If the resistance value of is sufficiently larger than the ON resistance of the NMOS transistor 125 of the inverter 117 included in the input buffer 105 (for example, about 10 times or more),
Since the node C becomes sufficiently L level, the PMOS transistor 113 is turned on, and the input node A is forcibly fixed to L level inside the input circuit.

When the external input terminal IN is used in a floating state, the internal signal S1 becomes L level and N
The MOS transistor 109 is turned off, and the output node B and the node C are separated. The node C becomes H level by the pull-up resistor 107, and the NMOS transistor 1
11 is turned on, the PMOS transistor 113 is turned off, and the input node A is forcibly fixed to the H level inside the input circuit. Therefore, input node A can be stably maintained at H level.

As described above, in the input circuit 103 of the semiconductor integrated circuit device according to the first embodiment of the present invention, since the level of the input node is forcibly fixed inside the input circuit, the input signal is input for a fixed time. Input noise such as spike noise that occurs when the output signal changes after a change or when the selected device changes, the semiconductor integrated circuit does not malfunction, and even when the external input terminal is in the floating state, Since an H-level output can be held stably, even if a large number of input pins are used, by using this input circuit for an input circuit whose output level is always fixed at the H level, board mounting is easy and It is possible to provide an inexpensive semiconductor integrated circuit device.

(2) Second Embodiment FIG. 2 is a circuit diagram of an input circuit 200 according to a second embodiment of the semiconductor integrated circuit device of the present invention.

Referring to FIG. 2, the input circuit 200 is similar to that of FIG.
Instead of the pull-up resistor 107 of the input circuit 103 of
The pull-down resistor 207 is connected to the node C.

Next, the operation of the input circuit 203 will be described.
When an L level input signal is input to the external input terminal IN, the node D of the input buffer 105 becomes H level and the output node B becomes L level. Here, since the NMOS transistor 109 to which the H-level internal signal S1 is applied is on and the node C is at the L level due to the pull-down resistor 207, the PMOS transistor 113 is turned on and the node A Is forcibly fixed to the L level inside the input circuit.

On the other hand, when an H level input signal is input to the external input terminal IN, the node D of the input buffer 105 becomes L level and the output node B becomes H level. Where H
The NMOS transistor 109 to which the level internal signal S1 is applied is turned on, and the pull-down resistor 2
If the resistance value of 07 is made sufficiently large (for example, about 10 times or more) by the ON resistance of the PMOS transistor 123 of the inverter 117 included in the input buffer 105, the node C becomes sufficiently H level. , NM
The OS transistor 111 is turned on, and the input node A is forcibly fixed to the H level inside the input circuit.

When the external input terminal IN is used in a floating state, the internal signal S1 becomes L level and N
The MOS transistor 109 is turned off, and the output node B and the node C are separated. The node C becomes L level by the pull-down resistor 207, and the PMOS transistor 1
13 is turned on, the NMOS transistor 111 is turned off, and the input node A is forcibly fixed to the L level inside the input circuit. Therefore, input node A can be stably maintained at the L level.

As described above, in the input circuit 200 of the semiconductor integrated circuit device according to the second embodiment of the present invention, since the level of the input node is forcibly fixed inside the input circuit, the input signal is input for a fixed time. Input noise such as spike noise that occurs when the output signal changes after a change or when the selected device changes, the semiconductor integrated circuit does not malfunction, and even when the external input terminal is in the floating state, Since an L level output can be held, a semiconductor integrated circuit which is easy and inexpensive to mount on a board by using this input circuit for an input circuit whose output level is always L level even when it has a large number of input pins. It becomes possible to provide a device.

(3) Third Embodiment FIG. 3 is a circuit diagram of an input circuit 300 according to a third embodiment of the semiconductor integrated circuit device of the present invention.

Referring to FIG. 3, the input circuit 300 is similar to that of FIG.
Of the NMOS transistor 10 in the input circuit 103 of
9 and a PMOS transistor 327 connected in parallel,
Internal signal S1 is input from the input terminal and the output terminal is PMO
And an inverter 329 connected to the gate electrode of S-transistor 327.

An inverted signal of the internal signal S1 is applied to the gate electrode of the PMOS transistor 327, and the NMOS transistor 109 and the PMOS transistor 327 constitute a transfer gate 309 for switching between the output node B and the node C. .

Therefore, in addition to the effect of the input circuit 103 of the first embodiment, the input circuit 300 of the semiconductor integrated circuit device of the third embodiment of the present invention has the transfer gate 30.
9, the input circuit 300 can apply the potential of the output node B to the node C without lowering the threshold voltage of the NMOS transistor 109, as compared with the input circuit 103 of FIG.

Further, instead of the pull-up resistor 107,
The NMOS transistor 307 having the drain electrode and the gate electrode connected to the power supply Vcc has output nodes B and C.
And NMOS transistor 307 connected between
A material having a long channel length and a short channel width and a large resistance value is used as the material.

(4) Fourth Embodiment FIG. 4 is a circuit diagram of an input circuit 400 according to a fourth embodiment of the semiconductor integrated circuit device of the present invention.

Referring to FIG. 4, the input circuit 400 is similar to that of FIG.
In the input circuit 200 of FIG.
It further includes a PMOS transistor 327 connected in parallel to the OS transistor 109, and an inverter 329 connected to the gate electrode of the PMOS transistor 327 and applying an inverted signal of the internal signal S1.

Therefore, in addition to the effect of the input circuit 200 of the second embodiment, the input circuit 400 of the semiconductor integrated circuit device of the fourth embodiment of the present invention has the NMOS transistor 1
2 and the transfer gate 309 composed of the PMOS transistor 327 and the input circuit 20 of FIG.
Compared with 3, the input circuit 400 can apply the potential of the output node B to the node C without lowering the potential of the NMOS transistor 109 by the threshold voltage.

Further, instead of the pull-down resistor 207,
A PMOS transistor 407 whose drain electrode and gate electrode are grounded is connected between the output node B and the node C. The PMOS transistor 407 has a long channel length and a short channel width and a large resistance value. Used.

(5) Fifth Embodiment FIG. 5 is a circuit diagram of an input circuit 500 according to a fifth embodiment of the semiconductor integrated circuit device of the present invention.

Referring to FIG. 5, the input circuit 500 is similar to that of FIG.
In the input circuit 103 of the transfer gate 531
, Inverter 537, and NMOS transistor 539
And a PMOS transistor 541.

The transfer gate 531 is connected in series between the external input terminal IN and the input node A of the input buffer 105, and is connected to the PMOS transistor 533 and the PMO.
It includes an S transistor 533 and an NMOS transistor 535 connected in parallel.

A chip select signal CS for activating the semiconductor integrated circuit device is applied to the gate electrode of the NMOS transistor 535, and an inverter 537 is connected to the gate electrode of the PMOS transistor 533.
An inverted signal of the chip select signal CS inverted by 37 is applied. The drain electrode of the NMOS transistor 539 is connected to the source electrode of the NMOS transistor 125, and the source electrode of the NMOS transistor 539 is grounded. The source electrode of the PMOS transistor 541 is connected to the power supply Vcc, and the drain electrode thereof is connected to the output node B of the input buffer 105. NM
OS transistor 539 and PMOS transistor 5
The chip select signal CS is applied to the gate electrode of 41.

Next, the operation of the input circuit 500 will be described.
The chip select signal CS is at H level during normal operation (including in the floating state), and is at L level during standby, which is low power consumption.

During normal operation, the chip select signal CS is at H level.
Since it is the level, the PMOS transistor 533 and the NM
The OS transistor 535 is turned on, and an input signal is input from the external input terminal IN to the input node A of the input buffer 105 via the transfer gate 531. Also,
The NMOS transistor 539 turns on, the source electrode of the NMOS transistor 125 is grounded via the NMOS transistor 539, and the PMOS transistor 541 turns off. At this time, input circuit 500 becomes the same circuit as input circuit 103 of the first embodiment shown in FIG. 1 and performs the same operation.

When an L level input signal is input from the external input terminal IN, the potential of the output node B of the input buffer 105 becomes L level, as described in the first embodiment. When the input circuit 500 enters the standby state from this state, the internal signal S1 is at the H level, so that the output node B becomes the H level by the pull-up resistor 109.

On the other hand, in the standby state, the chip select signal CS becomes L level and the PMOS transistor 5
41 is turned on, the NMOS transistor 539 is turned off, and the source electrode of the NMOS transistor 125 is in a floating state. Since the PMOS transistor 123 is off, the power supply voltage is supplied to the output node B from the power supply Vcc via the PMOS transistor 541,
The output node B becomes H level. Therefore, when the input signal is at the L level during the normal operation immediately before entering the standby state, the output node B, which is at the L level, is set to the H level, and the output node B is output from the power supply Vcc via the pull-up resistor 107. It is possible to prevent current from flowing to B and reduce power consumption.

The pull-up resistor 107 of the input circuit 500
Is the same as in the case of the input circuit 300 of the third embodiment, the drain electrode and the gate electrode are connected to the power supply Vcc.
The MOS transistor 307 can be used instead.

Further, instead of the NMOS transistor 109 of the input circuit 500, the input circuit 300 of the third embodiment.
It is possible to use the transfer gate 309 and the inverter 329 of the input circuit 30 of the third embodiment.
The same effect as 0 can be obtained.

Further, the input circuit 2 of the second embodiment shown in FIG.
00 or the input circuit 400 of the fourth embodiment shown in FIG.
Pull-up resistor 107 of input circuit 500 of the fifth embodiment
Is replaced with a pull-down resistor 207 or a PMOS transistor 407 whose drain and gate electrodes are grounded,
The PMOS transistor 541 whose source electrode is connected to the power supply Vcc can be replaced with an NMOS transistor whose source electrode is grounded. In this case, the input signal was at the H level during the normal operation immediately before the standby state. The output node B which is at H level is
By setting the level, it is possible to prevent current from flowing from the output node B to the ground via the pull-down resistor 207 or the PMOS transistor 407, and it is possible to reduce power consumption.

Further, since the chip select signal CS is at the L level in the standby mode, the PMOS transistor 5
33 and the NMOS transistor 535 are both turned off,
A leak current flowing from the power supply Vcc to the external input terminal IN via the NMOS transistor 111, or from the external input terminal IN to the ground PMOS transistor 11
It is possible to cut off the leak current flowing through 3.

Particularly, when the external input terminal IN is in a floating state, the L-level internal signal S1 is input, and N
When the MOS transistor 109 is turned off, the node C becomes H level by the pull-up resistor 107, the NMOS transistor 111 is turned on, and the H level is applied to the input node A, the external input terminal IN is unexpectedly turned on. NMO from power supply Vcc generated when L level is input
A leak current flowing to the external input terminal IN via the S transistor 111 can be blocked.

As described above, the input circuit 500 of the fifth embodiment of the semiconductor integrated circuit device of the present invention has the effect of the input circuit 103 of the first embodiment of FIG. 1 and the potential supply means such as the power supply Vcc. It is possible to prevent a leak current from the external input terminal to the external input terminal or a leak current from the external input terminal to the potential supply means such as the ground.

(6) Sixth Embodiment FIG. 6 is a circuit diagram of an input circuit 600 according to a sixth embodiment of the semiconductor integrated circuit device of the present invention.

Referring to FIG. 6, the input circuit 600 is similar to that of FIG.
In the input circuit 103 of the first embodiment, the signal transmitted to the internal circuit (not shown) is output not from the output node B but from the node D which is a connection node between the output of the inverter 115 and the input of the inverter 117.

Since the output node B is connected to the pull-up resistor and the transistor, the load capacity also increases,
In addition, the potential slightly floats above the ground potential or falls below the power supply potential, so that the internal circuit operates faster when the signal output from the node D is used.

As described above, the input circuit 600 of the sixth embodiment of the semiconductor integrated circuit device of the present invention realizes higher speed operation of the internal circuit in addition to the effect of the input circuit 103 of the first embodiment. Is possible.

Similarly to the case of the input circuit 600 of FIG. 6, the input circuits of the second to fifth embodiments of FIGS. 2 to 5 output the signal transmitted from the node D to the internal circuit.
High speed operation of the internal circuit becomes possible.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a semiconductor integrated circuit device according to the present invention.
3 is a circuit diagram of the input circuit 103 of FIG.

FIG. 2 is a second embodiment of the semiconductor integrated circuit device of the present invention.
3 is a circuit diagram of the input circuit 200 of FIG.

FIG. 3 is a third embodiment of the semiconductor integrated circuit device of the present invention.
3 is a circuit diagram of the input circuit 300 of FIG.

FIG. 4 is a fourth embodiment of the semiconductor integrated circuit device of the present invention.
3 is a circuit diagram of the input circuit 400 of FIG.

FIG. 5 is a fifth embodiment of the semiconductor integrated circuit device of the present invention.
3 is a circuit diagram of an input circuit 500 of FIG.

FIG. 6 is a sixth embodiment of the semiconductor integrated circuit device of the present invention.
3 is a circuit diagram of an input circuit 600 of FIG.

FIG. 7 is a circuit diagram showing an example of an input circuit of a conventional semiconductor integrated circuit device.

FIG. 8 is a circuit diagram showing an example of an input circuit of a conventional semiconductor integrated circuit device.

FIG. 9 is a circuit diagram showing an example of an input circuit of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

103, 200, 300, 400, 500, 600 Input circuit, 109, 111, 307, 535, 539 N
MOS transistor, 111, 327, 407, 53
3,541 PMOS transistor, 107 resistor, 3
29,537 inverter, 309,531 transfer gate, S1 internal signal.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device activated in response to an activation signal applied from the outside, the input buffer outputting an output signal in response to an input signal input from an external input terminal, On the other hand, the first N-channel MO whose conducting electrode is connected to the power supply
An S transistor and a first P-channel MOS transistor having one conduction electrode grounded and the other conduction electrode connected to the other conduction electrode of the N-channel MOS transistor and an input node of the input buffer.
A transistor, a potential supplying means for supplying a power supply potential or a ground potential to the gate electrodes of the N-channel MOS transistor and the P-channel MOS transistor, an input node of the input buffer, the first N-channel MOS transistor and the first N-channel MOS transistor. 1 P-channel MO
First switching means connected between the gate electrode of the S transistor and turned on when the input signal is given to the external input terminal and turned off when the input signal is not given to the external input terminal; And a semiconductor integrated circuit device including. 2. A second connection for connecting the external input terminal and an input node of the input buffer in response to the activation signal.
The semiconductor integrated circuit device according to claim 1, further comprising: 3. The potential supply means includes a resistance element, and the input buffer has a second P-channel MO whose one conductive electrode is connected to a power source.
The S transistor and one conduction electrode are grounded, and the other conduction electrode is the second P electrode.
A second N-channel MOS transistor connected to the other conduction electrode of the channel MOS transistor and the output node, and having a gate electrode connected to the gate electrode of the second P-channel MOS transistor; 3. The semiconductor integrated circuit device according to claim 1, wherein the resistance value is 10 times or more as large as the on resistance of the second N-channel MOS transistor. 4. The potential supply means includes a resistance element, and the input buffer has a second P-channel MO whose one conductive electrode is connected to a power source.
The S transistor and one conduction electrode are grounded, and the other conduction electrode is the second P electrode.
A second N-channel MOS transistor connected to the other conduction electrode of the channel MOS transistor and the output node, and having a gate electrode connected to the gate electrode of the second P-channel MOS transistor; 3. The semiconductor integrated circuit device according to claim 1, wherein the resistance value is 10 times or more as large as the on resistance of the second P-channel MOS transistor.