WO2006067859A1

WO2006067859A1 - Interface circuit

Info

Publication number: WO2006067859A1
Application number: PCT/JP2004/019396
Authority: WO
Inventors: Tatsuya Ueno
Original assignee: Yamatake Corporation
Priority date: 2004-12-24
Filing date: 2004-12-24
Publication date: 2006-06-29

Abstract

An interface circuit comprises a first inverter circuit for outputting an input signal applied to an external input terminal while inverting its logical level, a second inverter circuit for outputting the output signal from the first inverter circuit while inverting its logical level at a potential higher or lower, by a predetermined level, than the logical level of the input signal applied to the first inverter circuit, and a feedback circuit performing positive feedback of the output signal from the second inverter circuit to the external input terminal. The interface circuit performs positive feedback of the output signal from the second inverter circuit and elevates or lowers the potential at the external input terminal under floating state to H level or L level.

Description

Specification

Interface circuit

Technical field

The present invention relates to an interface circuit that is applied to various electronic devices and stabilizes the electrical state of an external input / output terminal.

Background art

[0002] In general, a signal transmitted by a device in a digital system basically has two states except for a floating state. The first state is a state designed to transmit an event corresponding to a logic high level (also called logic high, high, 1, on, H level), and the second state is It is a state designed to transmit events corresponding to logic low levels (also called logic low, low, 0, off, L level).

[0003] The specific signal potential that determines which of these logic high and logic low signals is transmitted depends on the semiconductor element that forms the circuit associated with the transmission.

[0004] For example, C MOS logic ICs and transistor-transistor-logic (TTL) ICs are the most common circuit configurations used to generate digital signals. In the case of CMOS logic ICs, the logic low signal is generally in the range where the potential force applied to the low voltage terminal is up to about 0.6V. On the other hand, if the potential applied to the high voltage terminal is Vcc, the logic high signal is generally in the range of Vcc to Vcc – 0.6V. Since it is a well-known technical matter that the relationship between the signal potential and the logic level is determined depending on the device in this way, it will not be described in detail in the following description.

[0005] Various information processing apparatuses as digital systems are generally provided with a plurality of external input terminals (connectors) for signal input. A semiconductor integrated circuit such as a CPU incorporated in an information processing apparatus is also provided with a plurality of input terminals (pins) for signal input, and may further be provided with a control terminal for switching the operation mode of the CPU or the like. The external input terminal has a function as an interface that inputs an H level or L level logic signal given from an external device and gives it to an internal circuit such as a CPU or a memory. In addition, the above control terminal outputs the control information given to the internal circuit depending on, for example, whether or not the grounding force is high. A function to switch to the L or L level.

[0006] By the way, the external input terminal Z control terminal for this type of logic circuit has a high input impedance, so its potential changes due to the influence of external noise in the floating state. Therefore, in order to prevent the external input terminal from being affected by external noise even when the potential of the external input terminal is in a floating state, conventionally, as shown in FIGS. 13A and 13B, a pull-up resistor Rpu or a pull-down resistor Rpd is generally used. The external input terminal 1 is connected to the power supply voltage Vcc or grounded.

An input buffer 2 having an external input terminal 1 includes, for example, a p-channel MOS transistor (abbreviated as PMOS) 3 and an n-channel MOS transistor (abbreviated as NMOS) 4 as shown in FIGS. 13A and 13B. It is comprised by the inverter circuit which consists of. If a pull-up resistor Rpu or pull-down resistor Rpd is connected to the external input pin 1 while applying force, leakage current may flow to the external input pin 1 using these resistors Rpu and Rpd as current paths.

For example, as shown in FIG. 14, a latch circuit composed of an NMOS transistor 6 and a PMOS transistor 7 gate-controlled by an NMOS transistor 5 is connected to an input node of an input buffer composed of two-stage inverter circuits 2a and 2b. It is shown that the leakage current can be reduced by providing 8 (see, for example, Patent Document 1). This latch circuit 8 latches according to the output level of the input buffer (two-stage inverter circuits 2a and 2b) that operates according to this signal when an external input terminal 1 is given an H-level or L-level signal (potential). As a result, the external input terminal 1 is forcibly fixed to H level or L level. At the same time, when the external input terminal 1 is in the floating state (open state), the latch circuit 8 turns off the NMOS transistor 5 by the external signal S, while conducting the NMOS transistor 6 by the pull-up resistor R pu (hereinafter referred to as “transistor”). It turns on and turns off the PMOS transistor 7 (hereinafter referred to as “off”) to maintain the external input terminal 1 at the H level.

[0009] Alternatively, as a similar technology, there is a known bus hold circuit provided for the purpose of preventing abnormal phenomena such as leakage current, oscillation, and data error of a semiconductor element caused when an external input terminal is opened. (For example, Patent Document 2 and Non-Patent Document 1 reference). This bus hold circuit has a function of holding the previous logical level given to the external input terminal when the external input terminal is in a floating state. In addition, this type of bus hold circuit may be used in place of a bull-up resistor or a pull-down resistor in order to prevent the bus from becoming unstable.

[0010] Incidentally, in this type of bus hold circuit, when a signal having a potential higher than the operating voltage of the bus hold circuit is applied to the external input terminal of the bus hold circuit, current flowing from the external input terminal is blocked. An overvoltage protection circuit is incorporated (see, for example, Patent Document 3).

[0011] As a general-purpose logic IC that realizes the above-described bus hold circuit, the 74VCX series and the like are commercially available.

Patent Document 1: Japanese Patent Laid-Open No. 9-161486

Patent Document 2: US Pat. No. 5,432,462

Patent Document 3: US Patent No. 6150845

Non-Patent Document 1: “AN—Designed with 5006J Bus Hold Circuit”, Fairchild Semiconductor Company, Application Note, March 1999 First Edition (revised September 1999), p. 1-3 Disclosure of Invention

Problems to be solved by the invention

[0012] However, when the latch circuit 8 as shown in Patent Document 1 is provided in the interface circuit, the external signal depends on whether or not the external input terminal 1 is in a floating state (open state). The NMOS transistor 5 needs to be on / off controlled by S. Therefore, the interface circuit has a dedicated circuit for determining whether the external input terminal 1 is in a floating state (open state) or a dedicated circuit for generating the external signal S to control the operation of the latch circuit 8. A circuit is required.

[0013] In addition, a bus hold circuit applied to a multi-drop node has a problem of leakage current as described in Non-Patent Document 1. Furthermore, when the logic level of the external input terminal is changed, the above-described bus hold circuit has a problem that current consumption is large.

On the other hand, a bus hold circuit provided for the purpose of preventing the bus from becoming unstable may cause the input to become unstable when the power supply to the bus hold circuit rises. That Therefore, in order to stabilize the bus potential at the rise of the power supply, it is necessary to provide, for example, a pull-up resistor in addition to the noshold circuit.

[0015] The present invention has been made in view of such circumstances, and its purpose is to set the external input terminal in advance without using an external signal when the external input terminal is in a floating state (open state). It is possible to provide an interface circuit with a simple configuration that can be automatically stabilized to the H level or the L level and has noise resistance and no leakage current from an external input terminal.

Means for solving the problem

In order to achieve the above object, an interface circuit according to the present invention includes a high voltage terminal and a low voltage terminal forming a pair of power supply terminals, and an external input terminal, and the logic level of the external input terminal is set to H It is an interface circuit that stabilizes the voltage at the level (logic high signal) or the L level (logic low signal).

A first inverter circuit configured using a transistor and inverting and outputting a logic level of an input signal applied to the external input terminal;

The potential of the input signal, which is configured by using a transistor and is obtained by inverting the logical level of the output signal in the first inverter circuit and applied to the first inverter circuit via the external input terminal. A second inverter circuit that generates an output signal of higher or lower potential,

A feedback path for positively feeding back the output signal of the second inverter circuit to the external input terminal is provided.

That is, the interface circuit according to the present invention basically has a logic level having the above-described H level potential (logic high signal) or L level potential (logic low signal) applied to the external input terminal. A first inverter circuit for inverting, and a second inverter circuit for inverting the logic level of the output signal of the first inverter circuit, the logic level of the output signal of the second inverter circuit being 1 is configured to provide positive feedback to the input node (external input terminal) of the inverter circuit,

In particular, the potential of the input signal applied to the input node of the first inverter circuit and the potential of the output signal output from the output node of the second inverter circuit [Input signal potential] <[Output signal potential]

Or

[Input signal potential]> [Output signal potential]

The external input terminal is in a floating state by positively feeding back the output signal of the output node of the second inverter circuit to the first input node (external input terminal). The logic level of the external input terminal is automatically maintained at the H level potential (logic high signal) or maintained at the L level potential (logic low signal) due to the positive feedback action. It is a feature. Note that the input signal potential and the output signal potential need only be slightly different.

[0019] When the external input terminal is in a floating state, the interface circuit configured as described above has an output signal with a potential higher or lower than the potential applied to the input node of the first inverter circuit. Is output positively to the input node of the first inverter circuit. For this reason, the potential of the output signal in the second inverter circuit is gradually shifted to the H level potential or the L level potential by the positive feedback action, and becomes stable when the potential becomes the H level potential or the L level potential. .

As a result, in the interface circuit according to the present invention, even when the external input terminal is in a floating state (open state), the potential of the external input terminal is automatically stabilized to the H level potential or the L level potential. I will do it. In the interface circuit according to the present invention, when the potential of the external input terminal is automatically stabilized to the H level potential or the L level potential, the external input terminal potential is electrically fixed to the H level potential. In any case where the potential of the external input terminal is electrically fixed to the L level potential, according to this interface circuit, the first and second inverter circuits allow the external input terminal to Since the high-voltage terminal and the low-voltage terminal force are separated, leakage current does not occur as in the case of using a bull-up resistor or pull-down resistor.

[0021] When the potential of the external input terminal is automatically set to the H level potential, the second inverter circuit is preferably

(a) Connected between the high voltage terminal and the external input terminal to output the first inverter circuit. A first transistor that is turned off when the power signal is at the H level potential and turned on (conductive state) when the output signal force SL level potential of the first inverter circuit;

(b) Second and third transistors inserted in series between the low voltage terminal and the external input terminal, wherein at least one of the second and third transistors is an output of the first inverter circuit. It is turned off (non-conducting state) when the signal level is at a potential, and at least one of the second and third transistors is turned off when the output signal of the first inverter circuit is at an H level potential. When the potential of the input signal applied to the external input terminal is an H level potential, an output signal having a potential equal to or higher than the potential of the input signal is output, and when the input signal is other than an H level potential, The second and third transistors are configured to output an output signal having a potential higher than that of the input signal.

[0022] Incidentally, one of the second and third transistors is turned off when it is at the potential of the output signal power level of the first inverter circuit, and the output signal of the first inverter circuit is at the potential of H level. It may be turned off when Alternatively, one or both of the second and third transistors may be turned off regardless of whether the output signal of the first inverter circuit is an H level potential or a ZL level potential. These second and third transistors have a voltage shift function that raises the potential of the output signal of the second inverter circuit by a predetermined potential above the potential of the external input terminal in the floating state. become.

[0023] When the second inverter circuit is configured as described above, the first inverter circuit receives the input signal having an L-level potential supplied from the external input terminal with respect to the H level. Preferably, voltage shift means is provided that lowers the potential of the output signal of the first inverter circuit to such an extent that the first transistor in the second inverter circuit is not turned on. Since the first inverter circuit includes the voltage shift means described above, it is possible to increase the convergence speed to the H level potential by the positive feedback action described above.

[0024] When the potential of the external input terminal is automatically set to the L-level potential, preferably the second inverter circuit is

(c) Connected between the low voltage terminal and the external input terminal to output the first inverter circuit. A first transistor that is turned off when the potential force ^S L level potential of the force signal is turned on, and turned on when the potential is H level;

(d) Second and third transistors inserted in series between the high voltage terminal and the external input terminal, wherein at least one of the second and third transistors is the first inverter circuit. When the potential of the output signal of the first inverter circuit is off, and at least one of the second and third transistors is at the H level of the potential of the output signal of the first inverter circuit. When the potential is at the potential level of the input signal applied to the external input terminal, an output signal equal to or lower than the potential of the input signal is output. It can also be composed of second and third transistors that output an output signal having a potential lower than that of the input signal.

[0025] Incidentally, one of the second and third transistors is turned off when the output signal of the first inverter circuit is at an H level potential, and the other is the output signal power level of the first inverter circuit. It may be turned off when the potential is. Alternatively, one or both of the second and third transistors may be turned off regardless of whether the output signal of the first inverter circuit is an H level potential or a ZL level potential. These second and third transistors have a voltage shift function that lowers the potential of the output signal of the second inverter circuit by a predetermined potential from the potential of the external input terminal in the floating state.

[0026] Then, when the second inverter circuit is configured as described above, the first inverter circuit uses the first inverter for an input signal having an L level potential applied via the external input terminal. It is preferable to provide voltage shift means for making the potential of the output signal of the circuit higher than the potential of the L level so that the first transistor in the second inverter circuit is not turned on.

Furthermore, in the interface circuit configured as described above, specifically, the output node of the second inverter circuit configured to automatically set the potential of the external input terminal to the H level potential. In addition, it is preferable that the high voltage terminal force further comprises a current supply means for supplying a constant current toward the external input terminal. In addition, in the second inverter circuit configured to automatically set the potential of the external input terminal to the L level potential. In this case, it is preferable to provide a current supply means for supplying a constant current from the external input terminal to the low voltage terminal at the output node.

[0028] When the potential of the external input terminal is fixed to the L level potential or the H level potential, the current supply means described above reduces the MOS transistor OFF operation time, although the external input terminal force also leaks current. In addition to shortening, it exhibits the effect of increasing the convergence speed to the H level potential or L level potential by the positive feedback action described above.

[0029] Note that the current supplied to the output node of the second inverter circuit has a voltage drop in the MOS transistor that forms the voltage shift function of the second inverter circuit when the external input terminal is in a floating state. Since it only occurs, the leakage current can be kept much lower than the leakage current when pull-up or pull-down resistors are used.

[0030] Preferably, in the above-described interface circuit, it is desirable to further include, for example, a resistor as a current limiting element that is inserted in series in the feedback path and limits the current flowing through the feedback path.

[0031] In the above-described interface circuit, a current limiting element (for example, a resistor) provided in the feedback path limits the current flowing into the external input terminal via the feedback path. For this reason, the above-described interface circuit can transition the external input terminal, which is stable at the H level potential, to the L level potential with a low driving current.

[0032] Further, the interface circuit described above is an interface circuit connectable to a power source, and includes an external input terminal, a first inverter to which the potential of the external input terminal is input, and an output of the first inverter. When a second inverter to which a potential is input and a feedback path for returning the potential of the output of the second inverter to the input of the first inverter are assumed, and this feedback path is assumed to be in a state, The potential of the external input terminal is substantially lower than the potential of the high-potential power line, and the output potential of the second inverter is always substantially higher than the potential of the external input terminal. Configured as

[0033] Preferably, the above-described interface circuit is an interface circuit connectable to a power source, and includes an external input terminal, a first inverter to which a potential of the external input terminal is input, and a first inverter. A second inverter to which the output potential of the second inverter is input, and a feedback path for returning the potential of the output of the second inverter to the input of the first inverter. Assuming that there is no feedback path, the potential of the output of the second inverter is always substantially higher than the potential of the external input terminal in the range where the potential of the external input terminal is substantially higher than the potential of the low potential power line. It is desirable to take the state low.

Strictly speaking, the external input terminal in the interface circuit of the present invention outputs a preset H level or L level signal in the floating state, so to speak, it functions as an output terminal. I have it. However, for convenience of explanation, the term “external input terminal” will be used consistently.

The invention's effect

As described above, according to the present invention, the potential of the external input terminal in a floating state can be set to the H level potential or the L level potential, and the leakage current of the external input terminal can be sufficiently suppressed. In addition, since the noise resistance can be enhanced by keeping the impedance low with respect to the power supply voltage terminal or the ground terminal of the external input terminal, the interface circuit of the present invention can be used in various electronic devices and semiconductor integrated circuits. It has a great effect as an interface circuit for an external input terminal in a circuit or the like. Moreover, the interface circuit of the present invention has an advantage that it can be easily incorporated into a semiconductor integrated circuit because the circuit configuration itself is simple.

Brief Description of Drawings

FIG. 1 is a configuration diagram of an interface circuit according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing input / output characteristics when the second inverter circuit force in the interface circuit shown in FIG. 1 stops positive feedback to the first inverter circuit;

FIG. 3 is a configuration diagram of an interface circuit according to Embodiment 2 of the present invention.

FIG. 4 is a configuration diagram of an interface circuit according to Embodiment 3 of the present invention.

FIG. 5 is a diagram showing input / output characteristics when the second inverter circuit force in the interface circuit shown in FIG. 4 is stopped from positive feedback to the first inverter circuit;

FIG. 6 is a configuration diagram of an interface circuit according to Embodiment 4 of the present invention.

FIG. 7 is a configuration diagram of an interface circuit according to Embodiment 5 of the present invention.

[FIG. 8A] A diagram showing an example of using a PMOS transistor as a switch.

[Figure 8B] Connecting the gate and drain of a PMOS transistor to form a p-channel diode The figure which shows the usage example of MOS transistor,

[Fig. 8C] Diagram showing an example of using a MOS transistor with a p-channel resistor by connecting the gate and source of a PMOS transistor.

[FIG. 8D] A diagram showing an example of using an NMOS transistor as a switch.

[Figure 8E] NMOS transistor gate and drain connected to form an n-channel diode

The figure which shows the usage example of MOS transistor,

[FIG. 8F] A diagram showing an example of using a MOS transistor with an n-channel resistor by connecting the gate and source of an NMOS transistor,

FIG. 9 is a diagram showing a configuration example of an interface circuit for verifying the configuration example of the second inverter circuit;

FIG. 10 is a diagram showing a verification result of the second inverter circuit shown in FIG.

FIG. 11 is a diagram showing another configuration example of the interface circuit for verifying the configuration example of the second inverter circuit;

FIG. 12 is a diagram showing a verification result of the second inverter circuit shown in FIG.

FIG. 13A is a block diagram showing an example of processing of an external input terminal using a pull-up resistor Rpu.

FIG. 13B is a block diagram showing an example of processing of an external input terminal using a pull-down resistor Rpd.

FIG. 14 is a diagram showing a configuration example of a conventional interface circuit;

FIG. 15 is a configuration diagram of an interface circuit according to Example 8 of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an interface circuit according to an embodiment of the present invention will be described with reference to the drawings.

[0038] Here, a high voltage terminal and a low voltage terminal forming a pair of power supply terminals will be described as a power supply node supplying a positive power supply voltage Vcc and a ground node defined as a zero potential. A circuit in which the voltage terminal is grounded and the low voltage terminal supplies a negative (minus) potential may be used. Alternatively, a circuit that supplies a positive (plus) power supply voltage to the high voltage terminal and a negative (minus) potential to the low voltage terminal may be used. In short, it is sufficient that the potential V supplied to the high voltage terminal and the potential V supplied to the low voltage terminal satisfy the relationship V> V.

2 1 2

[0039] By the way, in this specification, the conductive state and non-conductive state of a transistor are These are referred to as on and off, respectively.

Example 1

FIG. 1 shows a configuration of the interface circuit according to the first embodiment. Here, a configuration example using a MOS transistor as a transistor is shown. Specifically, 10 is a first inverter circuit composed of a PMOS transistor 11 and an NMOS transistor 12, and 20 is a second inverter circuit composed of two PMOS transistors 21, 22 and an NMOS transistor 23. is there.

[0041] In the first inverter circuit 10, the drain electrodes of the PMOS transistor 11 and the NMOS transistor 12 are connected to each other. The first inverter circuit 10 is connected in series between a power supply node (high voltage terminal) and a ground node (low voltage terminal). Each gate electrode of the first inverter circuit 10 is commonly connected to the external input terminal 1 via the input node A. The interconnected drain electrodes are configured as output node B. When the first inverter circuit 10 receives a signal having a predetermined potential at the external input terminal 1, the PMOS transistor 11 and the NMOS transistor 12 are complementarily turned on and off. As a result, the first inverter circuit 10 outputs to the output node B an output signal having a potential obtained by inverting the logic level of the external input terminal 1 (input node A).

Specifically, in the first inverter circuit 10, the PMOS transistor 11 is turned off and the NMOS transistor 12 is turned on when the input signal applied from the external input terminal 1 to the input node A is at the H level potential. The output node B potential is set to L level. Conversely, when the potential of the signal applied from the external input terminal 1 to the input node A is at the potential level, the PMOS transistor 11 is turned on and the NMOS transistor 12 is turned off, so that the potential of the output node B is changed to the H level potential. To do.

On the other hand, the second inverter circuit 20 connects two PMOS transistors 21 and 22 and an NMOS transistor 23 connected in series between a power supply node and a ground node. The second inverter circuit 20 is connected to the output node B of the first inverter circuit 10 by connecting the gate electrodes of these transistors 21, 22, and 23 together as an input node. The second inverter circuit 20 uses the connection point between the drain electrode of the PMOS transistor 21 and the source electrode of the PMOS transistor 22 as an output node C. This output node C is the first mentioned above. Is connected to the input node A of the inverter circuit 10 to form a feedback path. Thus, the output of the second inverter circuit 20 is positively fed back to the first inverter circuit 10.

[0044] Incidentally, the PMOS transistors 21 and 22 and the NMOS transistor 23 constituting the second inverter circuit 20 basically receive the output signal of the first inverter circuit 10 at the input node (gate electrode) and are complementary. In this case, it functions as a level reversal function that obtains an output signal having a potential obtained by inverting the logic level of the output node B of the first inverter circuit 10 at the output node C. In particular, the PMOS transistor 22 and the NMOS transistor 23 are voltages that increase the potential of the node C by applying a signal of a predetermined potential generated between the source and drain electrodes to the output node C when the PMOS transistor 22 and the NMOS transistor 23 are not completely turned on. It plays a role as a shift function.

Specifically, when the potential of the external input terminal 1 is an H level potential, and the first inverter circuit 10 receiving the potential outputs an output signal having an L level potential, the PMOS transistor 21 , 22 are turned on, and the NMOS transistor 23 is turned off. At this time, the NMOS transistor 23 is off, so that no leakage current occurs through the NMOS transistor 23 at the external input terminal 1.

On the other hand, when the first inverter circuit 10 receiving the potential of the potential level of the external input terminal 1 outputs an H level potential output signal, the PMOS transistor 21, 22 is turned off, and the NMOS transistor 23 is turned on. At this time, since the PMOS transistor 21 is off, no leakage current flows through the PMOS transistor 21 at the external input terminal 1.

[0047] If the external input terminal 1 is grounded (L level) force is also in a floating state (open state), the potential of the nodes A and C is not regulated by the external input terminal 1. As a result, the potential of the node C is positively fed back to the input node A of the first inverter circuit 10, and the potential of the node C gradually increases. For this reason, the output potential of the first inverter circuit 10 gradually decreases as the potential of the node C increases. At this time, the PMOS transistors 21 and 22 are turned on as the potential of the input signal applied to the input node of the second inverter circuit 20 decreases. Further, when the NMOS transistor 23 is turned off, the potential of the output node C is forcibly fixed to the H level potential. The external input terminal 1 potential is Determine. In other words, when the external input terminal 1 is in a floating state (open state), the potential of the external input terminal 1 is automatically set to the H level potential.

That is, when the second inverter circuit 20 itself does not positively feed back the output of this circuit to the input node A of the first inverter circuit 10, it corresponds to the potential of the input signal supplied to the external input terminal 1. Thus, an output signal having a potential always higher than the potential applied to the node A is output. Specifically, the second inverter circuit 20 outputs an output signal having a potential as shown by the characteristic X in FIG. In other words, when the external input terminal 1 is grounded and is not fixed at the potential level potential that can be supplied to the node A, the potential of the node A is the potential of the output signal of the second inverter circuit 20. Is positively fed back to the input node A of the first inverter circuit 10 and is gradually increased by a signal having a higher potential than the potential of the external input terminal 1 fed back positively from the second inverter circuit 20. As a result, the potential at node A automatically converges to the H level potential and stabilizes. For this reason, the potential of node A is automatically set to the H level potential when the external input terminal 1 is in a floating state (open state).

[0049] According to the interface circuit configured as described above, when the potential of the external input terminal 1 is set to the H level potential or the L level potential, the input of the external input terminal 1 that causes no leakage current is generated. The state can be kept stable. In particular, when the external input terminal 1 is in the floating state (open state), the potential of the external input terminal 1 can be automatically set to the H level potential. It is not necessary. When the force is forcibly fixed to the potential of the potential level of the external input terminal 1, the PMOS transistor 21 is turned off as described above, so that no leakage current occurs through the external input terminal 1. Therefore, the interface circuit of the present invention can stabilize the potential of the external input terminal 1 to the H level potential or the L level potential when various electronic devices are connected to the external input terminal 1.

Example 2

By the way, the embodiment described above is configured to automatically set the potential of the external input terminal 1 to the H level potential when the external input terminal 1 is in a floating state (open state). Is. However, the interface circuit of the present invention, on the contrary, has an external input terminal 1 It is also possible to configure the interface circuit to automatically set the potential at the L level. FIG. 3 is a block diagram of the interface circuit showing the embodiment. The same parts as those of the interface circuit shown in FIG.

[0051] This interface circuit has a second inverter circuit 20 connected in series to a PMOS transistor 24 and two NMOS transistors 25 and 26 connected in series between a power supply node and a ground node. , 25, and 26 are connected to the output node B of the first inverter circuit 10 as an input node connected in common. The connection point between the source electrode of the NMOS transistor 25 and the drain electrode of the NMOS transistor 26 is defined as an output node C. The output node C is connected to the input node A of the first inverter circuit 10 described above. In this way, the output of the second inverter circuit 20 is configured to be positively fed back to the first inverter circuit 10.

[0052] Incidentally, the PMOS transistor 24 and the NMOS transistors 25 and 26 constituting the second inverter circuit 20 are basically complementary to each other by receiving the output signal of the first inverter circuit 10 at the input node (gate electrode). In addition, it functions as a level inversion function that obtains a signal having a potential obtained by inverting the logic level of the output node B of the first inverter circuit 10 at the output node C. In particular, the NMOS transistor 25 and the PMOS transistor 24 have a voltage shift function that lowers the potential of the node C by covering the output node C with a predetermined voltage drop generated between the source and drain electrodes when the transistor does not completely turn on. Play the role of

[0053] According to the interface circuit configured as described above, when the external input terminal 1 is in the floating state (open state), the potentials of the nodes A and C are not defined by the external input terminal 1, so that the node C Is gradually fed back to the input node A of the first inverter circuit 10 and gradually decreases. As the potential decreases, the output potential of the first inverter circuit 10 gradually increases. On the other hand, the PMOS transistor 24 includes a second inverter circuit 2

It turns off as the potential of the signal applied to the 0 input node rises. When NMOS transistors 25 and 26 are turned on, the potential at output node C is forcibly fixed at L level, and the potential at external input terminal 1 is stabilized at the L level. In other words, when the external input terminal 1 is in the floating state (open state), the potential of the external input terminal 1 is automatically set to the L level potential. Therefore, in the interface circuit configured in this way, like the interface circuit shown in FIG. 1 described above, when the potential of the external input terminal 1 is set to the H level potential or the L level potential, The state of the potential of external input terminal 1 that does not cause leakage current can be maintained stably. In particular, in this interface circuit, when the external input terminal 1 is in a floating state (open state), the potential of the external input terminal 1 can be automatically set to the L level potential. For this reason, the interface circuit of the present invention does not need to lower the potential of the external input terminal 1 by connecting the pull-down resistor Rpd as in the prior art. In addition, when the potential of the external input terminal 1 is forcibly fixed to the H level potential, the NMOS transistor 26 is turned off as described above, so that no leakage current through the external input terminal 1 occurs. Therefore, the interface circuit of the present invention is connected to the external input terminal 1 in various electronic devices, and has the great effect that the potential of the external input terminal 1 can be stabilized to the H level potential or the L level potential. Obtainable.

Example 3

By the way, the interface circuit according to the present invention has the potential of the output signal output from the first inverter circuit 10 when it is one of the potential level potential or the H level potential applied to the input node A. It is also useful to incorporate in the first inverter circuit 10 a MOS transistor having a diode connection that shifts the second inverter circuit 20 to such an extent that the second inverter circuit 20 does not turn on and off. Specifically, in the case of the interface circuit shown in FIG. 1, for example, a diode-connected PMOS transistor 13 is provided between the power supply node and the source electrode of the PMOS transistor 11 as shown in FIG. The potential of the output node B is lowered by the operation threshold voltage of the PMOS transistor 13 connected in series.

In the interface circuit configured as described above, when the external input terminal 1 is grounded, the PMOS transistor 11 is turned on and the NMOS transistor 12 is turned off. For this reason, the potential of the source electrode of the PMOS transistor 11 and the potential of the node B are substantially equal. At this time, the potential of the node B is higher than the resistance between the source and the drain of the NMOS transistor 12 and the resistance between the source and the drain of the PMOS transistor 13, and therefore is lower than the voltage Vcc of the power supply node by about the operating threshold voltage of the PMOS transistor 13. Become. P in the second inverter circuit 20 The potential difference between the gate and the source of the MOS transistor 21 The potential difference between the gate and the source of the PMOS transistor 13 in the first inverter circuit 10 is substantially equal. Therefore, the PMOS transistor 21 is turned off. As a result, the interface circuit can keep the potential of the external input terminal 1 at the L level without causing leakage current.

However, in the interface circuit of the present invention, a slight leakage current may actually occur due to variations in the operation threshold voltage and transistor size of the PMOS transistor 13 and the PMOS transistor 21. However, this does not impair the effects of the present invention.

On the other hand, when the external input terminal 1 is released from the above-mentioned ground state force and becomes in a floating state, the potential of the node A rises due to the positive feedback action from the second inverter circuit 20 described above. Then, the potential of the output signal of the first inverter circuit 10 decreases as the potential of the node A increases, and the potential of the external input terminal 1 is automatically set to the H level potential as described above.

When the PMOS transistor 11 is on, the PMOS transistor 13 forms an equivalent current mirror circuit with the PMOS transistor 21 of the second inverter circuit 20. As described above, the potential applied to the gate electrode of the PMOS transistor 21 (the potential of the node B). Due to the presence of the PMOS transistor 13, the operating threshold voltage of the PMOS transistor 21 is lower than the power supply voltage Vcc of the PMOS transistor 21. It is kept. Therefore, the external input terminal 1 enters a floating state and the potential of the external input terminal 1 rises. Then, the potential of the signal applied to the gate electrode of the PMOS transistor 21 decreases, and the time until the operation threshold voltage of the PMOS transistor 21 is exceeded is shortened. As a result, the PMOS transistor 21 is turned on quickly, so that the time required for the potential of the external input terminal 1 to transition to the potential of the floating state force H level can be extremely shortened.

[0060] In this case, if the output of the second inverter circuit 20 is not positively fed back to the input node A of the first inverter circuit 10, the potential of the output signal output from the second inverter circuit 20 (node C potential) changes with respect to the potential of the signal supplied to the external input terminal 1 as shown by the characteristic Y in FIG. 5, for example, and is always higher than the potential supplied to the node A. Therefore, when the potential applied to the node A is not fixed at the potential level or the H level, the output signal of the second inverter circuit 20 is positively fed back to the input node A of the first inverter circuit 10. Then, the potential of the output signal of the second inverter circuit 20 quickly becomes V-level potential.

Example 4

In the case of the interface circuit shown in FIG. 3, a second inverter circuit 20 is connected by connecting a diode-connected NMOS transistor 14 between the source electrode of the NMOS transistor 12 and the ground node as shown in FIG. In this case, the potential applied to the gate electrode of the NMOS transistor 26 (the potential of the node B) may be set to be approximately equal to the operating threshold voltage of the NMOS transistor 26 and higher than the ground potential of the NMOS transistor 26.

The interface circuit of the present invention uses such an NMOS transistor 14 to reduce the potential of the external input terminal 1 when the potential of the external input terminal 1 becomes a floating state. As a result, the time required for the potential applied to the gate electrode of the NMOS transistor 26 to rise and exceed the operating threshold voltage of the NMOS transistor 26 can be shortened. As a result, in the interface circuit of the present invention, since the NMOS transistor 26 is turned on quickly, the time required for the potential of the external input terminal 1 to transition to the potential of the floating state force L level can be greatly shortened. It becomes possible.

Example 5

By the way, the interface circuit of the present invention, when the interface circuit is used to set the potential of the external input terminal 1 to the H level potential or the L level potential as described above, External power supply It is also useful to supply a constant current. That is, in the above-described interface circuit shown in FIG. 1, when the external input terminal 1 is in a floating state, the power supply voltage Vcc is applied to the external input terminal 1 by the PMOS transistor 21 in the second inverter circuit 20, and the external input terminal 1 is externally connected. The potential at input terminal 1 rises. However, the PMOS transistor 21 has a sufficiently high resistance value at the time of turning off to suppress a leakage current when the external input terminal 1 is grounded. For this reason, when the external input terminal 1 enters the ground state force floating state, the external input terminal 1 is It may take a long time for the potential at the input terminal 1 to transition to the H level potential. However, the resistance value when the PMOS transistor 21 is turned off varies depending on the ambient temperature. Therefore, the time from when the PMOS transistor 21 is turned on until the potential of the external input terminal 1 transitions to the H level potential also has temperature dependence.

Therefore, the interface circuit of the present invention may further include a current mirror circuit 30 as a current source for supplying a constant current to the external input terminal 1 as shown in FIG. Thus, it is desirable for the interface circuit of the present invention to shorten the time required until the PMOS transistor 21 is turned on. Specifically, in the interface circuit of the present invention, a current discharge type current mirror circuit 30 driven by a constant current source 31 is constituted by two PMOS transistors 32 and 33. When the external input terminal 1 is in a floating state, the constant current source 31 supplies a constant current from the current mirror circuit 30 to the external input terminal 1.

In such an interface circuit including the current mirror circuit 30, a current flows from the current mirror circuit 30 to the external input terminal 1 when the external input terminal 1 is grounded. On the other hand, when the external input terminal 1 transitions to the floating state, the potential of the external input terminal 1 rises rapidly due to the current supplied from the current mirror circuit 30 in the interface circuit of the present invention. As a result, the time required for the interface circuit of the present invention to turn on the PMOS transistor 21 in the second inverter circuit 20 is shortened.

Therefore, the potential of the external input terminal 1 is quickly raised to the H level potential. The PMOS transistor 21 is turned on, and the impedance of the external input terminal 1 with respect to the ground node is supported by the impedance of the NMOS transistor 23. For this reason, almost no current flows from the current mirror circuit 30 to the external input terminal 1.

Incidentally, the impedance of the external input terminal 1 with respect to the power supply node is governed by the impedance of the PMOS transistor 21. Therefore, the current supplied from the current mirror circuit 30 to the external input terminal 1 can be made much smaller than the leakage current caused by the conventional pull-up resistor Rpu. Therefore, the operating current of the interface circuit shown in FIG. 7 is slightly higher than that of the interface circuit configured as shown in FIG. 1, but the potential of the external input terminal 1 in the floating state is quickly changed to the H level potential. But it can. For this reason, the interface circuit of the present invention has an effect that the operation speed of the interface circuit can be increased while reducing the leakage current.

Example 6

It should be noted that such a current mirror circuit can be similarly applied to an interface circuit that automatically sets the potential of the external input terminal 1 in a floating state to an L level potential. Although not specifically illustrated, the interface circuit shown in FIG. 3 described above may be configured as a current sink type current mirror circuit so that a constant current is sucked from the external input terminal 1. The above-described interface circuit has the same effect as the interface circuit shown in FIG. 7 because the time until the aforementioned NMOS transistor 26 is turned on is shortened.

Example 7

Incidentally, in each of the above-described embodiments, the interface circuit of the present invention is a second inverter circuit 20 as an example in which the potential of the external input terminal 1 in the floating state is automatically set to the H level potential. Is composed of two PMOS transistors 21 and 22 and an NMOS transistor 23. In addition, the interface circuit of the present invention has an example in which the potential of the external input terminal 1 in the floating state is automatically set to the L level potential, the second inverter circuit 20 is connected to the PMOS transistor 24 and the two NMOS transistors 25, It consisted of 26.

[0070] Basically, the second inverter circuit 20 may satisfy the following points.

[0071] (a) a main MOS transistor (level inversion function) that operates on and off according to the potential of the output signal output from the first inverter circuit 10 to invert the logic level;

(b) When the external input terminal is in a floating state, it is turned off by the current flowing through the main MOS transistor or by the potential of the output signal output from the first inverter circuit 10 to generate an output signal of a predetermined potential. Any auxiliary MOS transistor (voltage shift function) that shifts the potential of the output signal from the main MOS transistor may be used.

[0072] Specifically, in the case of an interface circuit that sets the potential of external input terminal 1 to an H level potential when external input terminal 1 is in a floating state, the second inverter circuit The path 20 includes at least one main MOS transistor that performs an on-Z operation according to the potential of the output signal output from the first inverter circuit 10, and a potential at which the potential of the output node C is applied to the external input terminal 1. It is sufficient to provide at least one auxiliary MOS transistor that is higher than

Conversely, in the case of an interface circuit that sets the potential of the external input terminal 1 to the L level potential when the external input terminal 1 is in a floating state, the second inverter circuit 20 is the first inverter When at least one main MOS transistor that operates on and off according to the potential of the output signal output from the circuit 10 and the external input terminal 1 are in a floating state, the potential of the output node C is set to the external input terminal 1 described above. It is sufficient to provide at least one auxiliary MOS transistor that lowers the potential of the applied signal.

Incidentally, the MOS transistor has a function of a switch diode resistance as shown in FIGS. 8A, 8B, 8C, 8D, 8E and 8F, respectively. That is, as shown in FIGS. 8A and 8D, the PMOS and NMOS having a three-terminal structure having a gate as an input terminal functions as a switch for turning on and off between the source and the drain in accordance with the potential of the input terminal. As shown in Fig. 8B and Fig. 8E, PMOS and NMOS with two-terminal structure with gate and drain connected are p-channel diode (PD) and n-channel diode (ND). Each functions. Furthermore, as shown in Fig. 8C and Fig. 8F, the PMOS and NMOS with a two-terminal structure in which the gate and source are connected function as a p-channel resistor (PR) and an n-channel resistor (NR), respectively. To do.

[0075] Then, as shown in FIGS. 8A and 8D, the resistance values and operating threshold voltages of the three-terminal PMOS and NMOS with the gate as the input terminal are defined by the channel width of these MOS transistors. Therefore, if the input / output characteristics without the positive feedback of the first and second inverter circuits 10 and 20 in the interface circuit have characteristics as shown in Fig. 2 or 5, respectively, Select a MOS transistor according to the requirements, so that at least one MOS transistor is turned on and off as described above, and at least one other MOS transistor has a level shift function that shifts the potential of the output signal. I should do it.

However, depending on the combination of MOS transistors shown in FIG. It is also true that it does not function as a circuit.

Therefore, the present inventor, as shown in FIG. 9, the first-stage MOS transistor on the power supply node side in the second inverter circuit 20 is the PMOS transistor 21, and is output from the first inverter circuit 10. When functioning as a main MOS transistor (first transistor) that operates on and off according to the potential of the output signal, the MOS transistor with what function is used as the second and third stage MOS transistors. It was verified whether it was possible. However, this verification is based on an external input in which the transistors of the first inverter circuit 10 and the second inverter circuit 20 are equal in size to the third stage MOS transistors and in the floating state. It is assumed that terminal 1 is at the H level potential.

FIG. 10 summarizes the verification results. In this figure, “◯” indicates that it functions effectively as the second inverter circuit 20 described above. “X” indicates that it does not function as the second inverter circuit 20. Furthermore, “△” indicates that the sizes of the first to third MOS transistors are all equal, and sometimes does not function as the second inverter circuit 20, but the first to third MOS transistors It is shown that it functions as the second inverter circuit 20 by adjusting the size of.

That is, the verification result shown in FIG. 10 shows that when the first-stage MOS transistor is composed of PMOS transistors that are turned on and off, at least one of the second-stage and third-stage MOS transistors has a P resistance. Or N resistor or 3-terminal NMOS transistor, and if at least one of the second-stage and third-stage MOS transistors is selected other than the 3-terminal NMOS transistor, it can be designed as the second inverter 20. And

Further, the inventor similarly applies the configuration of the second inverter circuit 20 in the case where the first inverter circuit 10 itself has a PMOS transistor 13 for shifting the potential of the output signal as shown in FIG. Verified. As a result, the verification results shown in FIG. 12 were obtained. However, this verification shows that the characteristics of the transistors constituting the first inverter circuit 10 and the second inverter circuit 20 are equal to each other in the characteristics of the third stage MOS transistors and are in a floating state. An external input terminal 1 is set to H level potential.

[0081] These verifications yielded the following results.

(A) Connected between the power supply node (high voltage terminal) and the external input terminal 1 to connect the first input The first transistor 21, which is turned off when the potential of the output signal of the barter circuit 10 is the H level potential, and turned on when the potential is the L level, the ground node (low voltage terminal), and the external input terminal 1 Second and third transistors 22,23 inserted in series between,

(b) At least one of the second and third transistors 22 and 23 is turned off when the potential of the output signal of the first inverter circuit 10 is at the potential level, and at least one of the first and second transistors 22 and 23 is turned off. The second inverter circuit 20 is constructed with the second and third transistors 22 and 23 whose operating conditions are set so that the output signal of the inverter circuit 10 is turned off when the potential of the output signal is at the H level. With that

(c) When the potential of the input signal applied to the external input terminal 1 is an H level potential, a potential equal to or higher than the potential of the input signal is output, and when the input signal potential is other than the H level potential, An output signal having a potential higher than the potential is output.

Note that the verification results shown in FIG. 10 and FIG. 12 show that the interface circuit shown in FIG. 9 and FIG. 11 pulls the external input terminal 1 in the floating state to the H level potential as described above. This is an example of a configuration.

Accordingly, the selection criteria for selecting the second and third MOS transistors in the interface circuit that maintains the external input terminal 1 at the L level potential are as follows.

[0085] (a) The polarities of the ground node and the power supply node are reversed.

(B) The ground node side in the second inverter circuit 20 is a first-stage MOS transistor.

(C) All MOS transistor channels are reversed in polarity.

Example 8

By the way, in the interface circuit of the present invention, when an H level potential signal is input to the external input terminal 1 or when the external input terminal 1 is in a floating state, the external input terminal 1 is at the H level potential. When the current drive capability is low, the external input terminal 1 potential may not transition to the H level potential force L level potential in a circuit with low current drive capability. This is because the second inverter circuit 20 uses the PMOS transistor 21 having a low on-resistance. That is, when the external input terminal 1 is at the H level potential, the PMOS transistor 21 constituting the second inverter circuit 20 is turned on. At this time, PM The OS transistor 21 supplies a power supply voltage Vcc for driving the PMOS transistor 21 to the external input terminal 1 through the low ON resistance of the PMOS transistor 21 itself. Therefore, the element connected to the external input terminal 1 needs to have a current driving ability to overcome the current flowing into the node C force external input terminal 1 and transition to the H level potential force L level potential.

Therefore, in the interface circuit of the present invention, it is preferable to insert a current limiting element R in series in the feedback path between the node C and the node A as shown in FIG. Incidentally, FIG. 15 is a block diagram of the interface circuit showing the embodiment 8. The same parts as those of the interface circuit shown in FIG.

The current limiting element R limits the current that also flows into the external input terminal 1 at the node C force when the potential of the external input terminal 1 is transitioned from the H level potential to the L level potential. Specifically, the current limiting element R may be a resistor, a p-channel resistor (PR) shown in FIG. 8C, and an n-channel resistor (NR) shown in FIG. 8F. It doesn't matter.

[0091] According to such an interface circuit in which the current limiting element R is inserted in series in the feedback path, the element that drives the external input terminal 1 changes the potential of the external input terminal 1 to the H level potential switch. In addition, when transitioning to an L level potential, the current limiting element R acts as a general pull-up resistor that not only limits the current flowing from the power supply. Therefore, the interface circuit of the present invention can reliably transition the potential of the external input terminal 1 from the H level potential to the L level potential even when an element having only a low current driving capability drives the external input terminal 1.

Incidentally, even if the current limiting element R is inserted in series in the feedback path, the interface circuit of the present invention does not require an external signal as in the other embodiments described above, and the potential of the external input terminal 1 is set. It can be automatically set to H level potential or L level potential, and the effect of preventing leakage current is maintained.

[0093] In particular, if the interface circuit of the present invention is applied to a bus hold circuit applied to a multi-drop bus, the problem of leakage current can be solved, and furthermore, the logic level of the external input terminal can be changed. Even if it is, less current consumption is required. In addition, the interface of the present invention In the face circuit, the potential of the external input terminal 1 is automatically set to the H level potential or the L level potential, so that the problem that the external input terminal 1 becomes unstable at the rise can be solved. Further, the interface circuit of the present invention does not require a pull-up resistor or a pull-down resistor, and can reduce the chip area of the semiconductor element.

[0094] Incidentally, a general bus hold circuit has an overvoltage protection circuit that blocks current flowing from the external input terminal when a signal having a potential higher than the differential voltage is applied to the external input terminal of the bus hold circuit. It has been incorporated. Of course, the interface circuit of the present invention should be provided with overvoltage input countermeasures like the bus hold circuit described in Patent Document 3 and the like.

Further, the current limiting element R in FIG. 15 of the eighth embodiment has an effect of limiting the current flowing from the external input terminal 1 to the node. The interface circuit of the present invention is extremely effective, for example, an anisotropic resistance element can be used as the current limiting element R to effectively prevent a current flowing from the external input terminal 1 to the node C. is there.

Incidentally, in the first to eighth embodiments described above, the interface circuit of the present invention has shown the configuration example using only the MOS transistor as the transistor. When manufacturing the integrated circuit (LSI) using only MOS transistors as transistors in the circuit by incorporating the interface circuit of the present invention, all the transistors in the interface circuit of the present invention are also composed of only MOS transistors. Then, there is an advantage that the manufacturing process for forming the transistor on the substrate is not complicated. However, the use of MES transistors instead of MOS transistors in the interface circuit of the present invention is not denied. In addition, any type of transistor used in an LSI can be applied to the embodiments of the present invention.

As described above, the interface circuit according to the present invention can set the potential of the external input terminal 1 to the H level potential or the L level potential when the external input terminal 1 is in the floating state. it can. However, the interface circuit according to the present invention does not require the pull-up resistor Rpu and the pull-down resistor Rpd as in the prior art. Further, the interface circuit according to the present invention determines the potential of the external input terminal 1 without determining whether or not the external input terminal 1 is in a floating state and giving a control signal as in the circuit shown in FIG. It can be set to the H level potential or L level potential (the power to make the H level L level to be selected beforehand).

Further, the interface circuit according to the present invention effectively prevents leakage current by a MOS transistor having high resistance when the potential of the external input terminal 1 is set to H level potential or L level potential. be able to. Therefore, the interface circuit according to the present invention is an interface circuit for an external input terminal in various electronic devices, semiconductor integrated circuits, etc., when the potential of the external input terminal 1 is determined using the pull-up resistor Rpu or the pull-down resistor Rpd. The practical advantages of are enormous. However, since the interface circuit according to the present invention has a simple circuit configuration, it can be easily applied to a semiconductor integrated circuit such as a CPU or a memory. Also, by forming the interface circuit of the present invention in an independent package and connecting it to the external input terminal Z control terminal of the existing digital circuit, the logic level of the external input terminal Z control terminal is set to the H level and the L level. ! /, Deviation force This can be set.

Note that the present invention is not limited to the above-described embodiment. In each embodiment, the second inverter circuit 20 is realized using three MOS transistors. However, the present invention may be realized with two or four or more MOS transistors. In addition, the present invention provides a MOS transistor having a two-terminal structure in which a gate and a source having a sufficiently high resistance value are connected to the second and third stages of a MOS transistor having a two-terminal structure by connecting a gate and a source, for example. You may replace it. Alternatively, the interface circuit of the present invention may be devised to increase the switching operation speed by configuring it with a plurality of MOS transistors in which the first-stage MOS transistors are connected in parallel. In addition, in the present invention, it is sufficient that a designer or the like designs a circuit so as to realize the above-described operation characteristics while appropriately adopting various circuit configurations for realizing the inverter circuit. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

Claims

The scope of the claims

[1] An interface circuit having a high voltage terminal and a low voltage terminal forming a pair of power supply terminals and an external input terminal, and stabilizing the logic level of the external input terminal to an H level potential or an L level potential. ,

An interface circuit comprising: a feedback path that positively feeds back an output signal of the second inverter circuit to the external input terminal.

[2] The second inverter circuit includes:

A first transistor connected between the high voltage terminal and the external input terminal and turned off when the output of the first inverter circuit is at H level, and turned on when at the L level;

Second and third transistors inserted in series between the low voltage terminal and the external input terminal, at least one of which is OFF when the output of the first inverter circuit is at L level. And at least one of them is turned off when the output of the first inverter circuit is at the H level, and when the potential of the input signal applied to the external input terminal is at the H level, the potential of the input signal Second and third transistors that output the above potential and output a potential higher than the potential of the input signal when the potential of the input signal is other than an H level potential;

The interface circuit according to claim 1, wherein

[3] In the interface circuit according to claim 2,

Further, the first inverter circuit sets the potential of the output signal to the L level input signal applied via the external input terminal, so that the first inverter circuit in the second inverter circuit has a potential higher than the H level. It has voltage shift means to make it low enough not to turn on the transistor An interface circuit characterized by that.

[4] The second inverter circuit includes:

A first transistor connected between the low-voltage terminal and the external input terminal and turned off when the output power level of the first inverter circuit is on, and turned on when the output level is H level;

Second and third transistors inserted in series between the high voltage terminal and the external input terminal, at least one of which is off when the output of the first inverter circuit is at L level. And at least one of them is turned off when the output of the first inverter circuit is at H level, and at the potential level of the input signal applied to the external input terminal, the potential of the input signal Second and third transistors that output an output signal having a potential lower than that of the input signal and output an output signal having a potential lower than the potential of the input signal when the potential is not at the potential level of the input signal.

The interface circuit according to claim 1, wherein the interface circuit is also powerful.

[5] The interface circuit according to claim 4,

Furthermore, the first inverter circuit sets the potential of the output signal to the H-level input signal applied via the external input terminal in the second inverter circuit rather than the L level. An interface circuit comprising voltage shift means for increasing the first transistor so that it does not turn on.

[6] The interface circuit according to any one of claims 1 to 5,

The interface circuit further comprises current supply means for supplying a constant current from the high voltage terminal to the external input terminal or to the external input terminal force to the low voltage terminal.

[7] The interface circuit according to any one of claims 1 to 6,

An interface circuit comprising a current limiting element that is inserted in series in the feedback path and limits a current flowing through the feedback path.

[8] An interface circuit connectable to a power source,

An external input terminal,

A first inverter to which the potential of the external input terminal is input; A second inverter to which the potential of the output of the first inverter is input;

A feedback path for feeding back the output potential of the second inverter to the input of the first inverter;

Assuming that this feedback path is not present, the output potential of the second inverter is always higher than the potential of the external input terminal in a range where the potential of the external input terminal is substantially lower than the potential of the high potential power line. Interface circuit that takes a substantially high state.

An interface circuit connectable to a power supply,

An external input terminal,

A first inverter to which the potential of the external input terminal is input;

A second inverter to which the potential of the output of the first inverter is input;

Assuming that this feedback path is not present, the output potential of the second inverter is always higher than the potential of the external input terminal in the range where the potential of the external input terminal is substantially higher than the potential of the low potential power line. Interface circuit that takes a substantially low state.