TW201830863A - Power-on control circuit and input/output control circuit - Google Patents

Abstract

A power-on control circuit for generating a first control signal to control an output-stage circuit. The power-on control circuit comprises first and second power terminal, an inverter chain circuit, a switch circuit, and a capacitor. The switch circuit has a control terminal receiving the first control signal, an input terminal coupled to the second power terminal, and an output terminal coupled to a first node. The inverter chain circuit is coupled to the first power terminal and has an input terminal coupled to the first node. The inverter chain circuit is coupled for generating the first control signal. The capacitor is coupled between the first node and a ground terminal. When the first power terminal receives a first voltage and the second power terminal does not receive a second voltage, the switch circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switch circuit is turned off according to the first control signal.

Description

 Power start control circuit and input/output control circuit  

The present invention relates to a power start control circuit, and more particularly to a power start control circuit having a lower leakage current.

In some integrated circuits, the output circuit may be powered by two different voltages simultaneously. For example, an output stage circuit coupled to an input/output pad is powered by a voltage of 3.3V, and a control circuit for controlling the initial stage circuit of the output stage is powered by a voltage of 1.8V. When a voltage of 3.3V has been supplied and a voltage of 1.8V has not been supplied, the input of the output stage circuit is in a floating state due to the inoperative operation of the control circuit, which results in a leakage current in the output stage circuit. In order to solve the leakage current of the output stage circuit, the power start circuit is used to cut off the path of the leakage current. However, in the case where a general power supply starting circuit has been supplied with voltages of 3.3V and 1.8V, leakage current is also generated, resulting in unnecessary power consumption.

The invention provides a power start control circuit for generating a first control signal to control an output stage circuit. The power start control circuit includes a first power terminal, a second power terminal, a switching circuit, an inverter chain circuit, and a capacitor. The first power terminal is configured to receive the first voltage. The second power terminal is configured to receive the second voltage. The switch circuit has a control end that receives the first control signal, an input that is coupled to the second power supply end, and an output that is coupled to the first node. The inverter chain circuit is coupled to the first power terminal and has an input coupled to the first node for generating a first control signal. The capacitor is coupled between the first node and the ground. When the first power terminal receives the first voltage and the second power terminal has not received the second voltage, the switching circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switching circuit is turned off according to the first control signal.

The invention further provides an input/output control circuit coupled to the input/outlet pad. The input/output control circuit includes a first power terminal, a second power terminal, an output stage circuit, and a power start control circuit. The first power terminal is configured to receive the first voltage. The second power terminal is configured to receive the second voltage. The output stage circuit is coupled to the input/outlet pad and the first power terminal, and is controlled by the first control signal. The power start control circuit is coupled to the output stage circuit for generating the first control signal. The power start control circuit includes a switch circuit, an inverter chain circuit, and a capacitor. The switch circuit has a control end that receives the first control signal, an input that is coupled to the second power supply end, and an output that is coupled to the first node. The inverter chain circuit is coupled to the first power terminal and has an input coupled to the first node for generating a first control signal. The capacitor is coupled between the first node and the ground. When the first power terminal receives the first voltage and the second power terminal has not received the second voltage, the switch circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switch circuit is turned off according to the first control signal.

1‧‧‧Input/Output Control Circuit

10‧‧‧Power start control circuit

11‧‧‧Output stage circuit

12‧‧‧ gate control circuit

13, 14‧‧‧ power terminal

20...22‧‧‧reverse circuit

23‧‧‧ NMOS transistor

24‧‧‧ buffer circuit

25‧‧‧ PMOS transistor

30, 40‧‧‧ transmission gate

100‧‧‧Switch circuit

101‧‧‧Resistors

102‧‧‧ capacitor

103‧‧‧Inverter chain circuit

104‧‧‧Return circuit

110, 112‧‧‧ PMOS transistor

111, 113‧‧‧ NMOS transistor

200, 210, 220‧‧‧ PMOS transistors

201, 211, 221‧‧‧ NMOS transistors

240, 242‧‧‧ NMOS transistor

241, 243‧‧‧ PMOS transistor

300, 400‧‧‧ PMOS transistor

301, 401‧‧‧ NMOS transistor

GND‧‧‧ ground terminal

N10...N13, N20...N23‧‧‧ nodes

PAD‧‧‧Input/Output

POC0...POC3‧‧‧ control signal

Figure 1 shows an input/output control circuit in accordance with an embodiment of the present invention.

Fig. 2A shows an input/output control circuit in accordance with another embodiment of the present invention.

Fig. 2B is a view showing the operation of the input/output control circuit of Fig. 2A in the power-on control phase.

Fig. 2C is a view showing the operation of the input/output control circuit of Fig. 2A in the stabilization phase.

Figure 3 shows an input/output control circuit in accordance with another embodiment of the present invention.

Fig. 4 shows an input/output control circuit according to still another embodiment of the present invention.

Figure 5 shows an input/output control circuit in accordance with an embodiment of the present invention.

Figure 6 shows an input/output control circuit in accordance with another embodiment of the present invention.

Figure 7 shows an input/output control circuit in accordance with still another embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Fig. 1 is a diagram showing an input/output control circuit according to an embodiment of the present invention. Referring to FIG. 1, the input/output control circuit 1 is part of an output circuit of an integrated circuit and is coupled to an input/output pad PAD of the integrated circuit. The input/output control circuit 1 includes a power start control circuit 10, an output stage circuit 11, and a gate control circuit 12. The power start control circuit 10 includes a switch circuit 100, a resistor 101, a capacitor 102, an inverter chain circuit 103, and a feedback circuit 104. The output stage circuit 11 includes p-type metal-oxide-semiconductor (PMOS) transistors 110 and 112 and N-type metal-oxide-semiconductor (NMOS) transistors 111 and 113. . The control terminal of the switch circuit 100 receives a control signal POC2, the input end of which is coupled to the power supply terminal 13, and the output end of which is coupled to the node N10. The on/off state of the switch circuit 100 is controlled by the control signal POC2. The resistor 101 is coupled between the nodes N10 and N11. The capacitor 102 is coupled between the node N11 and the ground GND. The inverter chain circuit 103 is coupled to the power terminal 14 and the ground GND, and has a plurality of inverters connected in series. The input end of the inverter chain circuit 103 is coupled to the node N10, and generates mutually inverted control signals POC2 and POC3 according to the voltage on the node N10. The feedback circuit 104 is coupled between the inverter chain circuit 103 and the node N11, and can change the voltage level of the control signal POC0 on the node N11 according to the control signal POC2.

The gate of the PMOS transistor 110 receives the control signal POC2, the source of which is coupled to the voltage terminal 14, and the drain of which is coupled to the node N12. The gate of the NMOS transistor 111 receives the control signal POC3, the drain of which is coupled to the node N13, and the source of which is coupled to the ground GND. The gate of the PMOS transistor 112 is coupled to the node N12, the source of which is coupled to the voltage terminal 14, and the drain of which is coupled to the input/output pad PAD. The gate of the NMOS transistor 113 is coupled to the node N13, the drain of which is coupled to the input/output pad PAD, and the source of which is coupled to the ground GND. The gate control circuit 12 is coupled to the power terminal 13 and the power terminal 14. The gate control circuit 12 is also coupled to nodes N12 and N13, which can respectively provide a gate control signal to the gate of the PMOS transistor 112 and the gate of the NMOS transistor 114.

Power terminals 13 and 14 are used to receive different voltages. For example, power terminal 13 is used to receive a voltage of 1.8 volts (V) and power terminal 14 is used to receive a voltage of 3.3V. In some cases, power supply terminal 14 has received a 3.3V voltage, but power supply terminal 13 has not received a 1.8V voltage. For example, the 1.8V voltage is generated by a voltage converter that steps down the 3.3V voltage. Therefore, the power supply terminal 13 receives a voltage than the power supply terminal 14. In the embodiment of the present invention, when the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 has not received the 1.8V voltage (ie, the power supply terminal 13 has 0V), the input/output control circuit 1 operates in a power supply start control phase. At the instant when the input/output control circuit 1 enters the power-on startup control phase, the voltage level of the control signal POC0 on the node N11 is 0V, and the inverter chain circuit 103 generates 0V according to the control signal POC0 (0V) on the node N11. Voltage level control signal POC2 and control signal POC3 with 3.3V voltage level. Therefore, it can be seen that the control signal POC2 has a low voltage level, and the control signal POC3 has a high voltage level, that is, the voltage levels of the control signals POC2 and POC3 are opposite each other. At this time, the switch circuit 100 is turned on in accordance with the control signal POC2 having a voltage level of 0V. The PMOS transistor 110 and the NMOS transistor 11N1 are turned on in accordance with the control signals POC2 and POC3, respectively. Therefore, the nodes N12 and N13 have a voltage of 3.3 V and a voltage of 0 V, respectively, to turn off the PMOS transistor 112 and the NMOS transistor 113, respectively. In addition, since the power supply terminal 13 has not received the 1.8V voltage so that the gate control circuit 12 does not operate, the on/off states of the PMOS transistor 112 and the NMOS transistor 113 are not controlled by the gate control circuit 12. In this way, in the power-on control phase, since both the PMOS transistor 112 and the NMOS transistor 113 are turned off, the leakage current path between the power terminal 14 and the ground GND in the output stage circuit 11 is cut off, thereby avoiding driving leakage. The generation of current. Further, in the power-on control phase, the feedback circuit 104 does not change the voltage level on the node N11 in accordance with the control signal POC2.

When the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 also receives the 1.8V voltage, the input/output control circuit 1 operates in a stable phase. At the instant when the input/output control circuit 1 enters the steady phase from the power-on control phase, the control signal POC2 is still 0V, and the switch circuit 100 is turned on according to the control signal POC2. At this time, the voltage level of the control signal POC0 on the node N11 becomes 1.8V, and the inverter chain circuit 103 generates the control signal POC2 having a voltage level of 3.3V according to the control signal POC0 (1.8V) on the node N11 and The voltage level is 1.8V control signal POC3. Therefore, it can be seen that the control signal POC2 has a high voltage level and the control signal POC3 has a low voltage level. At this time, the control signal POC2 having a voltage level of 3.3V turns off the switching circuit 100, and the feedback circuit 104 provides a feedback path to change the voltage level of the control signal POC0 on the node N11 according to the control signal POC2 to make it control. The voltage level of signal POC2, which is 3.3V. Since the voltage level of the control signal POC0 is changed from 1.8V to 3.3V, the input terminal of the inverter chain circuit 103 is also at 3.3V, thereby intercepting the inverter chain circuit 103 between the power supply terminal 14 and the ground terminal GND. Leakage current path. Further, in the stabilization phase, the PMOS transistor 110 and the NMOS transistor 111 are turned off according to the control signals POC2 and POC3, respectively. At this time, since the gate controller 12 is powered by 1.8V through the power supply terminal 13 and is powered by 3.3V through the power supply terminal 14, the PMOS transistor 112 and the NMOS transistor 113 are turned on/off by the gate control circuit 12. control.

According to the above, in the power-on startup control phase and the stabilization phase, the leakage current is prevented from being generated by intercepting the leakage current path, thereby reducing unnecessary power consumption. The operation of the input/output control circuit 1 of the present invention will be described in detail below through various embodiments.

Fig. 2A shows an input/output control circuit in accordance with another embodiment of the present invention. Referring to FIG. 2A, the switching circuit 100 includes a PMOS transistor 25. The gate of the PMOS transistor 24 is coupled to the control terminal of the switch circuit 100 to receive the control signal POC2, the drain of which is coupled to the input end of the switch circuit 100 (ie, coupled to the power supply terminal 13), and the source thereof is coupled to the switch circuit 100. The output (ie, coupled to node N10). The well region of the PMOS transistor 24 is coupled to the power terminal 14. The inverter chain circuit 103 includes reverse circuits 20 to 22 and an NMOS transistor 23. The reverse circuit 20 includes a PMOS transistor 200 and an NMOS transistor 201. The reverse circuit 21 includes a PMOS transistor 210 and an NMOS transistor 211. The reverse circuit 22 includes a PMOS transistor 220 and an NMOS transistor 221. The gate of the PMOS transistor 200 is coupled to the input end of the inverter chain circuit 103 (ie, the coupling node N11), the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N20. The gate of the NMOS transistor 201 is coupled to the input end of the inverter chain circuit 103 (ie, coupled to the node N11), the drain of which is coupled to the node N20, and the source of which is coupled to the ground GND. According to the architecture of the reverse circuit 20, the node N11 can serve as the input of the inverting circuit 20, and the node 20 can serve as the output of the inverting circuit 20. The gate of the NMOS transistor 23 is coupled to the node N20, and the drain is coupled to the power terminal 14 and the source thereof is coupled to the ground GND. The gate of the PMOS transistor 210 is coupled to the node N20, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N21. The gate of the NMOS transistor 211 is coupled to the node N20, the drain of the node is coupled to the node N21, and the source thereof is coupled to the ground GND. According to the architecture of the inverting circuit 21, the node N20 can serve as the input of the inverting circuit 21, and the node 21 can serve as the output of the inverting circuit 21. The gate of the PMOS transistor 220 is coupled to the node N21, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N22. The gate of the NMOS transistor 221 is coupled to the node N21, the drain of the node is coupled to the node N22, and the source thereof is coupled to the ground GND. According to the architecture of the reverse circuit 22, the node N21 can serve as the input of the inverting circuit 22 and the node 22 can serve as the output of the inverting circuit 22. The inverter chain circuit 103 generates a control signal POC1 at the node N20, a control signal POC2 at the node N21, and a control signal POC3 at the node N22. The NMOS transistor 23 is used to provide an electrostatic discharge path when an electrostatic discharge event occurs.

In the 2A diagram, the feedback circuit 104 includes a buffer circuit 24. The input end of the buffer circuit 24 is coupled to the node N21, and the output end thereof is coupled to the node N11. The buffer circuit 24 receives the control signal POC2 through the node N21 to buffer it to the node N11, thereby controlling the voltage level of the control signal POC0. The buffer circuit 24 includes NMOS transistors 240 and 242 and PMOS transistors 241 and 243. The gate of the PMOS transistor 241 is coupled to the input end of the buffer circuit 24, the source of which is coupled to the power supply terminal 14, and the other end of which is coupled to the node N23. The gate of the NMOS transistor 240 is coupled to the input end of the buffer circuit 24, the drain of which is coupled to the node N23, and the source of which is coupled to the ground GND. The gate of the PMOS transistor 243 is coupled to the node N23, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the output of the buffer circuit 24. The gate of the NMOS transistor 242 is coupled to the node N23, the drain of which is coupled to the output of the buffer circuit 23, and the source of which is coupled to the ground GND. NMOS transistors 240 and 242 and PMOS transistors 241 and 243 operate in conjunction to buffer the voltage or signal on node N23. The detailed operation of the input/output control circuit in the embodiment of Fig. 2A will be described below.

Referring to Fig. 2B, when the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 has not received the 1.8V voltage (i.e., the power supply terminal 13 has 0V), the input/output control circuit 1 operates in the power supply start control phase. At the instant when the input/output control circuit 1 enters the power-on control phase, the voltage level of the control signal POC0 on the node N11 is 0V. Through the reverse operation performed by the inverting circuits 20 to 22, the inverting circuit 20 generates a control signal POC1 having a voltage level of 3.3 V at the node N20, and the inverting circuit 21 generates a control signal having a voltage level of 0 V at the node N21. POC2, and the inverting circuit 22 generates a control signal POC3 having a voltage level of 3.3V on the node N22. At this time, the PMOS transistor 25 is turned on in accordance with the control signal POC2 having a voltage level of 0 V, so that the voltage level of the control signal POC0 on the node N11 is maintained at 0V. The PMOS transistor 110 and the NMOS transistor 111 are turned on in accordance with the control signals POC2 and POC3, respectively. At this time, the nodes N12 and N13 have a voltage of 3.3 V and a voltage of 0 V, respectively, to turn off the PMOS transistor 112 and the NMOS transistor 113, respectively. In addition, since the power supply terminal 13 has not received the 1.8V voltage so that the gate control circuit 12 does not operate, the on/off states of the PMOS transistor 112 and the NMOS transistor 113 are not affected by the gate control circuit 12 in the power supply start control phase. control. In this way, in the power-on control phase, since both the PMOS transistor 112 and the NMOS transistor 113 are turned off, the leakage current path between the power terminal 14 and the ground GND in the output stage circuit 11 is cut off, thereby avoiding driving leakage. The generation of current.

Further, referring to FIG. 2B, in the power-on control phase, the buffer circuit 24 of the feedback circuit 104 receives the control signal POC2 of the 0V voltage level. Through the buffering operation of the buffer circuit 24, the output terminal of the buffer circuit 24 is also maintained at a voltage level of 0V. Therefore, it can be seen that the control signal POC0 on the node N11 is still maintained at 0V. In other words, the feedback circuit 104 does not change the voltage level on the node N11.

Referring to Fig. 2C, when the power supply terminal 14 receives a voltage of 3.3 V and the power supply terminal 13 also receives a voltage of 1.8 V, the input/output control circuit 1 operates in a stable phase. At the instant when the input/output control circuit 1 enters the stabilization phase from the power-on control phase, the control signal POC2 is still 0V, and the PMOS transistor 25 is continuously turned on according to the control signal POC2 having the 0V voltage level. At this time, the voltage level of the control signal POC0 on the node N11 becomes 1.8V. Through the reverse operation performed by the inverting circuits 20-22, the inverting circuit 20 generates a control signal POC1 having a voltage level of 0 V at the node N20, and the inverting circuit 21 generates a control signal having a voltage level of 3.3 V at the node N21. POC2, and the inverting circuit 22 generates a control signal POC3 having a voltage level of 0V on the node N22. Therefore, it can be seen that at the moment when the input/output control circuit 1 enters the stabilization phase from the power-on startup control phase, since the voltage of the gate of the PMOS transistor 200 is 1.8 V and the voltage of its source is 3.3 V, the PMOS transistor 200 It cannot be completely turned off, resulting in a leakage current path being formed between the power supply terminal 14 and the ground GND and through the transistors 200 and 201. The PMOS transistor 25 is turned off in accordance with the control signal POC2 having a voltage level of 3.3V. In the embodiment of the present invention, the leakage current path can be cut off by the operation of the feedback circuit 104, and the description is as follows. Referring to Fig. 4C, the buffer circuit 24 of the feedback circuit 104 receives the control signal POC2 of the 3.3V voltage level. Through the buffering operation of the buffer circuit 24, the voltage level of the node N11 is increased from 1.8V to 3.3V. In other words, in the stabilization phase, the feedback circuit 104 provides a feedback path at this time to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V. Since the voltages of the gate and the source of the PMOS transistor 200 are both 3.3V, the PMOS transistor 200 is turned off, thereby cutting off the leakage current path between the power terminal 14 and the ground GND and passing through the transistors 200 and 201. .

Further, referring to FIG. 2C, in the stabilization phase, the PMOS transistor 110 and the NMOS transistor 111 are turned off according to the control signals POC2 and POC3, respectively. Since the gate controller 12 is powered by 1.8V through the power supply terminal 13 and is powered by 3.3V through the power supply terminal 14 during the stabilization phase, the PMOS transistor 112 and the NMOS transistor 113 are turned on/off by the gate control circuit. 12 to control.

According to the above, by the operation of the power-on control circuit 10, not only the leakage current path in the output stage circuit 11 during the power-start phase but also the leakage current path in the inverter chain circuit 103 can be cut off in the stabilization phase. Thereby reducing unnecessary power consumption.

In the embodiment of the 2A-2C diagram, the feedback circuit 104 includes only the buffer circuit 24. In other embodiments, the feedback circuit 104 can also include a transmission gate that is at least controlled by the control signal POC2. In an embodiment, referring to FIG. 3, the feedback circuit 104 further includes a transfer gate 30 coupled between the output of the buffer circuit 24 and the node N11. The transfer gate 30 includes a PMOS transistor 300 and an NMOS transistor 301. The gate of the PMOS transistor 300 receives the control signal POC3, the source of which is coupled to the output of the buffer circuit 24 (ie, the source of the transistors 242 and 243), and the drain is coupled to the node N11. The gate of the NMOS transistor 301 receives the control signal POC2, the drain of which is coupled to the output of the buffer circuit 24 (ie, the source of the transistors 242 and 243), and the source of the transistor 301 is coupled to the node N11. In the embodiment of Fig. 3, the circuits and elements having the same reference numerals as in the embodiment of the second A-2C diagram operate in the power-start control phase and the stabilization phase as in the above-described embodiment of the second embodiment A-2C, The description is omitted. Only the operation of the transfer gate 30 will be described below. In the power-on control phase, the PMOS transistor 300 and the NMOS transistor 301 are turned off according to a control signal POC3 having a voltage level of 3.3 V and a control signal POC2 having a voltage level of 0 V, respectively. Therefore, the feedback circuit 104 does not provide a feedback path between the nodes N21 and N11, and thus, the feedback circuit 104 does not change the voltage level on the node N11 according to the control signal POC2. In the stabilization phase, the PMOS transistor 300 and the NMOS transistor 301 are turned on according to the control signal POC3 having a voltage level of 0 V and the control signal POC2 having a voltage level of 3.3 V, respectively. Therefore, the feedback circuit 104 provides a feedback path between the nodes N21 and N11 to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V.

In another embodiment, referring to FIG. 4, the feedback circuit 104 further includes a transfer gate 40 coupled between the node 21 and the input of the buffer circuit 24. The transfer gate 40 includes a PMOS transistor 400 and an NMOS transistor 401. The gate of the PMOS transistor 400 receives the control signal POC3, the source of which is coupled to the node N21, and the drain of which is coupled to the input terminal of the buffer circuit 24 (ie, the gates of the transistors 240 and 241). The gate of the NMOS transistor 401 receives the control signal POC2, the drain of which is coupled to the node N21, and the source thereof is coupled to the input terminal of the buffer circuit 24 (ie, the gates of the transistors 240 and 241 are coupled). In the embodiment of Fig. 4, the circuits and elements having the same reference numerals as in the embodiment of the second A-2C diagram operate in the power-start control phase and the stabilization phase as in the above-described embodiment of the second embodiment A-2C, The description is omitted. Only the operation of the transfer gate 40 will be described below. In the power-on control phase, the PMOS transistor 400 and the NMOS transistor 401 are turned off according to a control signal POC3 having a voltage level of 3.3 V and a control signal POC2 having a voltage level of 0 V, respectively. Therefore, the feedback circuit 104 does not provide a feedback path between the nodes N21 and N11, and thus, the feedback circuit 104 does not change the voltage level on the node N11 according to the control signal POC2. In the stabilization phase, the PMOS transistor 400 and the NMOS transistor 401 are turned on according to the control signal POC3 having a voltage level of 0 V and the control signal POC2 having a voltage level of 3.3 V, respectively. Therefore, the feedback circuit 104 provides a feedback path between the nodes N21 and N11 to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V.

In the above embodiments of FIGS. 2A, 3, and 4, the power source start control circuit 10 includes the resistor 101. In other embodiments, the power-on control circuit 10 does not have the resistor 101 in the embodiments of FIGS. 2A, 3, and 4, but the resistors provided by the PMOS transistor 25 of the switch circuit 100 are used as the 2A, 3, Resistor 101 in the embodiment of Figure 4. Referring to Fig. 5, in comparison with the embodiment of Fig. 2A, the power-on control circuit 10 does not have the resistor 101 of the embodiment of Fig. 2A. Referring to Fig. 6, in comparison with the embodiment of Fig. 3, the power-on control circuit 10 does not have the resistor 101 of the embodiment of Fig. 3. Referring to Fig. 7, in comparison with the embodiment of Fig. 4, the power-on control circuit 10 does not have the resistor 101 of the embodiment of Fig. 4.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

Claims (30)

 A power start control circuit for generating a first control signal for controlling an output stage circuit includes: a first power terminal for receiving a first voltage; and a second power terminal for receiving a second voltage a switching circuit having a control terminal for receiving the first control signal, an input coupled to the second power terminal, and an output coupled to the first node; an inverter chain circuit coupled to the first power source And having an input coupled to the first node for generating the first control signal; and a capacitor coupled between the first node and a ground; wherein, when the first power terminal receives The switching circuit is turned on according to the first control signal when the second voltage is not received by the second power terminal; and wherein the first power source receives the first voltage and the second power source When the terminal receives the second voltage, the switch circuit is turned off according to the first control signal.    The power start control circuit of claim 1, wherein the first voltage is different from the second voltage.    The power start control circuit of claim 2, wherein the first voltage is higher than the second voltage.    The power-on-control circuit of claim 1, wherein the switch circuit comprises a P-type transistor, the well region of the P-type transistor is coupled to the first power terminal, and the P-type transistor The gate, the source, and the drain are respectively coupled to the control end, the input end, and the output end of the switch circuit.    The power-on control circuit of claim 1, further comprising: a feedback circuit coupled to the inverter chain circuit and the first node, and receiving the first control signal; wherein, when the first When a power terminal receives the first voltage and the second power terminal receives the second voltage, the feedback circuit changes a voltage level on the first node according to the first control signal, and the inverter chain circuit A leakage current path is intercepted according to the changed voltage level on the first node.    The power-on control circuit of claim 5, wherein the feedback circuit comprises: a buffer circuit coupled to the first power terminal, coupled to the inverter chain circuit to receive the first control An input end of the signal and an output coupled to the first node; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the voltage level on the first node Equal to the voltage level of the first control signal.    The power-start control circuit of claim 6, wherein the feedback circuit further comprises: a transmission gate coupled between the output end of the buffer circuit and the first node, and controlled by the a first control signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the transmission gate is turned on.    The power-on control circuit of claim 7, wherein the transmission gate is turned off when the first power terminal receives the first voltage and the second power terminal has not received the second voltage.    The power-on control circuit of claim 6, wherein the feedback circuit further comprises: a transmission gate coupled between the inverter chain circuit and the input end of the buffer circuit, and controlled And the first control signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the transmission gate is turned on.    The power-on control circuit of claim 9, wherein the transmission gate is turned off when the first power terminal receives the first voltage and the second power terminal has not received the second voltage.    The power-start control circuit of claim 1, wherein the inverter chain circuit comprises a first reverse circuit and a second reverse circuit connected in series; and wherein the first reverse circuit The input end is coupled to the first node, and the output end of the second reverse circuit generates the first control signal.    The power-start control circuit of claim 11, wherein the inverter chain circuit further includes a third reverse circuit coupled to an output of the second reverse circuit, the third reverse circuit The output terminal generates a second control signal to control the output stage circuit, and the first control signal and the second control signal are opposite to each other.    The power-on control circuit of claim 12, further comprising: a feedback circuit coupled to the inverter chain circuit and the first node, and receiving the first control signal and the second control signal Wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the feedback circuit is controlled by the first control signal and the second control signal according to the first The control signal changes the voltage level on the first node, and the inverter chain circuit intercepts a leakage current path according to the changed voltage level on the first node.    The power-on-control circuit of claim 1, further comprising: a resistor coupled between the switch circuit and the first node.    An input/output control circuit coupled to an input/output pad includes: a first power terminal for receiving a first voltage; a second power terminal for receiving a second voltage; and an output stage circuit And the first power supply terminal is coupled to the first power control terminal and controlled by a first control signal; and a power start control circuit coupled to the output stage circuit for generating the first control signal, including a switching circuit having a control electrode for receiving the first control signal, an input coupled to the second power terminal, and an output coupled to the first node; an inverter chain circuit coupled to the first power source And having an input coupled to the first node for generating the first control signal; and a capacitor coupled between the first node and a ground; wherein, when the first power terminal receives The switching circuit is turned on according to the first control signal when the second voltage is not received by the second power terminal; and wherein the first power source receives the first voltage and the second power source Receiving the second voltage The switching circuit being closed by the first control signal.    The input/output control circuit of claim 15, wherein the first voltage is different from the second voltage.    The input/output control circuit of claim 16, wherein the first voltage is higher than the second voltage.    The input/output control circuit of claim 15, wherein the switch circuit comprises a P-type transistor, the well region of the P-type transistor is coupled to the first power terminal, and the P-type transistor The gate, the source, and the drain are respectively coupled to the control terminal, the input terminal, and the output terminal of the switch circuit.    The input/output control circuit of claim 15, wherein the power-on control circuit further includes: a feedback circuit coupled to the inverter chain circuit and the first node, and receiving the first a control signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the feedback circuit changes a voltage bit on the first node according to the first control signal And the inverter chain circuit intercepts a leakage current path according to the changed voltage level on the first node.    The input/output control circuit of claim 19, wherein the feedback circuit comprises: a buffer circuit coupled to the first power terminal, and having the inverter chain coupled to receive the first An input end of the control signal and an output coupled to the first node; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the voltage bit on the first node It is quasi-equal to the voltage level of the first control signal.    The input/output control circuit of claim 20, wherein the feedback circuit further comprises: a transmission gate coupled between the output end of the buffer circuit and the first node, and controlled by The first control signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the transmission gate is turned on.    The input/output control circuit of claim 21, wherein the transmission gate is turned off when the first power terminal receives the first voltage and the second power terminal has not received the second voltage.    The input/output control circuit of claim 20, wherein the feedback circuit further comprises: a transmission gate coupled between the inverter chain circuit and an input end of the buffer circuit, and Controlling the first control signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the transmission gate is turned on.    The input/output control circuit of claim 23, wherein the transmission gate is turned off when the first power terminal receives the first voltage and the second power terminal has not received the second voltage.    The input/output control circuit of claim 15, wherein the inverter chain circuit comprises a first reverse circuit and a second reverse circuit connected in series; and wherein the first reverse The input end of the circuit is coupled to the first node, and the output end of the second reverse circuit generates the first control signal.    The input/output control circuit of claim 25, wherein the inverter chain circuit further comprises a third reverse circuit, and the third reverse circuit is coupled to the output of the second reverse circuit The output end of the third reverse circuit stage generates a second control signal, and the first control signal and the second control signal are mutually opposite; and wherein the output stage circuit is more controlled by the Second control circuit.    The input/output control circuit of claim 26, further comprising: a feedback circuit coupled to the inverter chain circuit and the first node, and receiving the first control signal and the second control a signal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the feedback circuit is controlled by the first control signal and the second control signal according to the first A control signal is used to change the voltage level on the first node, and the inverter chain circuit intercepts a leakage current path according to the changed voltage level on the first node.    The input/output control circuit of claim 15, wherein the power-on control circuit further includes: a resistor coupled between the switch circuit and the first node.    The input/output control circuit of claim 15, wherein the inverter chain circuit further generates a second control signal, and the first control signal and the second control signal are opposite to each other; The output stage circuit includes: a first first type transistor, a control electrode for receiving the first control signal, an input electrode coupled to the first power terminal, and an output electrode coupled to a second node; a first type of transistor having a control electrode for receiving the second control signal, an input electrode coupled to a third node, and an output electrode coupled to the ground; a second first type transistor having a coupling a control electrode of the second node, an input electrode coupled to the first power terminal, and an output electrode coupled to the input/output pad; and a second second type transistor having a control electrode coupled to the third node And an input electrode coupled to the input/outlet pad and an output electrode coupled to the ground.    The input/output control circuit of claim 29, further comprising: a gate control circuit coupled to the control electrode of the second first type transistor and the control electrode of the second second type transistor And coupling the second power terminal; wherein, when the first power terminal receives the first voltage and the second power terminal receives the second voltage, the first first type transistor and the first second The type transistor is turned off, and the second first type transistor and the second second type transistor are controlled by the gate control circuit.