JP2003016780A - Non-volatile memory unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory unit having high reliability by eliminating the influence of erroneous write-in caused at the time of applying a power source. SOLUTION: A memory element array has a dummy memory element 5 selected by an address decoder 2 corresponding to a zero potential logic of an address signal when a power source is turned on, and a plurality of memory elements 3 selected by the address decoder 2 at the time of normal operation the prescribed time after the power source is turned on, a switching means consisting of a delay circuit 8 and an address conversion circuit 7 switches selection operation by the address decoder 2 from the dummy memory element 5 to the plurality of memory elements 3 the prescribed time after the power source is turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device using a non-volatile memory element including a ferroelectric non-volatile memory.

[0002]

2. Description of the Related Art A mainstream memory device at present is a volatile memory which loses its stored contents when the power is turned off, as represented by a dynamic random access memory (DRAM) using an oxide film as a capacitor in a memory element. It was sex memory. Therefore, in recent years, many non-volatile memory devices that can retain stored contents without power loss have appeared. Typical examples of the memory element that realizes the non-volatile memory device include a flash memory and a ferroelectric memory. In particular,
Although a ferroelectric memory is a non-volatile memory, it enables low voltage, high-speed rewriting, and a large number of times of rewriting as compared with a flash memory, and has the potential as a memory device that can replace the currently mainstream DRAM.

[0003]

However, as compared with a volatile memory such as a DRAM that does not need to retain the stored information when the power is turned off, the non-volatile memory needs to retain the stored content at all times. In particular, in the case of a ferroelectric non-volatile memory that can be rewritten at a low voltage in a short time, erroneous writing is likely to occur even if a whisker-shaped noise is included in the selection signal, and the circuit in the memory device is turned on when the power is turned on. There is a problem in that the potential of the node is indefinite, the specific address signal line is temporarily activated, and erroneous writing easily occurs in the memory element connected to the specific address signal line. Before the power is turned on, the internal circuit node potential is usually zero potential, so that the address line in which the erroneous writing easily occurs is often the address line corresponding to the zero potential logic. This erroneous writing will be described with reference to the drawings.

FIG. 6 shows a block diagram of a conventional nonvolatile memory device. Reference numeral 1 is an address signal line, 2 is an address decoder, 3 is a memory element array consisting of N memory elements M0 to M (N-1), 4 is a word line driver, and 5 is an address line selected by zero potential logic. Memory element (M0)
Indicates. When the power supply is turned on, the internal circuit node potential becomes indefinite, and if a whisker-like noise is on the selection signal line connected to the memory element 5, erroneous writing occurs in the memory element 5.

FIG. 7 shows a circuit diagram of a conventional nonvolatile memory device. Note that, in FIG. 7, the same components as those in FIG. 6 are denoted by the same reference numerals. Further, for simplification of the drawing, only the configuration in which the four memory elements 3 are selected by the two address signal lines is shown. Reference numeral 41 is an enable signal (Enable) line of the memory device, 42 is an address decode signal (ADR0) line which is activated when the address signal line 1 has a zero potential logic, and 43 is a selected word signal (WL0) line of the memory element 5. .

FIG. 8 shows a timing chart of the above signals when the power of the conventional nonvolatile memory device is turned on.
First, before the power supply VDD is turned on, the address signal A
DR is normally at zero potential (logic low level). When the power supply VDD is turned on, the logic of the address decoder 2 causes the decode signal A on the address decode line 42.
DR0 rises to a logic high level. The signal WL0 of the selected word line 43 is controlled by the enable signal Enable, and when not operating, the enable signal Enable is enabled.
Is in a logic low state, it is not activated.

However, as shown in FIG. 8, when a power supply is turned on, an indefinite potential node is generated in the control circuit portion of the enable signal Enable, and a whisker-like noise A is temporarily generated as a result of this. Since the decode signal ADR0 on the line 42 is at the logic high level, the signal WL0 on the word line 43 rises to the logic high level. As a result, the memory element 5 is selected, and erroneous writing occurs in the memory element 5 at that time.

The present invention has been made in view of the above problems, and an object of the present invention is to eliminate the influence of erroneous writing at power-on and provide a highly reliable nonvolatile memory device. is there.

[0009]

To achieve the above object, a first non-volatile memory device according to the present invention is a memory device array in which a plurality of non-volatile memory devices are arranged, and a memory according to an input address signal. A non-volatile memory device having means (address decoder) for selecting a single memory element in an element array, wherein the memory element array corresponds to a zero potential logic of an address signal when power is turned on. A non-volatile memory device comprising one first memory element (dummy memory element) selected by the selection means and a plurality of second memory elements selected by the selection means after a predetermined time has elapsed after power is turned on. Further comprises means for switching the selection operation by the selection means from the first memory element to the plurality of second memory elements after a predetermined time has elapsed since the power was turned on. That.

In this first non-volatile memory device, the switching means includes a delay circuit for delaying the rise time of the power supply voltage by a predetermined time, and a signal output from the delay circuit, among the plurality of second memory elements. It is preferable to provide an address conversion circuit that supplies a signal for controlling selection of the memory element corresponding to the zero potential logic of the address signal to the selection means.

According to the above configuration, even if a word line having an address signal of zero potential logic is temporarily activated when power is turned on and an erroneous write occurs, the erroneously written first memory element (dummy memory element ) Is not used during normal operation, the stored information of the normally used nonvolatile memory element does not change into erroneous contents, and a highly reliable nonvolatile memory device can be realized.

The first nonvolatile memory device preferably includes a potential initialization circuit connected to the address signal line. In this case, the potential initialization circuit preferably includes a pull-down resistor connected between the address signal line and the ground potential.

According to this structure, for example, by providing the potential initialization circuit including the pull-down resistor connected to the address signal line, the address signal line can be surely set to the zero potential logic when the power is turned on, and the power is turned on. Even when erroneous selection occurs, erroneous writing to the dummy memory element 5 can be ensured, and erroneous writing does not occur in the memory element selected during normal operation, which has stable non-volatile data retention characteristics. A non-volatile memory device can be realized.

To achieve the above object, a second non-volatile memory device according to the present invention comprises a memory element array in which a plurality of non-volatile memory elements are arranged, and a single one of the memory element arrays according to an input address signal. Non-volatile memory device having a first selecting means (address decoder) for selecting the memory element of, and a second selection for selecting a memory element corresponding to the zero potential logic of the address signal after a predetermined time after the power is turned on. It is characterized by having means.

In the second non-volatile memory device, the second selection means selects one of the memory element arrays based on the delay circuit delaying the rise time of the power supply voltage by the predetermined time and the signal output from the delay circuit. It is preferable to provide an address conversion circuit that supplies a signal for selecting and controlling the memory element whose address signal corresponds to the zero potential logic to the first selecting means.

According to the above configuration, in addition to the advantages of the first non-volatile memory device, it is not necessary to provide a dummy memory element and its associated circuit, and the chip area can be reduced.

Further, it is preferable that the second non-volatile memory device includes a potential initialization circuit connected to the address signal line. In this case, the potential initialization circuit preferably includes a pull-down resistor connected between the address signal line and the ground potential.

According to this structure, the address signal line can be surely set to the zero potential logic when the power is turned on, and a nonvolatile memory device having stable nonvolatile data holding characteristics can be realized.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a non-volatile memory device according to the first embodiment of the present invention. In addition, in FIG. 1, the same components as those in FIG. The difference between this embodiment and the conventional example of FIG. 6 is that the memory element array 3 uses the memory element 5 corresponding to the address 0 as a dummy memory element.
N together with N memory elements selected during normal operation
The point is that it has +1 memory elements and that the power supply voltage VDD from the power supply terminal 6 is supplied as a control signal to the address conversion circuit 7 via the delay circuit 8.

FIG. 2 is a circuit diagram showing the configuration of the nonvolatile memory device of FIG. In addition, in FIG. 2, the same components as those in FIG.
Further, in order to simplify the drawing, one dummy memory cell 5 (M0) and four memory elements 3 (M1 to M4) selected during normal operation are selected by two address signal lines. Shows only.

In FIG. 2, reference numeral 7 is an address conversion circuit composed of an exclusive NOR gate, 8 is a delay circuit composed of a CR time constant circuit, and 5 is a dummy memory element (M
0), 3 are N memory elements (M1 to MN) selected during normal operation, 31 is a memory element (M1) corresponding to address 0 selected in place of the dummy memory element 5 during normal operation, 42 Is an address decode signal (ADR0) line for selecting the dummy memory element 5, 43 is a selected word signal (WL0) line corresponding to the dummy memory element 5,
Reference numeral 44 denotes an address decode signal (ADR1) line to the memory element 31 (M1) selected in place of the dummy memory element 5 (M0) during normal operation.

The operation of the non-volatile memory device of FIGS. 1 and 2 will be described below with reference to the timing chart of FIG.

When the power is turned on, the signal A on the address signal line 1
When DR is at a zero potential (Low level), the signal ADR0 of the address decode signal line 42 becomes High level due to the logic of the address decoder 2, and at that time, the signal Enable of the enable signal line 41 has a whisker noise. When added, the signal WL0 of the word line 43 rises, causing erroneous writing to the memory element 5 (M0). The processes up to this point are the same as those of the conventional nonvolatile memory device.

However, the memory element 31 (M1) selected by the address 0 in the normal operation is not selected when the power is turned on. The reason for this will be described below.

When the power supply voltage VDD from the power supply terminal 6 rises to the high level when the power is turned on, the delay circuit 8
As a result, the signal S81 of the node 81 rises slowly and later than the rise of the power supply voltage VDD. Here, the CR time constant of the delay circuit 8 is set such that the rising edge of the signal S81 at the node 81 is later than the timing at which the memory element 5 (M0) is erroneously selected. At this time, the input of the address conversion circuit 7 is Lo when the power is on.
Since it is at the w level, the signal S7 at the output node 71 is
1 becomes High level.

Therefore, the signal ADR1 of the address decode signal line 44 for selecting the memory element 31 (M1) is Low.
The signal level of the enable signal line 41 remains
Even if the whisker-like noise A is added to the table, the memory element 31
(M1) is never selected.

After that, when the signal S81 of the node 81 rises and the input of the address conversion circuit 7 is recognized to be at the high level, the signal S7 of the output node 71 is detected.
1 drops to Low level. After that, the signal ADR1 of the address decode signal line 44 rises to the High level, and the selection operation at the address 0 for the memory element 31 (M1) becomes possible.

As described above, according to the present embodiment, the dummy memory element 5 is used in the unstable state when the power is turned on.
It is possible to realize a non-volatile memory device that can be switched to select another memory element during the normal operation after the power is turned on.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a nonvolatile memory device according to the embodiment. Note that, in FIG. 4, the same components as those in FIG. The second embodiment differs from the first embodiment in that the pull-down resistor 9
It has a potential initialization circuit consisting of

When the power is turned on, the address signal ADR on the address signal line 1 normally has a zero potential logic. However, when the address signal itself input to the address decoder 2 is generated through a plurality of logic circuits or due to the coupling noise due to the stray capacitance component between the wirings, the zero potential logic is stochastically small. There is a possibility that erroneous writing will occur in memory elements other than the address 0.

The present embodiment solves such a problem, and has a configuration in which the address signal line 1 is pulled down to the ground potential by using a resistance element. With this configuration, the address signal line can be surely set to the zero potential logic when the power is turned on, and erroneous writing to the dummy memory element 5 can be ensured even when erroneous selection occurs when the power is turned on.
It is possible to realize a non-volatile memory device having stable non-volatile data retention characteristics in which erroneous writing does not occur in a memory element selected during normal operation.

Further, in the first and second embodiments of the present invention, the dummy memory element 5 in which erroneous writing may occur.
However, it goes without saying that only the dummy selection signal system circuit of the present invention may be provided without providing the dummy memory element.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a nonvolatile memory device according to the embodiment. Note that, in FIG. 5, the same components as those in FIG. The third embodiment is different from the first and second embodiments in that a NAND element to which the address signal ADR of the dummy memory element 5 is input, a NAND element to which the ADR0 signal and the Enable signal are input, and its output. The point is that there is no inverter element and dummy memory element 5 connected to.

The operation of this configuration is the same as that of the first and second embodiments described above except that there is no selection signal ADR0 for the dummy memory element 5, and the same effect is obtained. You can get it.

Further, this embodiment has an advantage that the chip area can be reduced because it is not necessary to provide the dummy memory element 5 and its associated circuit.

[0037]

As described above, according to the present invention,
Even if a word line whose address signal is a zero-potential logic is temporarily activated when power is turned on and an erroneous write occurs, the erroneously written memory element is not used during normal operation. Information stored in the non-volatile memory device does not change to erroneous contents, and a highly reliable non-volatile memory device can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of the nonvolatile memory device of FIG.

FIG. 3 is a timing chart of signals at various parts when the power is turned on in the nonvolatile memory device of FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing a configuration of a nonvolatile memory device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a nonvolatile memory device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional nonvolatile memory device.

7 is a circuit diagram showing an internal configuration of the nonvolatile memory device of FIG.

FIG. 8 is a timing chart of signals at various parts of the nonvolatile memory device of FIG. 6 when the power is turned on.

[Explanation of symbols]

1 Address signal line 2 address decoder 3 Memory element array 4 word line driver 5 Dummy memory element 6 power terminals 7 Address conversion circuit 8 delay circuits 9 potential initialization circuit

Claims (8)

[Claims] 1. A non-volatile memory device comprising: a memory element array having a plurality of non-volatile memory elements arranged therein; and means for selecting a single memory element from the memory element array according to an input address signal. The memory element array includes one first memory element selected by the selecting means in response to a zero potential logic of an address signal when the power is turned on, and a predetermined time after the power is turned on. A plurality of second memory elements selected by a selection unit, wherein the nonvolatile memory device selects from the first memory element to the plurality of second memory elements after the power is turned on and the predetermined time has elapsed. A non-volatile memory device comprising means for switching selection operation by means. 2. The switching means includes a delay circuit for delaying a rise time of a power supply voltage by the predetermined time, and an address signal among the plurality of second memory elements based on a signal output from the delay circuit. 2. The non-volatile memory device according to claim 1, further comprising an address conversion circuit for supplying a signal for selecting and controlling the memory element corresponding to the zero potential logic to the selecting means. 3. The non-volatile memory device according to claim 1, wherein the non-volatile memory device includes a potential initialization circuit connected to an address signal line. 4. The non-volatile memory device according to claim 3, wherein the potential initialization circuit comprises a pull-down resistor connected between an address signal line and a ground potential. 5. A non-volatile memory device having a memory element array in which a plurality of non-volatile memory elements are arranged, and a first selecting means for selecting a single memory element in the memory element array according to an input address signal. A non-volatile memory device, comprising: a second selection unit that enables selection of a memory element corresponding to a zero potential logic of an address signal after a predetermined time has elapsed after power is turned on. 6. The delay circuit delays a rise time of a power supply voltage by the predetermined time, and the second selection circuit outputs an address signal of the memory element array based on a signal output from the delay circuit. 6. The non-volatile memory device according to claim 5, further comprising an address conversion circuit which supplies a signal for selecting and controlling a memory element corresponding to a zero potential logic to the first selecting means. 7. The non-volatile memory device according to claim 5, wherein the non-volatile memory device includes a potential initialization circuit connected to an address signal line. 8. The non-volatile memory device according to claim 7, wherein the potential initialization circuit includes a pull-down resistor connected between an address signal line and a ground potential.