JP2002208284A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable selecting whether or not write is performed in the arbitrary direction of data for each bit in a multi-bit device. SOLUTION: When a specific direction of data is inputted, a signal turning on a switch for selecting a column is disabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device to which multi-bit input data is input.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device to which multi-bit input data is inputted (so-called × 4 / × 8 / × 9 / ×
16 / × 18 / × 32 / × 36 / × 64 / × 72 multi-bit products).

[0003] Even in such multi-bit products, in application fields such as a memory tester Fail memory (memory for storing a defective address detected in a memory test) and an image processing application product, There has been a request to perform a data rewriting operation for each bit of multi-bit input data.

By the way, some multi-bit products have a function of prohibiting the writing of the whole input data controlled by a data write signal or the like when writing data.

[0005]

However, in order to rewrite only a part of the bits of the multi-bit input data, the entire data stored in the memory cell of the corresponding address is once read, and the entire data is stored in the register. After capturing, rewrite the bit data that you want to rewrite,
An operation of writing the entire data again was necessary.

As described above, some conventional multi-bit products have a function of prohibiting the writing of the entire input data. However, each bit has an arbitrary data direction (“0” data or “1”). It was not possible to select whether or not to write "data".

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to make it possible to select whether or not to perform writing in an arbitrary data direction for each bit in a multi-bit product. And

[0008]

A semiconductor memory device according to the present invention comprises, for example, a plurality of memory cells each storing data, a plurality of input data control circuits for receiving input data consisting of a plurality of bits, And a write control circuit for prohibiting the writing of data to the corresponding memory cell on a bit-by-bit basis when each bit is predetermined data.

Further, a semiconductor memory device according to the present invention is
For example, a plurality of memory cells for storing data, a plurality of bit line pairs connected to the plurality of memory cells, a plurality of input data control circuits for receiving input data, and a plurality of bit line pairs correspond to each of the plurality of bit line pairs. And a selection control circuit provided corresponding to each of the selection circuits and controlling selection / non-selection of the selection circuit, wherein the selection control circuit comprises: When the input data is predetermined data, the corresponding selection circuit is not selected.

According to the present invention, by adopting the above configuration, it is possible to select whether or not to perform writing in an arbitrary data direction for each bit in a multi-bit product.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment First Embodiment of the Present Invention
FIG. 1 shows a circuit configuration diagram of the semiconductor memory device according to the first embodiment. This embodiment shows an example in which writing of “1” data is prohibited.

As shown in FIG. 1, a cell array 1 includes a memory cell 2 for storing data "0" or "1" and a bit line pair 3 connected thereto. Here, an SRAM cell is used as the memory cell 2, but not only the SRAM but also the DR
It is also possible to use cells of other semiconductor storage devices such as AM.

Each bit line pair 3 is connected to an I / O line pair 5 via a column selection switch 4. The gate of the transistor constituting the column selection switch 4 has
A column selection switch control circuit 10 is connected.
The column selection switch control circuit 10 includes a column address, a normal write signal WE, and a write inhibit signal W.
P, input data Din, and a logic signal from a control terminal are input.

Specifically, the column selection switch control circuit 10 receives the NAND circuit 7 to which the input data Din and the write inhibit signal WP are inputted, and the output of the NAND circuit 7 and the normal write signal WE. AND circuit 8
It has an OR circuit 14 to which an output of the AND circuit 8 and a logic signal from the control terminal are input, and an AND circuit to which an output of the OR circuit 14 and an output of the column decoder 17 are input. Note that the column address is input to the column decoder 17 via the column address buffer 16.

On the other hand, the input data Din is supplied to the input data control circuit 6 as a complementary signal. Input data control circuit 6 is connected to I / O line pair 5. I / O line pair 5
It is connected to the bit line pair 3 via the column selection switch 4.

The write operation of the semiconductor memory device is performed as follows.

First, externally input data Din
Are complementary signals when transmitted directly to the input data control circuit 6 and when transmitted to the input data control circuit 6 via the inverter 9. Here, the input data control circuit 6 controls not to transmit the input data Din to the I / O line pair 5 at the time of reading, and controls the write timing of the input data Din.

The input data Din output from the input data control circuit 6 passes through the I / O line pair 5 and is transmitted to the bit line pair 3 via the column selection switch 4 and is stored in the memory cell 2. You. This column selection switch 4
Is a selection circuit for selecting a column of a memory cell into which the input data Din is to be written.

Here, the first embodiment of the present invention is characterized in that the column selection switch control circuit 10 for controlling the column selection switch 4 is configured as follows.

That is, conventionally, the column selection switch 4
Is mainly controlled by a signal from the column decoder 17. On the other hand, the present embodiment is characterized in that the write inhibit control circuit 13 is included in the column select switch control circuit.

More specifically, the write inhibit control circuit 13
Has a NAND circuit 7 to which input data Din and a write inhibit signal WP are input, and an AND circuit 8 to which an output of the NAND circuit 7 and a normal write signal WE are input. The output of the AND circuit 8 and a logical signal (for example, a read signal) from another control terminal (not shown) are input to the OR circuit 14, and the output of the OR circuit 14 and the signal from the column decoder 17 are ANDed. Input to the circuit 15. The output from the AND circuit 15 is input to the gate of the column selection switch 4.

Although the write inhibit signal WP has a negative logic in FIG. 1, if the signal WP has a positive logic, it is converted to an inverse signal before the NAND circuit 7 takes the logic with the input data Din. Just do it.

Next, the column selection switch control circuit 10
Will be described.

In the write state, when a certain column address is selected and writing of predetermined data is to be prohibited in a memory cell corresponding to the column address (here, writing of "1" data is prohibited). Inhibit), a low level (hereinafter referred to as “L level”) is input as the write inhibit signal WP.

At this time, when "1" is input as the input data Din, the output of the NAND circuit 7 goes low. Therefore, the output of the AND circuit 8 becomes L level.
As a result, the column selection switch 4 is turned off, and the input data “1” is not written in the memory cell 2.

On the other hand, when "0" is input as the input data Din, the output of the NAND circuit 7 goes high (hereinafter referred to as "H level"), and the normal write signal WE
Is at the H level, the output of the AND circuit 8 also goes to the H level. Thus, if the signal from the column decoder 17 is also at the H level, the column selection switch 4 is turned on, and the input data “0” is written into the memory cell 2.

If the normal write signal WE is at L level, the output of the AND circuit 8 is at L level regardless of the write inhibit signal WP and the input data Din. As a result, the column selection switch 4 is turned off, and the input data is not written to the memory cell 2.

FIG. 2 shows what result is stored in the memory cell by the operation of the column selection switch control circuit 10 as described above.

As can be seen from FIG. 2, according to the prior art, what is stored as a result of the memory cell always matches the input data Din. In contrast, the first of the present invention
According to the embodiment, when the input data Din is "1", the existing data already stored in the memory cell is stored as it is as a result.

Next, FIG. 3 shows an operation timing chart of the present embodiment. FIG. 3 shows (1) the case of the clock asynchronous system and (2) the case of the clock synchronous system.

As shown in FIG. 3A, in the clock asynchronous semiconductor memory device, the address signal Address is determined, the write signal WE (the inverted signal of / WE) becomes H level, and the write inhibit signal WP Goes low, the data is written to the memory cell 2 when the input data Din is "0", but the data writing to the memory cell 2 is prohibited when the input data Din is "1".

As shown in FIG. 3B, in a clock synchronous semiconductor memory device, an address signal Address, an address status control signal / ADSC (a signal for taking address information into the device), a global write signal / GW. (A signal for determining whether a write operation or a read operation) and the write inhibit signal WP are the clock signal C
Determined in synchronization with LK. Also in this case, when the write inhibit signal WP goes to L level, the data is written to the memory cell 2 when the input data Din is "0", but is written to the memory cell 2 when the input data Din is "1". Data writing is prohibited.

As described above, in the first embodiment according to the present invention, in a multi-bit product, an arbitrary data direction (“1” in the first embodiment) is set for each bit of input data.
Data) can be selected. Second Embodiment FIG. 4 shows a circuit configuration diagram of a semiconductor memory device according to a second embodiment of the present invention. However, FIG. 4 shows only the write inhibit control circuit 13 constituting the switch control circuit 10 for column selection. Other parts are the same as those in FIG. In this embodiment,
An example in which writing of “0” data is prohibited is shown.

Write inhibit control circuit 13 shown in FIG.
1 is different from the write inhibit control circuit 13 shown in FIG. 1 in that input data Din is inverted and input to the NAND circuit 7.

With such a circuit configuration, when the write inhibit signal WP is at the L level, the input data D
When "0" is input as in, the output of the NAND circuit 7 becomes L level. Therefore, the output of the AND circuit 8 is L
Level. As a result, the column selection switch 4 is turned off, and the input data “0” is not written in the memory cell 2.

On the other hand, when "1" is input as input data Din, the output of NAND circuit 7 goes high, and if normal write signal WE is high, the output of AND circuit 8 also goes high. . As a result, the column selection switch 4 is turned on, and the input data “1” is written to the memory cell 2.

As described above, in the second embodiment according to the present invention, in a multi-bit product, an arbitrary data direction (“0” in the second embodiment) is set for each bit of input data.
Data) can be selected. << Third Embodiment >> FIG. 5 shows a circuit configuration diagram of a semiconductor memory device according to a third embodiment of the present invention. However, FIG. 5 shows only the write inhibit control circuit 13 constituting the switch control circuit 10 for selecting a column. Other parts are the same as those in FIG. In this embodiment,
An example in which it is possible to select which data of “0” data or “1” data is write-protected is shown.

Write inhibit control circuit 13 shown in FIG.
Is the write inhibit control circuit 13 shown in FIG.
Instead of the input data Din input to the D circuit 7, a non-exclusive OR circuit (hereinafter referred to as "EXNOR circuit") 11
The difference is that the output of is input. This EXNOR circuit 1
1, the input data Din and the data Dp whose writing is to be prohibited are input.

Next, the operation of the column selection switch control circuit shown in FIG. 5 will be described. (1) It is assumed that “0” is input as data Dp for which writing is to be prohibited.

Here, when "0" is inputted as the input data Din, the output of the EXNOR circuit 11 becomes H level. Then, when the write inhibit signal WP is at the L level, the output of the NAND circuit 7 goes to the L level.
Therefore, the output of the AND circuit 8 becomes L level, the column selecting switch 4 is turned off, and the input data “0” is not written in the memory cell 2.

On the other hand, when "1" is input as the input data Din, the output of the EXNOR circuit 11 goes low. Then, the output of the NAND circuit 7 becomes H level,
If the normal write signal WE is at H level, the output of the AND circuit 8 goes to H level. As a result, the column selection switch 4 is turned on, and the input data “1” is written to the memory cell 2. (2) It is assumed that "1" is input as data Dp to be prohibited from being written.

Here, when "1" is inputted as the input data Din, the output of the EXNOR circuit 11 becomes H level. Then, when the write inhibit signal WP is at the L level, the output of the NAND circuit 7 goes to the L level.
Therefore, the output of the AND circuit 8 becomes L level, the column selecting switch 4 is turned off, and the input data “1” is not written in the memory cell 2.

On the other hand, when "0" is input as the input data Din, the output of the EXNOR circuit 11 becomes L level. Then, the output of the NAND circuit 7 becomes H level,
If the normal write signal WE is at H level, the output of the AND circuit 8 goes to H level. As a result, the column selection switch 4 is turned on, and the input data “0” is written to the memory cell 2.

As described above, in the third embodiment according to the present invention, either the data “0” or the data “1” is write-protected by externally inputting the data Dp to be prohibited from being written. Can be selected. << Fourth Embodiment >> FIG. 6 shows a circuit configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention. However, FIG. 6 shows only the write inhibit control circuit 13 constituting the switch control circuit 10 for column selection. Other parts are the same as those in FIG. In this embodiment, the third
Similarly to the embodiment, an example is shown in which it is possible to select which data of “0” data or “1” data is write-protected.

The difference between the write inhibit control circuit 13 shown in FIG. 6 and the write inhibit control circuit 13 shown in FIG.
The point is that the data taken into the register 12 is used instead of the data Dp that is to be prohibited from being written and input to the NOR circuit 11. The register 12 captures data whose writing is to be prohibited by a command input before the normal operation.

Write inhibit control circuit 1 shown in FIG.
The operation 3 is almost the same as the operation described in the fifth embodiment. The only difference from the operation described in the fifth embodiment is that the data fetched into the register 12 is used instead of the data Dp to be prohibited from being written.
Other operations are the same.

As described above, in the fourth embodiment according to the present invention, the data Dp to be prohibited from being written is stored in the register, so that either the data “0” or the data “1” is prohibited from being written. Can be selected. Further, in the third embodiment, a pin for inputting data Dp whose writing is to be prohibited from the outside is required, whereas in this embodiment, an increase in the number of pins can be prevented.

[0048]

According to the present invention, by employing the above configuration, it is possible to select whether or not to perform writing in an arbitrary data direction for each bit in a multi-bit product.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an operation result diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is an operation timing chart of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a column selection switch control circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a column selection switch control circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a column selection switch control circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Cell array, 2 ... Memory cell, 3 ... Bit line pair, 4
... Column selection switch, 5 I / O line pair, 6 input data control circuit, 7 NAND circuit, 8 AND circuit, 9
... Inverter circuit, 10 ... Switch control circuit for column selection, 11 ... EXNOR circuit, 12 ... Register.

Claims (10)

[Claims] 1. A plurality of memory cells each storing data, a plurality of input data control circuits receiving input data consisting of a plurality of bits, and when each bit of the input data is predetermined data, And a write control circuit for prohibiting writing of data to the memory cell for each bit. 2. The write control circuit according to claim 1, wherein a write inhibit signal for inhibiting data write is input, and said write inhibit signal is in an activated state and said input data is predetermined data. 2. The semiconductor memory device according to claim 1, wherein writing of data to said corresponding memory cell is prohibited. 3. The write control circuit according to claim 1, wherein a reference signal is input, and when the reference signal matches the input data, writing of data to the corresponding memory cell is prohibited. The semiconductor memory device according to claim 1. 4. The write control circuit receives a write inhibit signal and a reference signal for inhibiting writing, respectively.
2. The data write to the corresponding memory cell is inhibited when the write inhibit signal is in an active state and the reference signal and the input data match. Semiconductor storage device. 5. A plurality of memory cells for storing data, a plurality of bit line pairs connected to the plurality of memory cells, a plurality of input data control circuits for receiving input data, and a plurality of bit line pairs. A plurality of selection circuits provided corresponding to each of the plurality of selection circuits; and a selection control circuit provided corresponding to each of the selection circuits and controlling selection / non-selection of the selection circuit. Is a semiconductor memory device, wherein when the input data is predetermined data, a corresponding selection circuit is not selected. 6. The selection control circuit receives a write inhibit signal for inhibiting data writing to the plurality of memory cells, activates the write inhibit signal, and sets the input data to a predetermined value. 6. The semiconductor memory device according to claim 5, wherein the corresponding selection circuit is not selected when the data is the data of (1). 7. The selection control circuit according to claim 5, wherein a reference signal is input, and when the reference signal and the input data match, the corresponding selection circuit is not selected. 13. The semiconductor memory device according to claim 1. 8. The selection control circuit receives a write inhibit signal for inhibiting data writing and a reference signal, and when the write inhibit signal is in an activated state, the selection control circuit is configured to output the reference signal and the input data. 6. The semiconductor memory device according to claim 5, wherein when the values match, the corresponding selection circuit is not selected. 9. The semiconductor memory device according to claim 3, wherein said reference signal is inputted from outside. 10. The semiconductor memory device according to claim 3, wherein said reference signal is generated based on data stored in a register.