JP2582300B2 - Memory access circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access circuit of a data flow type system in which, for example, data flows in synchronization with a pulse and processing is performed as data moves.

[Prior Art] FIG. 3 shows a conventional example of a memory access circuit of a data flow type system.

In the figure, 203 and 204 are pipeline registers, 205 is a memory body, and 206 is an address decoder.

A packet input line 212 is connected to the pipeline register 203. Here, a parallel bit string that includes information such as data required for memory access, an address signal, and a read / write flag and propagates in synchronization with a pulse is referred to as a packet.

The write data output from the pipeline register 203 is supplied to the memory main unit 205 via the write data line 227, and the read / write flag output from the pipeline register 203 is supplied to the memory main unit 205 via the read / write flag line 226. Is done.

A part of the address signal output from the pipeline register 203 is directly supplied to the memory main body 205 via the address line 223, and a part of the address signal is
The output of the address decoder 206 is supplied to the memory main body 205 via the chip enable line 225 as a chip enable signal.

A part of the packet output from the pipeline register 203 and whose contents are not changed by the memory access is supplied to the pipeline register 204 via the packet transfer line 222.

Read data from the memory main body 205 is supplied to the pipeline register 204 via the read data line 228. The packet output line 214 is connected to the pipeline register 204.

Reference numerals 201 and 202 denote transfer control circuits for controlling the propagation of a pulse.
11 is connected. When a pulse is supplied to the transfer control circuit 201, a write pulse is immediately supplied to the pipeline register 203, and after a predetermined time, the transfer control circuit 202
Is supplied with a pulse. When a pulse is supplied to the transfer control circuit 202, a write pulse is immediately supplied to the pipeline register 204, and a pulse is output to the pulse output line 213 after a predetermined time.

When the write pulse is supplied, the pipeline registers 203 and 204 hold data on the input line,
Output at the same time.

The memory body 205 is configured to operate as follows.

When the read / write flag from the read / write flag line 226 is set to the read value and the chip enable signal from the address decoder 206 becomes active, a read operation is performed in the memory body 205 and the address line 223
The data at the address specified by the address signal from is output to the read data line 228.

When the read / write flag from the read / write flag line 226 is set to a write value and the chip enable signal from the address decoder 206 becomes active, a write operation is performed in the memory body 205 and the address line 223
The write data from the write data line 227 is written to the address specified by the address signal from. The data on the read data line 228 has the same value as the data on the write data line 227 regardless of the state of the chip enable signal.

Note that when the chip enable signal is not active, the memory main body 205
Is in a non-selected state, and the stored contents are held.

In the above configuration, a case where reading is performed from the memory body 205 will be considered.

A packet whose read / write flag is set to a read value is supplied to the packet input line 212, and a pulse is supplied to the pulse input line 211. As a result, a write pulse is supplied from the transfer control circuit 201 to the pipeline register 203, and a packet supplied from the packet input line 212 is held and output to the pipeline register 203. Then, after a predetermined time, a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202.

During this time, the read / write flag from the read / write flag line 226, the address signals from the address lines 223 and 224, and the write data from the write data line 227 are stabilized to the contents of the packet, the read operation is performed in the memory body 205, and the read data line The read data is output to 228.

When a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202, the transfer control circuit 202 sends the pipeline register 2
04 is supplied with a write pulse, the pipeline register 204 holds data supplied from the read data line 228 and the packet transfer line 222, and outputs the data to the packet output line 214. Then, after a predetermined time, a pulse is output from the transfer control circuit 202 to the pulse output line 213.

 In this way, a series of read processing is performed.

When writing to the memory body 205,
By setting a write value to the read / write plug of the packet supplied to the packet input line 212, the write process is performed in the same manner as the above-described series of operations of the read process.

[Problems to be solved by the invention] However, in the memory access circuit of the example of FIG.
There are the following problems.

First, as the first packet, the write packet
It flows to the memory access circuit in the figure. When a series of write processing is performed and a pulse is output from the transfer control circuit 202 to the pulse output line 213, the memory access circuit returns to the standby state. At this time, the pipeline register 203
Holds the contents of the first packet, and the data is continuously supplied to the memory main body 205. That is,
The standby state is maintained while the write flag is supplied from the read / write flag line 226 and the chip enable signal in the active state is supplied from the chip enable line 225.

In this state, as the second packet, a write packet in which only the address signal supplied to the memory body 205 via the address line 223 is different from the first packet flows.

Here, based on the pulse supplied from the transfer control circuit 201, the content held in the pipeline register 203 is changed to the second
Attention is paid to a change in output data when the content is updated to the content of the packet.

The read / write flag remains unchanged as written. Also,
The chip enable signal remains unchanged in the active state. That is, when viewed from the memory main body 205, only the address signal changes while the read / write flag and the chip enable signal are stable in the write and active states, respectively.

This is because the operating characteristics of the memory body 205 and the address lines 2
Considering whether or not all the 23 bits change at the same time, etc., may cause erroneous writing or destruction of stored data.

4A shows the address signal from the address line 223, FIG. 4B shows the read / write flag from the read / write flag line 226, and FIG. 4C shows the chip enable signal from the chip enable line 225, but only the address signal changes. Time t ₀
The above-mentioned problem occurs.

Therefore, an object of the present invention is to provide a memory access circuit capable of performing stable writing.

[Means for Solving the Problems] The present invention relates to a first storage circuit that holds packet data including write data, a read / write flag, and an address signal supplied to a memory body in synchronization with a panel,
A second storage circuit that holds a chip enable signal originally supplied to the memory in synchronization with the pulse and has an initialization function, and a delay circuit that delays the pulse for a predetermined time; The chip enable signal held in the second storage circuit is initialized to an inactive state.

[Operation] The memory access circuit according to the present invention initializes the chip enable signal held in the second storage circuit to an inactive state by a pulse output from the delay circuit, so that the second storage circuit is disabled. You are in the selected state.
Then, when the address signal supplied to the memory main body changes in synchronization with the pulse, the chip enable signal becomes active, and the memory main body is in the selected state and writing is performed. Therefore, the address does not change when the memory main body is selected, and the erroneous writing and the destruction of the stored data accompanying this are avoided.

Embodiment An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, a packet input line 212 is connected to a pipeline register 207. The write data output from the pipeline register 207 is supplied to the pipeline register 203 via the write data line 229, and the read / write flag output from the pipeline register 207 is output via the read / write flag line 230 to the pipeline register 2
Supplied to 03.

A part of the packet output from the pipeline register 207 and not changed by the memory access is supplied to the pipeline register 203 via the packet transfer line 231.

A part of the address signal output from the pipeline register 207 is transferred to an address decoder 206 via an address line 224.
Supplied to The output of the address decoder 206 is supplied to the register 208 via the chip enable line 232.
The register 208 is supplied with a write pulse output from the transfer control circuit 201. When the write pulse is supplied, the register 208 holds the data on the input line and outputs the data at the same time. The output of the register 208 is supplied as a chip enable signal to the memory main body 205 via a chip enable line 225.

Further, the pulse input line 211 is connected to the transfer control circuit 209. When a pulse is supplied to the transfer control circuit 209, a write pulse is immediately supplied to the pipeline register 207, and a pulse is supplied to the transfer control circuit 201 after a predetermined time. When the write pulse is supplied, the pipeline register 207 holds the data on the input line and outputs the data at the same time.

The write pulse output from the transfer control circuit 201 is supplied to the delay circuit 210. The delay amount of the delay circuit 210 is set shorter than the packet input interval and longer than the time required for memory access.

The read / write flag output from the pipeline register 203 is supplied to the delay circuit 210 as a control signal. This delay circuit 210 does not output a pulse input from the transfer control circuit 201 when the read / write flag is read, while it outputs a pulse input from the transfer control circuit 201 with a delay when the read / write flag is write. .

The pulse output from the delay circuit 210 is supplied to the register 208 as an initialization pulse. When the initialization pulse is supplied, the output of the register 208 supplied to the memory body 205 as a chip enable signal via the chip enable line 225 is initialized so as to be in an inactive state.

The present example is configured as described above, and the rest is configured similarly to the example in FIG.

Hereinafter, the operation of the present example will be described. First, the memory body 205
Consider a case where reading is performed more.

A packet whose read / write flag is set to a read value is supplied to the packet input line 212, and a pulse is supplied to the pulse input line 211. As a result, a write pulse is supplied from the transfer control circuit 209 to the pipeline register 207, and a packet supplied from the packet input line 212 is held and output to the pipeline register 207. After a certain time, a pulse is supplied from the transfer control circuit 209 to the transfer control circuit 201.

The same operation is performed for the stage composed of the transfer control circuit 201 and the pipeline register 203, and the packet is held and output to the pipeline register 203. Then, after a certain time, a pulse is supplied to the transfer control circuit 202.

Here, the output of the address decoder 206 is held and output to the register 208 by a write pulse similar to that of the pipeline register 203.

Before the pulse is supplied to the transfer control circuit 202,
The read / write flag from the read / write flag line 226, the address signal from the address line 223, the write data from the write data line 227 are stable in the contents of the packet, and the value on the chip enable line 225 is stable in the active state, In the memory body 205, a read operation is performed, and the read data is output to the read data line 228.

In this case, the write pulse supplied from the transfer control circuit 201 to the delay circuit 210 is not output from the delay circuit 210 because the read / write flag is read, and the register 208
Output is not initialized.

When a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202, the transfer control circuit 202 sends the pipeline register 2
04 is supplied with a write pulse, the pipeline register 204 holds data supplied from the read data line 228 and the packet transfer line 222, and outputs the data to the packet output line 214. Then, after a predetermined time, a pulse is output from the transfer control circuit 202 to the pulse output line 213.

 In this way, a series of read processing is performed.

Next, a case in which writing is performed on the memory main body 205 will be considered.

A packet with a write value set in the read / write flag is supplied to the packet input line 212, and a pulse is supplied to the pulse input line 211. Then, through a series of operations similar to the above-described read, the packet is held and output to the pipeline register 203.

Before the pulse is supplied to the transfer control circuit 202,
The read / write flag from the read / write flag line 226, the address signal from the address line 223, the value of the write data from the write data line 227 are stable to the contents of the packet, and
The value on the chip enable line 225 is stabilized in the active state, and the write operation is performed in the memory main body 205.

In this case, the write pulse supplied from the transfer control circuit 201 to the delay circuit 210 is output from the delay circuit 210 after a predetermined time since the read / write flag is a write value. As a result, the output of the register 208 is initialized, the chip enable signal supplied to the memory main body 205 becomes inactive, and the memory main body 205 becomes non-selected. Then, the same data as the write data line 227 is output to the read data line 228.

After the pulse is supplied to the transfer control circuit 202, the same operation as reading is performed, and a series of writing processes is performed.

Here, the operation of the continuous writing process will be described.

First, when the first packet flows through the memory access circuit of the present example, a series of write operations is performed. When a pulse is output to the pulse output line 213, the memory access circuit returns to the standby state.

At this time, the pipeline register 203 holds the content of the first packet, and its value is continuously supplied to the memory main body 205. However, the chip enable signal from the chip enable line 225 is inactive due to the initialization pulse from the delay circuit 210. Accordingly, the read / write flag is in a write state, and the chip enable signal is in an inactive state in a standby state.

Next, as a second packet, a write packet in which only the address signal supplied to the memory main body 205 via the address line 223 is different from the first packet flows.

Here, pipeline register 203 and register 208
Is updated to the contents of the second packet based on the pulse supplied from the transfer control circuit 201, and the change in the output data until the output signal of the register 208 is initialized is focused on. .

The read / write flag remains unchanged as written. Also,
The chip enable signal changes from the inactive state to the active state when the address signal supplied from the address line 223 to the memory main body 205 changes to the content of the second packet, and returns to the inactive state after a certain period of time. I do.

When viewed from the memory main body 205, the chip enable signal is in an inactive state during standby, and is in a non-selected state. When the second packet reaches the pipeline registers 203 and 208, the address changes and , The chip enable signal becomes active, writing is performed, and the chip enable signal returns to the non-selected state as it returns to the inactive state again. That is, in the write operation, the address does not change while the memory main body 205 remains in the selected state, and the state changes from the non-selected state to the selected state through the change of the address.

2A shows an address signal from the address line 223, FIG. 2B shows a read / write flag from the read / write flag line 226, FIG. 2C shows an initialization pulse supplied from the delay circuit 210 to the register 208, and FIG. while indicating the chip enable signal from line 225, chip enable signal at a time t ₀ when the address signal is changed is changed to active from inactive state.

As described above, according to the present example, in the write operation to the memory main body 205, the address does not change while the memory main body 205 is in the selected state, and erroneous writing and destruction of stored data due to the address change in the selected state are prevented. Can be avoided.

[Effects of the Invention] As described above, according to the present invention, the standby memory main body after the write processing is in the non-selected state, so that the address changes while the memory main body is in the selected state and the write is specified. Therefore, erroneous writing, destruction of stored data, and the like can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is an explanatory diagram of its operation. 201, 202, 209 transfer control circuit 203, 204, 207 pipeline register 205 memory body 206 address decoder 208 register 210 delay circuit 211 pulse input line 212 packet input line 213 pulse output line 214 ... Packet output lines 222,231 ... Packet transfer lines 223,224 ... Address lines 225,232 ... Chip enable lines 226,230 ... Read / write flag lines 227,229 ... Write data lines 228 ... Read data lines

Claims (1)

(57) [Claims] A write data supplied to a memory body;
A first storage circuit that holds packet data including a read / write flag and an address signal in synchronization with a pulse; and a first storage circuit that holds a chip enable signal originally supplied to the memory in synchronization with the pulse and has an initialization function. And a delay circuit that delays the pulse by a predetermined time, and initializes a chip enable signal held in the second storage circuit to an inactive state by a pulse output from the delay circuit. A memory access circuit, characterized by: