JPS60170094A - I/o circuit of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an I/O circuit to ensure a high speed, low power comsumption and high reliability by providing a switch circuit which is provided between an output terminal of an input buffer circuit and an input terminal of a latch circuit and introduce an output of an input buffer circuit directly to latch circuit in accordance with the generation of an I/O switching control circuit. CONSTITUTION:When a WE signal is at a low level, the deivce is in the input data write enable condition and when is at a high level, is in the read enable condition. When the WE signal is at a low level under the write enable condition, a SW circuit 34 in on, the device has a bus to write data outputted from an input buffer circuit 12 directly to a memory circuit 13 and that to write data to a latch circuit 16 through the SW circuit 34. On the other hand, when an address will not change and the WE signal is changed from a low level to a high level, the device is read enable state, and an output buffer circuit 7 is bought into enable condition. Simultaneously, the SW circuit 34 becoms off, and data latched by the latch circuit 16 at the time of writing are outputted outside through the output buffer circuit 17.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an input/output circuit of a semiconductor device, and particularly to one used in a high-speed operation, low power consumption, and highly reliable semiconductor device. .

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 1 has been considered for a semiconductor device, for example, an internally synchronous semiconductor memory device. In other words, the reference numeral 11 in the figure is an input/output (Ilo) terminal that shares input and output functions], and when data is input, data supplied to this input/output terminal 11 is sent to a plurality of memory cells via an input buffer circuit 12. and is stored in a memory cell designated by a word line control (WLC) signal from an address transition detector (ATD) circuit 14. Conversely, when outputting stored data, the above AT
The data stored in the memory cell specified by the WLC signal from the D circuit 14 is sent to the column sense amplifier (a/
A) After being temporarily stored in the latch circuit 16 via the circuit 15, the signal is supplied to the I10 terminal 11 via the output sofa circuit 17. The output operating states of the human capacitor circuit J2, the S/A circuit 15, and the output sofa circuit 17 are each set by a write control (WE) signal from a central control circuit (not shown). .

By the way, the S/A circuit 15, as shown in FIG.
The data of the memory cell is taken out from L and BL, and is sent to the P-channel MO8) Lanzostar 1 according to the latch signal φL.
8.19 and N channel MO8) Lanzosta 20-22
A so-called latch type is generally used, in which a different latch circuit 15& selects and holds the selected signal and outputs the signal via an inverter 15b. However, such a latch-type S/A circuit 15 may malfunction depending on the latch timing. As shown by the dotted line in FIG. 3(a), the latch timing of the latch signal φL (time 1
If 1) is too early, the data will be latched before the data appears on the bit lines BL and BL, as shown in Figure 3(b), and the opposite data will be latched, as shown by the dotted line in Figure 3(b). Sometimes I end up doing it. Therefore, the latch type a/
The operating speed of the A circuit 15 is extremely slow in order to maintain an operating margin. A circuit with a higher operating speed is normally-on W such as a current mirror shop.
An S/A circuit is being considered. This normally on type S
/A circuit, for example, as shown in FIG.
O8) Current 11.12 from the power supply voltage VDD is passed through the current mirror circuit consisting of Lanzostars 23 and 24 to the latch circuit consisting of N-channel MO8) Lanzostars 25 to 28.
The latch circuit selectively holds the data taken out to the bit lines BL and BL in response to a chip enable (CE) signal.

However, since this normally-on fi S/A circuit always flows a current iJ+t2 as shown in the figure, it consumes a large amount of power. In order to reduce this power consumption, it is conceivable that K should set this S/A circuit to a non-operating state at least during a write operation. Also,
In order to reduce power consumption during reading, the memory cell is connected to resistors R1, R, ? as shown in FIG. and N-channel MO8) transistors 29 to 32, and after the address changes and the read operation is completed, the current 11. An effective method is to automatically cut off the signal +2 and also deactivate the word line WL to cut off the currents 13 and 14 flowing into the S/A circuit from the bit lines BL and BL.

However, with this method, the address changes during the write operation, and if a certain period of time has elapsed, the word line will be deactivated when the read operation begins, so the read operation will not be performed and the output data will not be processed. Cannot be guaranteed - To prevent this, 1. There is no change in the address. In order to ensure good data output even when transitioning from write operation to read operation, as shown in FIG. 1 again, a WE transition detector (WrD) circuit 33 is provided in parallel with the ATD circuit 14. W.E.
A possible method is to output the internal clock even when changing from the double signal enable state to the discontinued state, thereby activating the word line. However, this has the following problems.

(1) Since the S/A circuit 15 is in a discontinuous state during a write operation, when switching to a read operation, the WE signal goes high (H) as shown in FIG. 6(a). The output buffer circuit 17 is activated when the level changes from
As shown in FIG. 6(b), the data held in the latch circuit 16 is once output (period T in the figure), and then new data is output (period T2 in the figure). become. Therefore, unnecessary whisker-like signals may appear in the output.

(2) When the whisker-like unnecessary signals described in (1) appear in the output, noise components increase.

(In the state of 31 (1), if data opposite to the latched data is written, when the state is switched to the read operation state, the latched data and the data being written and input are contradictory.) Because of this, large currents may flow.

(4) Since the ATD method uses WE multiplied signals, access time is slow.

That is, in general, in the output buffer circuit 17 having the latch circuit 16 at the front stage as described above, the previous data A remains in the latch circuit 16), the input/output buffer circuit 12 is deactivated, and the output buffer circuit 17 is When activated, the previous data A is momentarily output from the latch circuit 16 to the output buffer circuit 12, and then the correct data B is output. Then, when data A and B are different, by the time data B is output, the output buffer circuit 17
This results in the output of whisker-like unnecessary signals.

Based on the above, the input/output circuit of a semiconductor device should be able to achieve high speed, low power consumption, and high reliability without outputting unnecessary signals when the operating state of υ input/output changes. This was strongly desired.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and it does not output unnecessary signals when the input/output operation status is switched, and has extremely high speed, low power consumption, and high reliability. The purpose of this invention is to provide an input/output circuit for a semiconductor device.

[Summary of the invention]

That is, the input/output circuit of the semiconductor device according to the present invention is as follows:
An input/output terminal that shares input/output, an input buffer circuit whose input terminal is connected to this input/output terminal, an output parallel circuit whose output terminal is connected to the input/output terminal, and an input terminal of this output parallel circuit. In the input/output circuit of a semiconductor device, the output terminal of the input bag 77 circuit has a latch circuit connected thereto, and is configured to switch and control the input state and output state of data according to the generation of an input/output switching control signal. and a switch circuit which is interposed between the input terminals of the latch circuit and leads out the output of the input cover sofa circuit directly to the latch circuit in response to the generation of the input/output switching control signal.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9. However, in FIG. 7, the same parts as in FIG. 1 are designated by the same reference numerals, and only the different parts will be described here.

FIG. 7 shows the hydrocyanic acid. In this semiconductor memory device, a switch (SW) circuit 34 is interposed between the output terminal of the input cover sofa circuit 12 and the input terminal of the latch circuit 16. The switch is controlled by the WE multiplication signal. For example, as shown in FIG. 8, this SW circuit 34 is composed of a transfer l'-)J(a and an inverter 94b), and the above WE multiplied signal is a transfer l'-)J(a) and an inverter 94b. It is designed to switch. Note that the WTD circuit 33 is not used in the device described above.

The operation of the above configuration will be described below.

First, in this device, when the above-mentioned WE double signal is at L level (enable state), input data can be written.6.
When the wg multiplied signal is at H level (Disneytle state), it becomes a readable state. Here, in the writable state,
Above WE1! When the number is L, the SW circuit 34
is in the on state, and Jin's device has a path for directly writing the data output from the input buffer circuit 12 into the storage circuit 13 and a path for writing it into the latch circuit 16 via the SW circuit 34. Become. In this state, the S/
If the A circuit 15 is set to the disabled state, 8/A
In the circuit 15, the current 11. shown in FIG. Since i2 is shut off, it becomes busy so that power consumption can be reduced.

On the other hand, if the address does not change and the WE multiplier signal changes from L level to H level, this device is not in a readable state as described above, and the SW circuit 34 is turned off at the same time as the output pesosophe child circuit 17 is enabled. become a state. Therefore, the data latched by the latch circuit 16 at the time of writing is transferred to the I10 terminal 1 via the output buffer circuit 17.
1, it will be output externally. That is, the above WE
When the double signal changes from H level to L level as shown in Figure 9 (-), an output signal as shown in Figure 9 (b) appears at the I10 terminal 11, and the output signal as shown in Figure 6 (b) appears. Such unnecessary signals are not generated.

Therefore, by configuring the input/output circuit of a semiconductor memory device as described above, power consumption during a write operation can be reduced, and even if the S/A circuit 15 enters the DisneySol state, the latch circuit 16 is already Since the data written in the memory circuit 13 is latched, there is no possibility of unnecessary No. 45 occurring in the output even when switching to read operation, and this also reduces noise components. I come to do it. Furthermore, when data opposite to the latched data is written and then a read operation is entered, there is no possibility that the data will collide with each other and a large current will flow. This makes it possible to provide a highly reliable semiconductor memory device.

By the way, if the above-mentioned device is of the ATD method as described above, it detects a change in the WE times signal and generates a pulse,
As a result, even if the memory cells are accessed, the time until the output is delayed and complicated problems such as the timing of pulses arise, but the data input to the input/output circuit cannot be transferred to the memory circuit. Since the data is directly written to the launch circuit 16 at the same time as the data is written to the launch circuit 13, the data can be read out at a very high speed, and there is no need to set the timing strictly.

Although the above embodiment has been explained using a semiconductor memory device as an example, the present invention can also be implemented in other semiconductor devices.In particular, in the case of a memory device, stored data may be destroyed by noise. It is therefore extremely important.

Furthermore, the present invention can be applied not only to an input/output circuit connected to the I10 terminal 11 but also to an internal bus.

〔Effect of the invention〕

As described above, according to the present invention, an extremely good input/output circuit of a semiconductor device can be achieved which is fast, has low power consumption, and has high reliability without outputting unnecessary signals when the input/output operation state is switched. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of an input/output circuit of a conventional semiconductor device, FIG. 2 is a circuit diagram showing the configuration of a latch type S/A circuit used in the semiconductor device, and FIG. 3 is a block diagram showing the configuration of the input/output circuit of the semiconductor device. FIG. 4 is a waveform diagram for explaining the drawbacks of the conventional latch type S/A circuit used in the above latch ill.
A circuit diagram showing the configuration of a current mirror type S/A circuit that replaces the S/A circuit, Figure 5 is a circuit diagram showing the configuration of a memory cell, and Figure 6 shows the output waveform when switching the operating state of the input/output circuit. FIG. 7 is a block circuit diagram showing one embodiment of the input/output circuit of the semiconductor device according to the present invention, FIG. 8 is a circuit diagram showing a specific configuration of the SW circuit of the above embodiment, and FIG.
The figure is a waveform diagram showing the output waveform when the operating state of the input/output circuit in the above embodiment is changed. 11... I10 terminal, 12... Input buffer circuit,
13... Memory circuit, 14... ATD circuit, 15...
・S/A circuit, 16...Latch circuit, 17...Output sofa circuit, 18-32...MOS) transistor, 33...WTD circuit, 34...SW circuit, 34a
...Transfer Dart. Applicant's Representative Patent Attorney Takehiko Suzue 1 Figure WE Figure 2 Figure 3 Figure 4 Figure m5 Figure 6 Figure 'TT T2 --- Figure 7 1/. W [Fig. 8 UT Continued from page 1 O Inventor Takayuki Otani @ Inventor Tetsuya Iizuka [Partner] Inventor Aono 1 Komukai Toshiba-cho, Saiwai-ku, Meiyousaki City Tokyo Shibaura Electric Co., Ltd. Kawasaki, Kawasaki City 2-11 Higashida-cho, Toshiba Microcomputer Engineering Co., Ltd.

Claims (2)

[Claims] (1) An input/output terminal that shares input and output, an input cover sofa circuit whose input terminal is connected to this input/output terminal, and an output terminal whose output terminal is connected to the input/output terminal. In the input/output circuit of a semiconductor device, the input/output circuit has a launch circuit and controls switching between the input state and the output state of data according to the generation of an input/output switching control signal. 1. An input/output circuit for a semiconductor device, comprising a switch circuit interposed between input terminals for directing an output of the input buffer circuit to a latch circuit in response to generation of the input/output switching control signal. (2) The input/output circuit for a semiconductor device according to claim 1, wherein the input/output terminal is an input/output terminal of a semiconductor memory.