JPH0458677B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an input/output circuit of a semiconductor device,
In particular, it relates to semiconductor devices that operate at high speed, consume low power, and are highly reliable.

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 1 has been considered for semiconductor devices, such as internally synchronous semiconductor memory devices. That is, the reference numeral 11 in the figure is an input/output (I/O) terminal that shares input and output.
At the time of data input, data supplied to this input/output terminal 11 is supplied to a storage circuit 13 composed of a plurality of memory cells via an input buffer circuit 12, and an address transition detector (ATD) circuit 14. is stored in the memory cell designated by the word line control (WLC) signal from. Conversely, when outputting stored data, the data stored in the memory cell designated by the WLC signal from the ATD circuit 14 is once sent to the latch circuit 16 via the column sense amplifier (S/A) circuit 15. After being stored, the I/O terminal 11 is sent via the output buffer circuit 17.
It is designed to be supplied to The output operating states of the input buffer circuit 12, S/A circuit 15, and output buffer circuit 17 are set by write control () from a central control circuit (not shown), respectively.
This is done by signals.

By the way, as shown in FIG. 2, the S/A circuit 15 takes out the data of the memory cell to the bit line BL, which is precharged by the signal, and transfers it to the P channel MOS in response to the latch signal φL. A so-called latch type is generally used in which a latch circuit 15a consisting of transistors 18, 19 and N-channel MOS transistors 20-22 selects and holds the signal and outputs the signal via an inverter 15b. However, such a latch type S/A circuit 15 may malfunction depending on the timing of the latch. In other words, the third
If the latch timing (time t1) of the latch signal φL is too early, as shown by the dotted line in the middle of FIG. As shown by the dotted line in b, reverse data may be latched. Therefore, the latch type S/A circuit 15
The operating speed is extremely slow in order to provide an operating margin.

Normally-on type S/A circuits such as current mirror type are being considered to increase the operating speed. This normally-on type S/A circuit is
For example, as shown in FIG. 4, N-channel MOS transistors 25 to 24 are
The latch circuit consisting of 28 is supplied with currents i1 and i2 from the power supply voltage _VDD , and the bit lines BL,
The data taken out to the BL is selected and held by the latch circuit according to the chip enable (CE) signal.

However, since this normally-on type S/A circuit always flows currents i1 and i2 as shown in the figure, it consumes a large amount of power. In order to reduce this power consumption, it is conceivable that this S/A circuit should be set to a non-operating state at least during a write operation. In addition, in order to reduce power consumption during reading, the memory cell is connected to resistors R1, R2 and an N channel as shown in FIG.
It consists of MOS transistors 29 to 32, and after the address changes and the read operation is completed, V _DD
In addition to automatically cutting off currents i1 and i2 from the power supply, the word line WL is also deactivated, and the bit line
The current i flowing into the above S/A circuit from BL,
3. A method of blocking i4 is effective.

However, in this method, if the address changes during a write operation and a certain period of time has elapsed, the word line will be deactivated when the read operation starts, so the read operation will not be performed.
Output data cannot be guaranteed.

In order to prevent this, that is, to ensure good data output even when transitioning from a write operation to a read operation without any change in address, as shown in FIG.・Transition detector (WTD)
A possible method is to provide a circuit 33 so that the internal clock is output even when the signal changes from the enabled state to the disabled state, thereby activating the word line. However, this has the following problems.

(1) Since the S/A circuit 15 is disabled during a write operation, when switching to a read operation, that is, the signal changes from high (H) level to low (L) level as shown in FIG. 6a. Output buffer circuit 17 when switching to level
is activated, and the data held in the latch circuit 16 is temporarily output to the I/O terminal 11 as shown in FIG. 6b (period T1 in the figure).
After that, correct data will be output (period T2 in the figure). Therefore, there is a possibility that unnecessary whisker-like signals may appear in the output.

(2) When the whisker-like unnecessary signals mentioned in (1) appear in the output, noise components increase.

(3) In the state of (1), if data opposite to the latched data is written, the latched data and the data being written and input will be different when switching to the read operation state. Because they are contradictory, there is a possibility that a large current will flow.

(4) Since the ATD method uses WE signals, access time is slow.

That is, in general, in the output buffer circuit 17 having the latch circuit 16 at the front stage as described above, the previous data A remains in the latch circuit 16, and the input buffer circuit 12 is deactivated and the output buffer circuit 17 is activated. When the latch circuit 16
After the previous data A is momentarily output to the output buffer circuit 17, the correct data B is output. If data A and B are different, an unnecessary whisker-like signal will be output from the output buffer circuit 17 before data B is output.

From the above, the input/output circuits of semiconductor devices need to be made high-speed, low-power consumption, and highly reliable without outputting unnecessary signals when the input/output operating state changes. was strongly desired.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and it does not output unnecessary signals when the input/output operating state is switched, and has extremely high speed, low power consumption, and high reliability. The purpose of this invention is to provide an input/output circuit for a semiconductor device.

[Summary of the invention]

That is, the input circuit of the semiconductor device according to the present invention includes an input/output terminal that shares input and output, an input buffer circuit whose input terminal is connected to the input/output terminal, and an output terminal whose output terminal is connected to the input/output terminal. An input/output circuit for a semiconductor device having a buffer circuit and a latch circuit connected to the input end of the output buffer circuit, and configured to switch and control the input state and output state of data according to an input/output switching control signal. , further comprising a switch circuit interposed between the output terminal of the input buffer circuit and the input terminal of the latch circuit, for directing the output of the input buffer circuit to the latch circuit when the input/output switching control signal is in an input state. It is characterized by this.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9. However, in Fig. 7, the same parts as in Fig. 1 are indicated with the same reference numerals.
Only the different parts will be described here.

FIG. 7 shows its configuration. In this semiconductor memory device, a switch (SW) circuit 34 is interposed between the output terminal of the input buffer circuit 12 and the input terminal of the latch circuit 16. Switching is controlled by the signal.
The SW circuit 34, for example, as shown in FIG. 8, is composed of a transfer gate 34a and an inverter 34b, and is configured to switch the transfer gate 34a in response to the WE signal. In addition, in this device, the above
WTD circuit 33 is not used.

The operation of the above configuration will be described below.

First, in this device, when the above-mentioned signal is at L level (enable state), the input data is in a writable state, and when the signal is at H level (disable state), it is in a readable state. Here, in the writable state, when the signal is at L level, the SW circuit 34 is turned on, and this device connects the bus for directly writing data output from the input buffer circuit 12 to the storage circuit 13, and the
A bus for writing to the latch circuit 16 via the SW circuit 34 is provided. If the S/A circuit 15 is set to a disabled state in this state, the S/A circuit 15 will generate the current i shown in FIG.
1 and i2, power consumption can be reduced.

On the other hand, if the address does not change and the signal changes from the L level to the H level, the device becomes readable as described above, and the output buffer circuit 17 becomes enabled and the SW circuit 34 turns off at the same time. Therefore, the data latched in the latch circuit 16 at the time of writing is outputted to the outside from the I/O terminal 11 via the output buffer circuit 17. That is, when the signal changes from H level to L level as shown in FIG. 9a, an output signal as shown in FIG. 9b appears at the I/O terminal 11, and as shown in FIG. 6b. Such unnecessary signals are not generated.

Therefore, if the input/output circuit of the semiconductor memory device is configured as described above, power consumption during write operation can be reduced, and even if the S/A circuit 15 is disabled, the latch circuit 16 is Since the data already written in the memory circuit 13 has been latched, there is no possibility that unnecessary signals will be generated in the output even when switching to read operation, and this will eliminate noise components. It starts to decrease. Furthermore, when data opposite to the latched data is written and a read operation is subsequently performed, there is no possibility that the data will collide with each other and a large current will flow. This makes it possible to provide a highly reliable semiconductor memory device.

By the way, if the above-mentioned device is of the ATD method as described above, even if it detects a change in and generates a pulse and accesses the memory cell accordingly, the time until the output is delayed, Although there are many complicated problems such as pulse timing, when input data is written into the memory circuit 13 by the input/output circuit, it is directly written to the latch circuit 16.
Since the data is written to, it can be read at very high speed, and there is no need to set the timing strictly.

Although the above embodiment has been explained using a semiconductor memory device as an example, the present invention can also be implemented in other semiconductor devices, and in particular, in the case of a memory device, stored data may be destroyed by noise. This is extremely important because of the Furthermore, the present invention can be applied not only to input/output circuits connected to the above-mentioned I/O terminal 11 but also to input/output circuits that communicate with internal buses.

〔Effect of the invention〕

As described above, according to the present invention, an extremely good input/output circuit of a semiconductor device can be realized which is high speed, low power consumption, and highly reliable, without outputting unnecessary signals when the input/output operation state is switched. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of the input/output circuit of a conventional semiconductor device, FIG. 2 is a circuit diagram showing the configuration of a latch type S/A circuit used in the semiconductor device, and FIG. 3 is a block circuit diagram showing the configuration of the input/output circuit of the semiconductor device. 4 is a waveform diagram for explaining the drawbacks of the conventional latch type S/A circuit used in the above-mentioned latch type S/A circuit. FIG. FIG. 6 is a circuit diagram showing the configuration of a memory cell, FIG. 6 is a waveform diagram showing the output waveform when the operating state of the input/output circuit is changed, and FIG. 7 is an embodiment of the input/output circuit of the semiconductor device according to the present invention. FIG. 8 is a circuit diagram showing the specific configuration of the SW circuit of the above embodiment, and FIG. 9 is a waveform diagram showing the output waveform when switching the operating state of the input/output circuit in the above embodiment. be. 11...I/O terminal, 12...Input buffer circuit, 13...Memory circuit, 14...ATD circuit, 1
5...S/A circuit, 16...Latch circuit, 17...
...output buffer circuit, 18-32...MOS transistor, 33...WTD circuit, 34...SW circuit, 34a...transfer gate.

Claims (1)

[Claims] 1. An input/output terminal that shares input and output, and an input buffer circuit whose input end is connected to the input/output terminal;
It has an output buffer circuit whose output terminal is connected to the input/output terminal, and a latch circuit which is connected to the input terminal of this output buffer circuit, and controls the input state and output state of data according to the input/output switching control signal. In an input/output circuit of a semiconductor device configured to perform switching control, the input/output switching control signal is interposed between the output terminal of the input buffer circuit and the input terminal of the latch circuit, and when the input/output switching control signal is in an input state, the output of the input buffer circuit is directly controlled. 1. An input/output circuit for a semiconductor device, comprising a switch circuit leading to a latch circuit. 2. The input/output circuit for a semiconductor device according to claim 1, wherein the input/output terminal is an input/output terminal of a semiconductor memory.