JPH0612626B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an asynchronous static MOS memory device capable of significantly reducing power consumption due to an internal DC current.

[Background of the Invention]

In an asynchronous static memory device composed of conventional NMOS transistors, an X decoder, a Y decoder, and a predetermined memory cell are selected according to an address signal, and a sense amplifier amplifies information stored in the cell, It is transmitted to the output buffer circuit to obtain the output. Next, when the address changes, the X decoder and Y decoder
Select a cell and read the information stored in that cell,
Get the following output. The shortest cycle time is the same as the output access time.

Further, when the chip is in the selected state, a DC current constantly flows through the X decoder, the Y decoder, the sense amplifier, the output buffer circuit, etc., so that a very large amount of power is consumed. On the other hand, during the writing period, DC currents flow in exactly the same manner, and these DC currents flow regardless of the cycle time.

By the way, recently, there has been used a method of highly integrating a peripheral circuit of a memory device into a CMOS to reduce power consumption, and configuring a memory cell with an NMOS transistor and a high resistance. 1/5 to 1/10 compared to a memory device using only
It has become possible to reduce power consumption. However, even in this case, since the memory cell is composed of the NMOS transistor, the DC current always flows through the memory cell, and the current reaches about half of the total current.

FIG. 1 is a main part configuration diagram showing an example of a conventional static type MOS memory device.

In FIG. 1, 1 is a memory cell group (memory plane), and its unit circuit (memory cell) 2 is composed of NMOS transistors 3, 4, 5, 6 and resistors 7, 8. This memory cell 2 is accessed by the decoder 10 which drives the word line 9, and when the switching MOS transistors 13 and 14 are turned on by a Y decoder (not shown), a pair of information stored inside the cell is output. Then, it appears as a slight potential difference on the data lines 11 and 12, and the switch M
It appears on the common data lines 15 and 16 through the OS transistors 13 and 14.

The minute potential difference appearing on the common data lines 15 and 16 is amplified by the analog sense amplifier 18 and transmitted to the output buffer circuit 19. The MOS transistors 20, 21 and 22, 23 are connected to the data lines 11, 1
It is a load for keeping the 2 and common data lines 15 and 16 at a predetermined potential. Next, at the time of writing, a signal having a pair of high potential differences is obtained at the output terminals 25 and 26 by the data input buffer circuit 24, and this signal is passed through the write switch MOS transistors 27 and 28 to the common data lines 15 and 16. Appearing in, and MO for switch
Data lines 11 and 12 through S transistors 13 and 14
Appears in. Prior to this, potentials are applied to the input terminals for turning on the switching MOS transistors 13, 14 and 27, 28, respectively. Furthermore, the decoder 10
The word line 9 is driven by, so that the potential information on the data lines 11 and 12 is written in the memory cell 2.

In this case, the following DC power consumption occurs.

(1) In the analog-type sense amplifier 18, a DC current always flows in order to amplify an input signal that appears on the common data lines 15 and 16 and has a minute potential difference (sense D
C current).

(2) The memory cell 2 is a flip-flop circuit, and when the MOS transistor 5 is turned on and the MOS transistor 6 is turned off now, the word line 9 driven by the decoder 10 causes the data line load from the power supply voltage Vcc. A DC current flows to the ground voltage Vss through the MOS transistor 20, the data line 11, the MOS transistor 3 of the memory cell 2, and the same 5 (memory cell DC current).
In this case, a DC current will flow in all the memory cells connected to word line 9. That is, since the word line 9 is still set to the selection potential by the word line selection drive circuit 10, a pair of transfer MOs of the plurality of static memory cells 2 connected to one word line 9 are transferred.
Since the S transistors 3 and 4 are in the conductive state, the data line load 20, the data line 11 and the transfer M are transferred from the high potential power supply voltage Vcc.
Since a current flows through the OS transistor 3 to the information storage node (drain of the MOS transistor 5) on the low potential side of the flip-flop circuit of the memory cell 2, a plurality of word lines connected to one word line 9 after the sense amplification is completed. (3) At the time of writing, a high potential difference appears at the output terminals 25 and 26 of the data input buffer circuit 24, and one of them becomes the ground voltage Vss level. Now, the output terminal 25 is Vss
If it is at the level, from the power supply voltage Vcc to the data line load MOS transistor 20, the data line 11, the switch M
D is set to the ground voltage Vss through the OS transistor 13, the common data line 15, and the switch MOS transistor 27.
C current flows (write DC current). Therefore, during the reading, these DC currents flow regardless of the length of the cycle time due to the above (1) and (2). Also,
During writing, write signal by (2) and (3) above
These DC currents flow regardless of the pulse width of (▲ ▼).

[Object of the Invention]

The present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to provide a static semiconductor memory device of low power consumption.

[Outline of Invention]

In order to achieve the above object, the basic configuration of the present invention is arranged at the intersection of the word line (9) and the data line pair (11, 12) and the flip-flop circuit (5, 6, 7, 8). And the source / drain path is connected between the pair of information storage nodes of the flip-flop circuit and the data line pair (11, 12), and the gate thereof is connected to the word line (9). A static memory cell (2) composed of transfer MOS transistors (3, 4) and a pair of data lines connected between the data line pair (11, 12) and the operating potential point (Vcc). Load (20, 21), word line selection drive circuit (10, 60) that drives the word line (9) to a selection potential, and the memory cell read to the data line pair (11, 12)
A semiconductor memory device comprising a sense amplifier (18) for amplifying read data from (2), comprising a signal holding means (6) for holding an output of the sense amplifier (18).
3) is further provided, and the word line selection drive circuit (10, 60) is composed of a CMOS circuit, and in response to a change of the address signal, a predetermined time (T
During the period (A), the word line selection drive circuit (10, 60) drives the word line (9) to the selection potential and controls the sense amplifier (18) to be in the active state. ) Amplify the read data from the memory cell, and after the elapse of the predetermined time (TB), the sense amplifier (18)
Are controlled to an inactive state, and the word line selection drive circuit (10, 16) sets the word line (9) to a non-selection potential to transfer the pair of static memory cells (2). The MOS transistors (3, 4) are made non-conductive to cut off the current from the high-potential operating potential point (Vcc) to the low potential side information storage node of the pair of information storage nodes of the flip-flop circuit. , The word line (9) is set to a non-selection potential and the output of the sense amplifier (18) is set in advance to the signal holding means (6) before the sense amplifier (18) is controlled to an inactive state.
It is characterized in that the read data is obtained from the signal held in the signal holding means (63) after the predetermined time has elapsed.

According to the basic configuration of the present invention, the original purpose can be achieved for the following reasons.

(i) CMOS circuit configuration word line selection drive circuit (10, 60)
After the output of is set to the selection potential or the non-selection potential,
The steady-state current of this CMOS circuit becomes a negligibly small value, and the power consumption of the word line selection drive circuit (10, 60) itself can be reduced.

(ii) After the elapse of a predetermined time from the change of the address signal, the sense amplification by the sense amplifier (18) is completed, and the sense amplifier (18) is controlled to the inactive state.
The useless power consumption of the sense amplifier (18) can be reduced.

(iii) After the elapse of a predetermined time from the change of the address signal, the word line selection drive circuit (10, 60) causes the word line (9)
Is set from the selection potential to the non-selection potential, the word line
Multiple static memory cells connected to (9) (2)
The pair of transfer MOS transistors (3, 4) become non-conductive, and the current from the high potential operating potential point (Vcc) to the information storage node on the low potential side of the flip-flop circuit of the memory cell (2) is cut off. After the completion of the sense amplification, it is possible to reduce unnecessary power consumption of the plurality of memory cells (2) connected to the word line (9).

Further, according to the basic configuration of the present invention, the word line (9) is set to the non-selection potential, and the sense amplifier (18) is set.
The output of the sense amplifier (18) is held in advance in the signal holding means (63) before being controlled to the inactive state, and after a predetermined time has elapsed, the read data is read from the signal held in the signal holding means (63). Since the word line (9) is set to a non-select potential and the sense amplifier (18) is inactivated, the read data from the memory cell disappears from the output of the sense amplifier (18). It is possible to prevent this.

According to a more preferred embodiment of the present invention, the write signal (W
In response to E), the sense amplifier is controlled to the inactive state. Therefore, the power consumption of the sense amplifier 18 can be reduced in the write mode of the semiconductor memory device.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

2 to 5 are logic diagrams of a pulse generator and a pulse collecting circuit showing an embodiment of the present invention, respectively.
A circuit that detects a change in address, generates a clock, and collects them is shown.

FIG. 2 (a) shows a pulse generator (indicated by a dotted line) 50 including a combination of an input / output buffer circuit in which inverters are connected in series and a NAND circuit. When there is a change in the address input level, when the input signal passes through a plurality of inverters, the propagation delay of the signal generated between the inverters is detected by the pulse generator 50, as shown in FIGS. 11 and 12. Pulse signal φP _i is generated. The first
FIG. 1 is a time chart of a read operation according to the present invention,
FIG. 12 is a time chart of the write operation.

The structure of the pulse generator of FIG. 2 (a) is shown in FIG. 2 (b). In FIG. 2 (b), the NAND circuit is formed by using CMOS transistors, but it is of course possible to form it by using NMOS transistors. As shown in FIG. 2 (a), since the output lines 51, 53, 52, 54 of the inverter are the outputs of the inverters connected to the second, fifth, third and sixth inverters respectively, the high level is applied to the input terminal.・ When the level signal “H” is input, “H”,
"L", "L", and "H" are input to the left and right NAND circuits. In this case, PM in the NAND circuit on the left side of FIG.
Since one OS and one NMOS transistor turn on and a high level is output, and in the NAND circuit on the right side, one PMOS and one NMOS transistor turn on and a high level is output to the central NAND circuit, respectively. Both NMOS transistors are turned on and a low level is obtained as the output signal φP _i . When the address signal changes, it becomes a transient level and the output line 5 of the inverter
Two of 1 and 53 or 52 and 54 become high level "H". In this case, since the low level is output from the NAND circuit on the left side or the right side shown in FIG. 2B, the NAND circuit at the center has the NMOS transistor and the PMO.
The S transistors are turned on one by one, and a high level is obtained as the output signal φP _i . Since the transient state in which the address changes occurs only momentarily, the output signal φP _i is
The pulse waveforms are as shown in FIGS. 1 and 12.

The pulse generator shown in FIG. 2 (a) is provided for each address signal input buffer circuit.

In addition, in this embodiment, together with each address signal input buffer circuit, ▲ ▼ (write enable signal)
The input buffer circuit of (1) is also provided with the same pulse generator as in FIG.

As shown in FIG. 3, the output signal .phi.P _i of the pulse generator of the address input buffer circuit, ▲ ▼ collect the output signal .phi.P _i of the pulse generator of the input buffer circuit, is input to the pulse set circuit.

When the pulse signal φP _i is input to the pulse aggregation circuit, the output signal φP becomes low level for a certain period. FIG. 4 shows the case where the pulse collecting circuit of FIG. 3 is composed of CMOS transistors, and FIG. 5 is the same case when it is composed of NMOS transistors (D is a depletion type and E is an enhancement type).

When the pulse signal φP _i is input, the time for which the output signal φP is held at the low level is determined by the transfer constant β _R of the load PMOS transistor 55 and the capacitance of the node 56 shown in FIG. When different address input signals change almost at the same time, the low level time of the output signal φP is held for a long time. The output signal φP resets the control clock of the switch circuit for stopping the operation of each circuit.

In FIG. 4, if no pulse signal φP _i is input and only the chip select signal (▲ ▼) is input.
(Low level), since only the PMOS transistor 55 is turned on, the node 56 becomes high level “H”, turning on the NMOS transistor of the second-stage inverter from the end and turning on the PMOS transistor of the final-stage inverter. As a result, during the period when the pulse signal φP _i is not input, that is, when the address change and the write signal are not input, the output φP of the pulse aggregation circuit is at the high level “H”.
Is. On the other hand, when even one pulse signal φP _i is input, the NMOS transistor is turned on, and the potential of the node 56 is lowered to the low level “L” even though the load PMOS transistor 55 of the first stage is turned on. .
As a result, the PMOS transistor of the second-stage inverter from the last is turned on, the NMOS transistor of the last-stage inverter is turned on, and the output φP is set to low level "L". The output φP of the pulse collection circuit is the eleventh
The waveform is as shown in FIG. The PMOS transistor 57 shown in FIG. 4 is for positive feedback and is for shaping the rising waveform of the node 56. Even if it is configured with NMOS transistors as shown in FIG. 5, the same operation is performed. However, if a CMOS transistor is used, no current flows at all in a stationary state, so that power consumption is very small. Note that the reason why the pulse φP _i from the pulse generator of the input buffer circuit is also added to the input of the pulse aggregation circuit is that the information is read from a predetermined memory cell and then the memory address is changed without changing the address. This is so that the cell can be written. Further, it is possible to write to a predetermined memory cell and then read from the memory cell itself. The output signal φP of this pulse collection circuit is used to control a series of control clock circuits.

FIG. 6 is a logic diagram of a decoder circuit using a control clock showing an embodiment of the present invention, and FIG. 7 is a main part configuration diagram of a memory device using a control clock showing an embodiment of the present invention. Is. Further, FIGS. 8, 9 and 10 are logic diagrams of the control clock circuit used in FIGS. 6 and 7.

In Figure 6, but to transmit the output of the decoder 10 to the word line 9 by the word driver 60, a clock phi _DC
Is low, the NMOS transistor 60 'is turned off and the word line 9 is irrelevant regardless of the output of the decoder 10.
Goes low to suppress the DC current in the memory cell. Decoder 10 and word driver 60 are CMOS
With the configuration, the power consumption is very small in the stationary state.

In FIG. 7, the clock φ _SEN controls the NMOS transistor 18 ′ and the PMOS transistors 30 and 31, and controls the power on / off of the sense amplifier 18 and the precharge of its output terminals 61 and 62. Next, the clock φ _DS is the NMOS transistor 6
3'and PMOS transistors 32 and 33 are controlled,
It controls the on / off of the power of the data store circuit 63 and the open / close switch between the output of the sense amplifier 18 and the input of the output buffer circuit 19. The data
The store circuit 63 holds the information detected by the sense amplifier 18 even after the power of the sense amplifier 18 is turned off, and supplies it to the output buffer circuit 19. If the data store circuit 63 is a flip-flop circuit composed of CMOS transistors, power consumption will be minimal in a stationary state.

Next, the clock φ _TRI is applied to the NMOS transistor 1
9'to control the power of the output buffer circuit 19,
Turn off to control the high impedance state of this output.

Further, the clock φ _CD is generated by the PMOS transistor 22,
23 and the NMOS transistors 27 and 28 are controlled,
Precharging the common data lines 15 and 16 and the output of the data input buffer circuit 24 and the common data line 1
The open / close switch between 5 and 16 is controlled.

Further, the clock φ _DIB is used for the PMOS transistor 2
4'is controlled to turn on / off the power of the data input buffer circuit 24 to control the precharge of the output terminals 25 and 26.

FIG. 11 is a time chart when reading the control clock signal, and FIG. 12 is a time chart when writing the same. In FIG. 11, time TC
Is a read cycle time, time TA is an operation period of a circuit necessary for reading, and time TB is a period of a quiescent (DC operation) state in which only the output buffer circuit 19 and the data store circuit 63 are operating thereafter. is there. Since the power consumption of the time TB is very small and the power consumption of the time TA is constant, the longer the cycle time TC, the longer the time TB, and the smaller the average power consumption of the cycle time.

In FIG. 12, time TC is a period when the write (▲ ▼) signal is at a low level “L” for writing, time TA is an operation period of a circuit required for writing, and time T
B is the period of the stationary (DC operation) state after the writing is completed. The power consumption during the time TB is very small, and the time TA is constant as in the case of reading.
▼ The longer the width of the low level signal, the more time T
B becomes longer, and the average power consumption for writing becomes smaller.

Next, referring to FIGS. 6, 7, and 11, the operation during standby and during reading will be described.

During standby, clocks φ _DC , φ _SEN , φ
_DS , φ _TRI , φ _CD , and φ _WL go low, and only the clock φ _DIB goes high. That is, the word driver 60 shown in FIG. 6, the sense amplifier 18 and the data store circuit 63 shown in FIG. 7 are powered off, the output of the output buffer circuit 19 is brought into a high impedance state, and the data input buffer circuit 24 Output terminals 25 and 2
Precharge 6 Also, the output of the sense amplifier 18 and the common data lines 15 and 16 are precharged. The output of the sense amplifier 18 is the output buffer circuit 1
9 and the output of the data input buffer circuit 24 is disconnected from the common data lines 15 and 16.

Next, at the time of reading, first, the clock φ _TRI becomes high level, and the output buffer circuit 19 is changed from the high impedance output state to the normal buffer state. When the clock φP is changed from the low level to the high level by the clock φP _i , the clock φ _DC is changed to the high level, the word driver 60 is powered on, and the word line 9 is selected by the output of the decoder 10. When the word line 9 starts to be selected, the clock φ _SEN becomes high level, the output terminals 61 and 62 of the sense amplifier 18 are released from precharge, and the sense amplifier 18 is powered on. At this point, the clock φ _DC is at low level,
The output of the sense amplifier 18 is directly connected to the input of the output buffer circuit 19, and in this state, the output buffer circuit 19 provides an output based on the output of the sense amplifier 18. Around the time when the sense amplifier 18 detects correct information and starts transmitting this information to the output buffer circuit 19, the clock φ _DS becomes high level, and this information is held in the data store circuit 63 so that the sense amplifier 18 outputs the information. The output is disconnected from the input of the output buffer circuit 19. At this point, clock φ _DC
Goes low, the word driver 60 powers off, the word line 9 goes low, and the memory
Block the DC current in the cell. At the same time, φ _SEN becomes low level, the sense amplifier 18 is powered off, the sense DC current is blocked, and the output terminals 61 and 6 are
Precharge 2. Clock φ _CD during reading
Is maintained at a low level, and the clock φ _DIB is maintained at a high level. This makes the reading stationary
In the (DC) state (time TB), only the data store circuit 63 and the output buffer circuit 19 are in the DC operating state, and the power consumption is extremely reduced.

Next, the write operation will be described with reference to FIGS. 6, 7, and 12.

At the time of writing, when the write signal (▲ ▼) becomes the low level, the pulse φP _i changes the clock φP from the low level to the high level, and the clock φ _SEN ,
φ _DS and φ _TRI become low level. As a result, the sense amplifier 18 and the data store circuit 63 are powered off, and the output buffer circuit 19 maintains the high impedance output state.

That is, at the time of writing, first, the clock φ _TRI becomes low level, and the output buffer circuit 19 becomes high impedance. When the clock φ _CD goes high, the precharge of the common data lines 15 and 16 is released, and the common data lines 15 and 16 are directly connected to the output of the data input buffer circuit 24. At this time point, since φ _DIB is at the high level, the output of the data input buffer circuit 24 is precharged. Then, when the clock φP is at a high level, the clock φ _DC is at a high level, the word driver 60 is powered-on. The word line 9 selected by the decoder 10
The clock φ _DIB becomes low level when the signal becomes high level, and the data input buffer circuit 24 is powered on. As a result, an output signal appears at the output terminals 25, 26, and the common data lines 15, 16, the data line 11,
The selected memory cell 2 is written through 12.

When the writing to the memory cell is completed, the clock φ
_By setting _WL to a high level and clock φ _CD to a low level to disconnect the common data lines 15 and 16 from the output of the data input buffer circuit 24, the write D
Block C current. At the same time, the common data lines 15 and 1
Precharge 6 Further, the clock φ _{DIB is set} to the high level, and the data input buffer circuit 24 is powered on.
It is turned off and the output terminals 25 and 26 are precharged. Further, the clock φ _{DC is set} to the low level, the word driver 60 is powered off, and the selected word line 9 is set to the low level. This blocks the DC current in memory cell 2. Incidentally, when the clock φP becomes a low level, even at a low level clock phi _WL.

In this way, in the write DC operation state (time TB), the power consumption is extremely reduced because the memory cell write is completed.

Next, the operation of the control clock circuit is shown in FIG.
This will be described with reference to FIG.

FIG. 8 shows the generation logic of the clock φ _DC for controlling the MOS transistor 60 ′ of the word driver 60, and FIG. 9 shows the MOS transistor 18 ′ of the sense amplifier 18,
Clock φ _SEN for controlling 30, 31 and MOS transistors 63 ′, 32, 33 of the data store circuit 63
Shows the clock phi _DS generation logic that controls, Fig. 10, 'the clock phi _TRI for controlling, MOS transistor 24 of the data input buffer circuit 24' MOS Torajisuta 19 of the output buffer circuit 19 clocks for controlling phi
_DIB and switch MO for common data lines 15 and 16
The generation logic of the clock φ _CD for controlling the S transistors 22, 23, 27, 28 and the clock φ _WL for controlling the clock φ _DC is shown. In addition, during chip operation,
When the clock φP goes low, the clock φ _TRI
All clocks except are reset. Clock φ
_{The TRI} is reset by _changing the ▲ ▼ signal or the ▼ signal from the low level to the high level.

First, in FIG. 10, during writing, as shown in FIG. 12, ▲ ▼ is at a low level, clock φP is at a high level, and ▲ ▼ is at a low level, so that it passes through the inverter 81 and the NOR gate 82. Clock φ
_TRI goes low. Further, the high level of the clock φP is the AND gates 86, 89 and the delay circuits 71, 7.
Since it is still high level after passing 2, the clock φ
Both _DIB and φ _WL are at high level. further,
The low level of ▲ ▼ and ▲ ▼ is Noah Gate 8
The clock φ _CD becomes low level by passing through the 3,85 inverter 84. Such a state is
It corresponds to the state of time TB in FIG.

Next, in FIG. 9, at the time of reading, since the clock φP is at the high level and WE is at the high level, the clock φ passed through the NAND gate 77 and the NOR gate 78.
_SEN goes low, and the clock φ _DS passed through the delay circuit 70, the inverter 79, and the AND gate 80 goes high. This state matches the state at time TB in FIG.

Further, in FIG. 8, at the time of reading, the clock φP
Is a high level, the clock φ _WL is a low level, and the clock φ _DS is a high level. Therefore, the same level is held by the OR gate 73, the NAND gate 74 and the inverter 75, and the clock φ is passed through the AND gate 76. _DC
Becomes low level. This state is the time TB in FIG.
It matches the condition of. Thus, in the semiconductor memory device of FIGS. 6 and 7, the actual reading operation time (TA)
Is constant, the longer the cycle time (TC), the lower the average power. Since the sense amplifier 18 is not of the latch type, even if the clocks φ _SEN and φ _DS are activated with a delay, the access time is hardly affected. In addition, the number of clocks required for a complete clock type memory device is 18 or more, whereas the number of clocks required for the circuits of FIGS. 6 and 7 is six, so the occupied area is a complete clock type memory device. Then, while 10% of the chip is required, the present invention requires only 3%. Therefore, in the memory device of the present invention, the layout wiring is simplified, the time sequence of the clock signal is not complicated, and the memory device is simplified.

〔The invention's effect〕

As described above, according to the present invention, the circuit in which the DC current flows is controlled by the internal control clock circuit, so that the power consumption in the stationary state (DC state) is extremely small. Further, since the number of clocks is small, the time sequence is simplified, layout wiring is simplified, and highly reliable memory operation with low power consumption is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional semiconductor memory device, FIG. 2 is a block diagram of a pulse generator used in the present invention, FIGS.
5 and 5 are block diagrams of a pulse set circuit used in the present invention, FIG. 6 is a block diagram of a decoder circuit showing an embodiment of the present invention, and FIG. 7 is a semiconductor memory device showing an embodiment of the present invention. FIG. 8, FIG. 9, FIG. 10 and FIG. 10 are schematic diagrams of the control clock circuit used in FIG. 6 and FIG. 7, respectively, and FIG. 11 and FIG. 3 is a time chart of the clock signal of FIG. 2: memory cell, 9: word line, 10: decoder, 1
1, 12: data line, 15, 16: common data line,
18: sense amplifier, 19: output buffer circuit, 20,
21: Data line load MOS transistor, 22, 23:
Common data line precharge MOS transistor, 2
4: data input buffer circuit, 30, 31: output terminal precharge MOS transistor, 50: pulse generator, 60: word driver, 63: data store circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Osamu Minato 1-280 Higashi Koigokubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Toshio Sasaki 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Tokumasa Yasui 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi Plant (72) Inventor Kotaro Nishimura 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Plant ( 56) References JP-A-54-136239 (JP, A) JP-A-54-161876 (JP, A)

Claims (4)

[Claims] 1. A flip-flop circuit is arranged at an intersection of a word line and a data line pair, and a source / drain path is formed between the pair of information storage nodes of the flip-flop circuit and the data line pair. A static type memory cell connected to the word line and having a pair of transfer MOS transistors connected to the word line, and a pair of data line loads connected between the data line pair and the operating potential point. And a word line selection drive circuit for driving the word line to a selection potential, and a sense amplifier for amplifying read data from the memory cell read to the data line pair. And further comprising signal holding means for holding the output of the sense amplifier, wherein the word line selection drive circuit is a CMOS circuit. In response to a change in the address signal in the read cycle time, the word line selection drive circuit drives the word line to the selected potential during a predetermined period required for the holding operation in the signal holding means from the change. In addition, by controlling the sense amplifier in an active state, the sense amplifier amplifies the read data from the memory cell, and after the path of the predetermined period, the sense amplifier is controlled in an inactive state. The pair of transfer MOS transistors of the static memory cell are made non-conductive by setting the word line to a non-selection potential by the word line selection drive circuit, and the flip-flop is operated from the operation potential point of high potential. The information storage node on the low potential side of the pair of information storage nodes of the circuit. Cut off the current to de, allowed previously retained in said signal holding means said output of said sense amplifiers before the sense amplifier is controlled to be inactive with the word line is set to a non-selection potential,
A semiconductor memory device, wherein read data is obtained from a signal held in the signal holding means after a predetermined period of the read cycle time has elapsed. 2. The semiconductor memory device according to claim 1, wherein the sense amplifier is controlled to an inactive state in response to a write signal in the write mode of the semiconductor memory device. Semiconductor memory device. 3. The semiconductor memory device according to claim 1 or 2, wherein the data input circuit for writing write data to the memory cell is controlled to an inactive state in a read mode of the semiconductor memory device. A semiconductor memory device having the following features. 4. A semiconductor memory device according to any one of claims 1 to 3, wherein the output of the sense amplifier and the signal holding means are:
A semiconductor memory device, wherein an input of an output buffer circuit is connected, and read data is obtained from an output of the output buffer circuit.