JPH01192078A - Semiconductor memory device and level shift circuit - Google Patents

Abstract

PURPOSE:To accelerate the readout operation of data by converting micro level change in the neighborhood of a source voltage set as a pre-charge level for a signal line to the level change in the neighborhood of an operating point which shows the maximum sensitivity in the amplifying operation of a sense amplifier. CONSTITUTION:A level shift circuit 6, etc., included in a readout circuit 4 converts the micro level change in the neighborhood of the source voltage Vdd set as the pre-charge level in the signal line such a bit line or a common data line at the time of reading out the data in a memory cell 1 to the level change in the neighborhood of the operating point which shows the maximum sensitivity in the amplifying operation of the sense amplifier 5. And by supplying such level change to the input terminal of the sense amplifier 5, it is possible to determine the amplifying operation by the sense amplifier 5 without waiting the arrival of the bit line or the common data line large in load capacity in the neighborhood of the operation point of the sense amplifier 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and a sense amplifier drive system therein. The present invention relates to a technology that is effective when applied to speed up read operations and reduce power consumption in static random access memory (static random access memory).

[Prior art]

In an SRAM, a read signal from a memory cell is amplified by a differential amplification type sense amplifier via a bit line pair and a common data line pair, but the operating point at which the sense amplifier has a high amplification amount and high sensitivity is generally Therefore, to confirm the amplification operation by the sense amplifier, it is necessary to wait until the read signal of the selected memory cell reaches above and below the operating point of the sense amplifier on the common data line. .

In addition, in SRAM, a bit line load element or a precharge element is used to restore the potential difference generated between the bit lines due to reading of memory cell data and bring the bit line potential to a level desired for data reading operation before starting data reading. element is required.

If the precharge level of the bit line or common data line given by this bit line load element is near the operating point of the sense amplifier, the time it takes for the input signal of the sense amplifier to reach the operating point can be shortened. Therefore, it is considered desirable for high-speed data reading.

However, in order to set the precharge level of the bit line and common data line to near the operating point of the sense amplifier, that is, to the intermediate level of the power supply voltage, a DC current path is formed in the signal line including the bit line and common data line. If an attempt was made to form such a precharge level by resistor division in the circuit, there was a problem in that the power consumption would significantly increase.

Therefore, one bit line of the complementary bit line pair is supplied with the power supply voltage of the circuit, and the other bit line is charged with the circuit ground potential, respectively, and then the complementary bit line pair is short-circuited. Accordingly, Japanese Patent Application No. 60-58403 proposes a technique for precharging complementary bit line pairs to an intermediate level of the power supply voltage by charge redistribution.

[Problem to be solved by the invention]

However, in the above-described precharging method for bit lines and common data lines, the operation of charging the complementary bit line pair to the power supply voltage and the ground potential, respectively, and the operation of shorting the complementary bit line pair are performed in two steps. Furthermore, during this precharge operation period, it is necessary to wait for word line selection operation to prevent erroneous data from being written to the memory cell. This not only complicates the timing regulations for reading data, but also increases the access time, which limits the ability to read data at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device equipped with a sense amplifier drive system that can achieve high-speed data read operations and low power consumption. Still another object of the present invention is to provide a level shift circuit suitable for a sense amplifier drive system of a semiconductor memory device.

The above and other objects and features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor memory device is configured by providing a level shift circuit that shifts a read signal of a memory cell to a level near the operating point of a sense amplifier and supplies the signal to an input terminal of the sense amplifier.

For example, in the case of a semiconductor memory device including a static memory cell equipped with a load element for statically holding memory cell information, a signal line that can be made conductive to the data input/output terminal of the memory cell is connected to the load element. The precharge element is provided with a precharge element capable of supplying a power supply voltage level at or near the power supply voltage level. At this time, the level shift circuit shifts the voltage level that can be supplied via the precharge element to the signal line that can be made conductive to the data input/output terminal of the memory cell to near the operating point of the sense amplifier.

This level shift circuit includes a current amplifier that uses a series connection node of a current amplification transistor and a current source as an output terminal and changes the output terminal voltage to follow the input voltage of the current amplification transistor.

The configuration may include a power switch that opens a DC current path in response to activation of the sense amplifier.

The level shift circuit also includes a pair of current amplifiers that use a series connection node of a current amplification transistor and a current source as an output terminal and change the output terminal voltage to follow the input voltage of the current amplification transistor. The current amplifying transistor may be formed by coupling load transistors of different conductivity types, and by coupling the control terminals of the load transistors to the output terminals of the other current amplifier. At this time, the current sources included in the pair of current amplifiers can be configured with a current mirror circuit.

[For production]

According to the above-mentioned means, the level shift circuit included in the sense amplifier drive system of a semiconductor memory device uses a power supply voltage that is set as a precharge level on a signal line such as a bit line or a common data line when reading memory cell data. A minute level change in the vicinity is converted into a level change near the operating point at which the sense amplifier's amplification amount is also high in sensitivity, and this is applied to the input terminal of the sense amplifier. As a result, the amplification operation by the sense amplifier can be determined without waiting for the bit line or common data line itself, which has a large load capacitance, to reach the vicinity of the operating point of the sense amplifier, thereby increasing the speed and complexity of the data read operation. achieve.

Furthermore, by keeping the amplitude of the bit line and common data line within the range of the power supply voltage during a data read operation, the bit line precharge operation for the next read cycle can be accelerated, which is necessary for the precharge operation. In addition, it is possible to stabilize the read state in that there is no risk of erroneous writing during reading, and to eliminate strict timing regulations between precharge timing and word line selection timing.

When configuring a level shift circuit including a current amplifier that shifts the output voltage to follow the input voltage of the current amplification transistor, the relationship between the input and output is shaped like a source follower, and the level shift circuit Since it is only necessary to drive a relatively small input capacitance of the sense amplifier, the time required for the level shift operation is substantially negligible. Moreover, as mentioned above, the output load of the level shift circuit is relatively small, so even if the components are set to reduce the through current flowing through the DC current path in this level shift circuit, it is not practical for high-speed level shift operation. No impact.

Furthermore, the power consumption of the level shift circuit itself is made extremely small by the action of the power switch element which is operated in synchronization with the activation of the sense amplifier.

In the level shift circuit, a load transistor having a conductivity type different from that of the current amplifying transistor is coupled to the output terminal of the pair of current amplifiers, and the control terminals of the load transistors are coupled to the output terminal of the other current amplifier. With this configuration, the level difference between the level-shifted complementary output signals obtained at the pair of output terminals by supplying complementary level signals to the input terminals of the pair of current amplifying transistors is determined by the complementary current of the load transistors. Based on the supply operation, the level difference of the complementary input signals is amplified by a difference greater than or equal to that of the complementary input signals, thereby further speeding up the determination of the amplification operation by the sense amplifier.

〔Example〕

FIG. 1 is a circuit diagram showing the main parts of an SRAM that is an embodiment of the present invention.

The SRAM shown in the figure is formed on one semiconductor substrate by a known MO3 integrated circuit manufacturing technique, although this is not particularly limited.

The SRAM of this embodiment has a memory cell array in which a plurality of static memory cells 1 are arranged in a matrix. Memory cell 1 includes, but is not particularly limited to, a P-channel type MO8FETQI and an N-channel type MO8FETQ.
2 and E pair 0MO8 (complementary MO8
) A flip-flop circuit in which the input terminals and output terminals of the inverter circuits IA and 1B are mutually cross-coupled, and the above CM
A pair of N-channel type selection M○5FETQ whose source electrodes are coupled to the output terminals of the OS inverter circuits IA and IB.
3. Consists of Q4. This selection MO8FETQ
3. The drain electrode of Q4 is used as a data input/output terminal of memory cell 1, and the gate electrode thereof is used as a selection terminal of memory cell 1.

The bit line pairs BL, , BL, ~BLn shown in
, BLn on a column-by-column basis, and the selection terminal of the memory cell 1 is coupled on a row-by-row basis with corresponding word lines WL to WLi. Of the word lines WL, ~WLi, a predetermined one corresponding to a row address signal supplied from the outside is driven to a selection level, and its drive is controlled by a row address decoder and a word driver (not shown).
B Lz ~ B Lnt One end of B Ln is an N-channel type MO8FETQ5 and a P-channel type MO3FET.
C as a column switch circuit constituted by Q6
MO5 transfer gate 'I'G1. TG1~TGn
, TGn are commonly connected to the common data line pair CD, CD.

CMOS transfer gate TG, TG, ~TGn
, TGn selectively conducts a predetermined pair of bit lines corresponding to a column address signal supplied from the outside to a common data line pair CD, CD, and outputs a column selection signal C8W□ as a switch control signal for this purpose. ~C3Wn are formed by a column address decoder (not shown).

The bit line pair BL, BL, ~BLn, B
The drain electrode of a P-channel precharge MO5FETQ7 whose source electrode is supplied with the power supply voltage Vdd is coupled to the other end of Ln, and each precharge MO8FE
TQ7 is switch-controlled by a precharge signal φpQ supplied to its gate electrode. The precharge signal φpQ is set to each precharge MO8 by its low level.
The precharge MO8FETQ7, which turns on the FETQ7 and takes the on state, connects the bit line pair B L,, B L1
~B Ln, B Ln, and CMOS transfer gate TG1. The common data line pair CD, CD is charged to approximately the level of the power supply voltage Vdd via TG1 to T Gn, T Gn, and the potential difference generated in the bit line pair and the common data line pair CD, CD due to the previous memory access is reduced. to the same potential.

The write circuit 3 is connected to the common data line pair CD, CD.
The output terminal of the readout circuit 4 and the input terminal of the readout circuit 4 are coupled.

The write circuit 3 drives the common data line pair CD, CD to a predetermined complementary level in accordance with write data Dw supplied from a data buffer (not shown).

The readout circuit 4 is a differential amplifier that amplifies the complementary potential difference, which is a minute level change in the vicinity of the power supply voltage Vdd as a precharge level, which is generated in the common data line pair CD, CD by reading out memory cell data. In the preceding stage, a common data line pair CD, CD is connected by reading memory cell data.
The above-mentioned minute level change near the power supply voltage Vdd that occurs in the sense amplifier 5 is converted into a level change near the operating point at which the amplification amount of the sense amplifier 5 becomes highly sensitive.
A level shift circuit 6 is provided to apply the signal to the input terminal of.

The sense amplifier 5 includes, but is not particularly limited to, a pair of N-channel type input MOs forming a differential pair in which a common connection end of the source electrode is connected to the ground potential Vss via an N-channel type power switch MO8FETQIO serving as a current source.
Has 8FETQII, Ql2, input MO8FETQI
A P-channel type MO8FET Q13.I, which constitutes a current mirror load, is connected to each of the drain electrodes of I and Q12. Ql
4 drain electrodes are connected to each other. P-channel type MO3FETQ13, Ql4 that constitutes the current mirror load
The source electrode of is connected to the power supply voltage Vdd, and the common connection end of these gate electrodes is coupled to the drain electrode of input MO8FETQII.

A pair of input terminals of sense amplifier 5 are input MO8FETQ
I 1. It is used as the gate electrode of Ql2. sense amplifier 5
The output terminal of is used as a combined drain electrode of MO8FETQ12 and Ql4, and is coupled to the input terminal of the output inverter INV. When the amplified output voltage Vout of the sense amplifier 5 reaches a level detectable by the output inverter INV, the output inverter INV provides read data Dr to a data output buffer (not shown). The power switch MO8FETQIO is switch-controlled by a sense amplifier signal φsa supplied to its gate electrode. The high level of the sense amplifier signal φsa turns on the power switch MO8FETQIO to activate the sense amplifier 5. Note that the output terminal of the sense amplifier 5 is set to the power supply voltage V d by the P-channel type MO8FETQ15 in response to the deactivation of the sense amplifier 5.
d It is designed to be charged twice.

When the sense amplifier 5 is activated and a complementary signal is applied to the input terminal, MO8FETQI1. The drain-source current flowing through each Ql2 is different, and as a result,
The drain-source current of MO8FETQII is MO8
The source-drain voltage of MO8FETQ14 is determined by changing the source-drain voltage of FETQ13 and the change in the drain-source current of MO8FETQ12.0For example, if the gate input voltage of MO5FETQII is higher than the gate input voltage of MO8FETQ12, is also high, the drain voltage of MO8FETQ12, which is the amplified output of sense amplifier 5, becomes MO8FETQI
I is made higher than the drain voltage of I. On the contrary, MO8FE
When the gate input voltage of TQ12 is higher than the gate input voltage of MO8FETQII, the drain voltage of MO8FETQI2, which is the amplified output of the sense amplifier 5, is higher than that of MO8FETQII.
It is made lower than the drain voltage of 3FETQII.

In this way, the sense amplifier 5 has a pair of input MO8FETQ
11. Due to the difference in gate input voltage of Q12, MO
8FETQI 1. Ql:H: The resulting current change is MO
Since the change in voltage between the source and drain of MO8FETQ14 is taken out to its output terminal, in order to maximize the amplification degree or amplification sensitivity of sense amplifier 5, MO8FETQ11. Ql2. Ql
3. It is desirable to operate each of Ql4 in the saturation region.

In other words, the differential input level at which the amplification operation of the sense amplifier 5 becomes highly sensitive is approximately the intermediate level of the power supply voltage Vdd (near the voltage V d, d / 2) that allows the pMO8FET to operate in the saturation region. The complementary level is centered around the range of .

The level shift circuit 6 uses a power supply voltage V as a precharge level generated on the common data line pair CD, CD by reading memory cell data.

The sense amplifier 5 detects minute complementary level changes near dd.
The amount of amplification operation is also converted into a level change near the above-mentioned operating point where the sensitivity is high.

That is, the level shift circuit 6 includes, as a basic configuration, a pair of source follower circuits that change the output source potential to follow the input voltage, although this is not particularly limited. Specifically, the level shift circuit 6 includes an N-channel type as a current amplification transistor. The drain electrode of the drive MO8FETQ20°Q21 is coupled to the power supply voltage Vdd, and one of the drive MO8FETQ2
0 is coupled to the common data line CD, and the gate electrode of the other drive MO8FETQ21 is coupled to the common data line CD. And the above drive MO8FETQ20
．． N-channel type MO8FETQ is connected to the source electrode of Q21.
22. Q23 (7) FL/A: / Connects the electrodes and connects them to MO8FETQ22. A common connection end of the gate electrode of MO8FETQ23 is connected to the drain electrode of MO8FETQ22 to form a current mirror circuit, and MO8FETQ22. Connect the source electrode common connection end of Q23 to N-channel power switch MO8FETQ
24 to the ground potential Vss. A pair of input terminals of this level shift circuit 6 are driven by MO8FETQ20.
．． The source electrode of the drive MO8 FET Q20, which is the gate electrode of Q21 and one output terminal of the level shift circuit 6, is the input MO8 which is one input terminal of the sense amplifier 5.
The drive MO8FETQ is connected to the gate electrode of FETQII and is the other output terminal of the level shift circuit 6.
The source electrode 21 is connected to the gate electrode of the input MO8FETQ12, which is the other input terminal of the sense amplifier 5. The power switch MO3FETQ24 is switch-controlled by the sense amplifier signal φSa supplied to its gate electrode, and is activated in synchronization with the sense amplifier 5.

The amount of shift of the output voltage with respect to the input voltage in this level shift circuit 6 is determined by the amount of shift of the output voltage with respect to the input voltage of the driving MO3FETQ20
), a constant determined by the gate oxide film capacitance, carrier movement in the channel, etc., and MO8
It is determined by the drain-source current of FETQ20 (Q21), and in relation to the operating point of the sense amplifier 5, it is set to about 2v to 2.5v in the case of a 5v power supply, for example. Therefore, a minute complementary level change near the power supply voltage Vdd that occurs in the common data line pair CD, CD by reading memory cell data is near the intermediate level of the power supply voltage Vdd, where the amplification amount of the sense amplifier 5 becomes highly sensitive. is converted into a level change near the operating point of
This is supplied to the input terminal of the sense amplifier 5.

In particular, the relationship between the input and output of the level shift circuit 6 is a source follower type.

If the output load capacitance is small, the output response will be extremely fast, and in this embodiment, the output load of the level shift circuit 6 is only the input gate capacitance of the sense amplifier 5, so the time required for the level shift operation by the level shift circuit 6 is The time is so short that it can be virtually ignored. Moreover, when the level shift circuit 6 is activated, a DC current path is formed due to its structure, but since the driving load of the level shift circuit 6 is extremely small as described above, the through current of the DC current path is Even if the level shift circuit 6 is small, it does not substantially affect the high-speed level shift operation, and the level shift circuit 6
The constants of the MOSFETs constituting the circuit are appropriately set.

Next, the data read operation of the SRAM will be explained with reference to the time chart of FIG.

When the address signal supplied from the outside is determined, a selection operation on the column side is performed in response to the address signal at a predetermined timing to synchronized with an external clock (not shown). For example, the column selection signal C5W1 is set to CS
It is set to high level instead of Wn. As a result, the common data line pair CD, CD is connected to the transfer gate TG1.
bit line pair BL1. Conductivity is established with BL. At this time.

The precharge MO8FET Q7 is already controlled to be in an on state by the precharge signal φpC controlled to a low level. Common data line pair CD.

CD is charged to the power supply voltage Vdd together with the bit line pair BLn, BLn via the transfer gate TGn before time 0. The precharge signal φpa is inverted to a high level at time t after the time required to charge the common data lines CD and CD has elapsed.

Next, at time t2, a low-side selection operation is performed in response to the address signal, for example, the word line WLi is driven to the selection level, and the sense amplifier signal φSa is controlled to the high level, so that the level shift circuit 6 and the sense Amplifier 5
is activated.

When the word line WL1 is set to the selection level at time t2, the selection terminal is coupled to the word line WL1, and the data input/output terminal is connected to the bit line pair BL1. Selected MO8FETQ3. of memory cell 1 coupled to BL□. Q4 is turned on, thereby bit line pair BL1. BL1 and the common data line pair CD, CD cause a slight complementary level change from near the power supply voltage according to the information held in the memory cell 1, and the level difference gradually increases with time. For example, when MO8FETQ2 of inverter IA is turned on and MO8FETQ2 of inverter IB is turned off according to the information held in the memory cell 1, one bit line BL1 and common data line CD
The charged charge is gradually discharged through MO8FETQ3 and Q2, and its potential is gradually lowered from the precharge level and the power supply voltage Vdd, and the potential of the other bit line BL and common data line CD is Maintain the precharge level.

When the level shift circuit 6 and the sense amplifier 5 are activated in response to the selection operation of the word line WL□, complementary level changes near the power supply voltage Vdd occurring on the common data lines CD, CD are driven by MO8FETQ20. The level shift circuit 6 received by the gate electrode of Q21 shifts the complementary input levels by about 2v to 2.5v, respectively, to the operating point v at which the amplification operation of the sense amplifier 5 also becomes highly sensitive.
Convert to level change near c and input MO8FETQ11
, given to Q12. As a result, the sense amplifier 5 can be used for bit line pairs with large load capacitance or common data line pairs CD, C.
The amplification output operation can be determined without waiting for the level change of D itself to reach the vicinity of the operating point of the sense amplifier 5.

After the amplified output operation of the sense amplifier 5 is determined, in other words, the amplified output voltage Vout of the sense amplifier 5
is determined relative to the logic threshold level of the output inverter INV, the level changes of the bit line pair BL□, BL, the common data line pair CD, and CD itself reach the vicinity of the operating point of the sense amplifier 5. The timing before (time t
In step a), the selection operation of the word line WL is completed. As a result, bit line pair BL, BL1 and common data line pair CD
.

The level change of CD is kept to a level change near the power supply voltage Vdd.

Then, when the precharge signal φpQ is changed to low level again at time t4 at a predetermined timing synchronized with an external clock (not shown), the bit line pair BL, BL
1 and common data line pair CD.

The CD starts charging to the power supply voltage Vdd by the action of the precharge MO8FET Q7, and then at time t, the sense amplifier signal φSa is changed to low level, the sense amplifier 5 and the level shift circuit 6 are inactivated, and the above-mentioned By controlling the MO3FET Q15 to be in the on state, the output voltage Vout of the sense amplifier 5 is initialized to a high level to prepare for operation for the next memory cycle.

FIG. 3 is a circuit diagram showing an example of a level shift circuit capable of magnifying and outputting complementary changes in input voltage, and the level shift circuit 7 shown in the same figure is the level shift circuit 7 in the SRAM of FIG. Samurai can be used instead of 6.

The level shift circuit 7 shown in FIG. 3 is based on a pair of source follower circuits that make the output source potential follow the input voltage, and similarly to the level shift circuit 6 shown in FIG. Channel type drive MO8FETQ20
．． Q21, N-channel type MO3FET Q22. which constitutes a current mirror circuit. Q23 and an N-channel power switch MO8FET Q24, and the drive MO8FET Q24 is also connected to the output terminal of each source follower circuit.
Q20. Q21 is a P-channel type load MO8FET Q25. which has a different conductivity type. The drain electrode of Q26 is coupled together, and the gate electrodes of loads MO8FE'rQ25 and Q26 are coupled to the output terminal of the other source follower circuit. In addition, the above load MO8FETQ25. Q
The transconductance of 26 is the driving MO8FETQ20.
It is relatively small compared to Q21.

The level shift circuit 7 in FIG. 3 is the level shift circuit 6 described above.
When replaced by the memory cell data read-out driving MO8FETQ20. Q21 (7) When a small complementary level change near the power supply voltage Vdd is applied to the gate electrode via the common data lines CD, CD, this change will affect the amplification operation of the sense amplifier 5 similarly to the level shift circuit 6 above. is also converted into a level change near the intermediate level of the power supply voltage Vdd, which has high sensitivity, and this is transferred to the pair of output terminals Pout.
□, Pout, is applied to the input terminal of the sense amplifier 5, but in particular, the potential difference between the complementary outputs is the load MO8.
FETQ25. Due to the action of Q26, the potential difference between complementary inputs tends to be expanded over time. That is, the load MO8FETQ25, Q26 is the drive MO8FE
TQ20. Complementary changes in the on-resistance of Q21 serve to increase changes in the current flowing through each source follower circuit based on the output voltage of the other source follower circuit.

For example, as shown in FIG. 4, which corresponds to a portion of FIG. When the load is increased with %08F, the gate electrode is coupled to the output terminal Pout1 whose level is relatively low.
The amount of current supplied to the other output terminal Pout by the ETQ26 is gradually increased, and the output level of the output terminal Pout2 is gradually increased. On the other hand, a gate electrode is connected to the output terminal Pout2 whose level is relatively gradually increased. , is connected to the output terminal Po by the load MO8FETQ25.
The amount of current supplied to the UT works is gradually decreasing.

The water is reduced or the load MO8FETQ25 itself is cut off, and the output level of the output terminal Pout1 is gradually lowered in accordance with the gate input voltage of the drive MO8FETQ20. As a result, the change in the output of the level shift circuit 7 in response to the change in the input is shifted as shown by the solid line with respect to the two-dot chain line showing the change in the high level side output of the level shift circuit 6 in FIG. Therefore, the level shift circuit 7 can obtain a complementary shift output by gradually increasing the level difference between the complementary input voltages, thereby further speeding up the determination of the amplification operation by the sense amplifier 5.

According to the above embodiment, the following effects can be obtained.

(1) Level shift circuit 6 included in readout circuit 4.
7 is highly sensitive to minute level changes near the power supply voltage Vdd, which is the precharge level in signal lines such as bit lines and common data lines, when reading memory cell data. By converting it into a level change near the operating point and applying it to the input terminal of the sense amplifier 5, it is possible for bit lines and common data lines with large load capacitance to reach near the operating point of the sense amplifier 5. The amplification operation by the sense amplifier 5 can be determined without having to use the sense amplifier 5.

(2) The level shift circuits 6 and 7, which include current amplifiers that shift the output voltage to follow the input voltages of the driving MO8FETs Q20'' and Q21, have a source follower type relationship between their inputs and outputs. In addition, since the level shift circuits 6 and 7 only need to drive a relatively small input gate capacitance of the sense amplifier 5, the time required for the level shift operation is substantially negligibly short.

Therefore, the level shift circuits 6 and 7 can instantaneously convert a minute level change near the power supply voltage Vdd in the bit line pair to a level near the operating point of the sense amplifier 5.

(3) The word line selection operation can be completed without the bit line or common data line having a large load capacitance reaching the vicinity of the operating point of the sense amplifier 5.
The amplitude of the bit line and common data line in the data read operation can be kept at a change closer to the power supply voltage Vdd, and the precharging operation of the bit line and common data line can be accelerated.

(4) The above effects (1), (2), and (3) make it possible to significantly speed up data read operations.

(5) Since the sense amplifier 5 can immediately detect minute level changes in the vicinity of the power supply voltage Vdd of the bit line pair through the level shift circuit 6 or 7, the sense amplifier 5 can simply detect a minute level change near the power supply voltage Vdd of the bit line pair and the common data line pair. A configuration for precharging to the power supply voltage Vdd can be adopted, and the circuit configuration for precharging can be simplified.

(6) Since the amplitude of the bit line and common data line during data read operation can be kept within the range of the power supply voltage, the power consumption required for precharging the bit line and common data line is reduced. can do.

(7) Since the output load of the level shift circuits 6 and 7 is a relatively small load such as the input gate capacitance of the sense amplifier 5, the through current flowing in the DC current path in the level shift circuit 6°7 is reduced. Even if the constituent elements are set in this manner, the high speed of the level shift operation is not substantially affected.Moreover, the level shift circuit 6, The power consumption of 7 itself can be made extremely small.

(8) From the effects (6) and (7) above, compared to the slight increase in power consumption due to providing the level shift circuit 6 or 7, the power required for precharging the bit line pair and common data line pair is Since consumption is greatly reduced, SRA
Lower power consumption can be achieved for M as a whole.

(9) Since the level changes of the bit line and common data line in the data read operation are kept close to the power supply voltage Vdd as the precharge level, even if the word line selection timing and the precharge timing overlap, the memory cell 1 There is no risk of erroneous writing to the data, the read state can be stabilized, and strict timing regulations between the precharge timing and the word line selection timing can be eliminated.

For example, in FIG. 2, the word line selection operation may be performed before time t, which is the timing at which precharging ends, and further in synchronization with the selection operation of the bit line pair by the column selection signal. .

(10) As in the level shift circuit 7 shown in FIG. 3, the output terminals of the pair of source four circuits are connected to the drive MO8FETQ20. Q21 is a load MO8FET Q25. which has a different conductivity type. Q26 and the load M
O8FETQ25. When this is constructed by coupling the gate electrodes of Q26 to the output terminals of the other source follower circuit, a pair of drive MO8FETs Q20. Q21(7) The level difference between the level-shifted complementary output signals obtained at the pair of output terminals by supplying complementary level signals to the gate electrodes is determined by the load MO8FETQ25. Q2
Based on the complementary current supply operations of the sense amplifiers 6 and 6, the difference is expanded to be greater than the level difference of the complementary input signals, thereby making it possible to further speed up the determination of the amplification operation by the sense amplifier 5.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various modifications can be made without departing from the gist thereof.

For example, the sense amplifier is not limited to one stage of differential amplifier circuits that obtain a single-ended output, but may connect such differential amplifier circuits in series or parallel, or may employ other circuit formats. Furthermore, another precharge element that is switch-controlled in synchronization with the precharge element provided in the bit line pair may be provided in the common data line pair.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to an SRAM configured with an MO8 integrated circuit, which is the field of application that formed the background of the invention.
The present invention is not limited to this, but is a dynamic RA in which a level shift circuit is provided at the input stage of the main amplifier.
It can be widely applied to M and various other semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

When reading memory cell data, the level shift circuit handles minute level changes near the power supply voltage, which is used as a precharge level for signal lines such as bit lines and common data lines. By converting the level change to a level change near the operating point where the sensitivity is high and applying it to the input terminal of the sense amplifier, it is possible to prevent bit lines and common data lines with large load capacitance from reaching near the operating point of the sense amplifier. It is possible to determine the amplification operation by the sense amplifier without having to use the sense amplifier, thereby achieving high-speed data read operation.

Moreover, the level shift circuit that includes a current amplifier that shifts the output voltage to follow the input voltage of the current amplification transistor has a source follower type relationship between its input and output, and the level shift circuit Since it is only necessary to drive a relatively small input capacitance of the sense amplifier, the time required for the level shift operation is substantially negligible. Therefore, the level shift circuit can instantaneously convert minute level changes near the power supply voltage that occur in signal lines such as bit line pairs and common data line pairs by selecting memory cells to a level near the operating point of the sense amplifier. Can be done.

Furthermore, the word line selection operation can be completed without the signal line with a large load capacitance connected to the memory cell reaching the vicinity of the operating point of the sense amplifier, thereby reducing the amplitude of the signal line in the data read operation. can be kept at a change closer to the power supply voltage, making it possible to speed up the precharging operation of signal lines such as bit lines and common data lines. Moreover, the amplitude of signal lines such as bit lines and common data lines during data read operations can be kept within the range of the power supply voltage.
The power consumption required for the precharge operation of the signal line can be reduced.

In addition, the sense amplifier can immediately detect minute level changes near the power supply voltage when reading memory cell data through a level shift circuit, so it simply connects signal lines such as bit line pairs and common data line pairs. A configuration that precharges the power supply voltage can be adopted,
The circuit configuration for precharging can be simplified.

Furthermore, since the output load of the level shift circuit is a relatively small load such as the input capacitance of a sense amplifier, the components are set to minimize the through current flowing through the DC current path in this level shift circuit. However, the power consumption of the level shift circuit itself can be minimized by the action of the power switch element, which operates in synchronization with the activation of the sense amplifier. . Therefore, compared to the slight increase in power consumption caused by providing a level shift circuit, the power consumption required for precharging signal lines such as bit line pairs and common data line pairs can be greatly reduced as described above. Therefore, it is possible to achieve lower power consumption of the semiconductor memory device as a whole.

In addition, since the level change in the memory cell data read signal line is limited to a change closer to the power supply voltage as the precharge level, there is no risk of erroneous writing to the memory cell even if the word line selection timing and the precharge timing overlap. Therefore, the read state can be stabilized, and strict timing regulations between the precharge timing and the word line selection timing can be eliminated.

In a level shift circuit including a pair of current amplifiers that use a series connection node of a current amplification transistor and a current source as an output terminal and change the output terminal voltage to follow the input voltage of the current amplification transistor, the output terminal of each current amplifier is connected to the above-mentioned output terminal. A current amplification transistor is a load transistor with a different conductivity type.

and the control terminals of the load transistors are coupled to the output terminals of the other current amplifier,
The level difference between the level-shifted complementary output signals obtained at the pair of output terminals by supplying complementary level signals to the input terminals of the pair of current amplifying transistors is based on the complementary current supply operation of the load transistors. The difference is expanded to a level difference greater than or equal to the level difference of the complementary input signals, thereby making it possible to further speed up the determination of the amplification operation by the sense amplifier.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts of an SRAM that is an embodiment of the present invention. FIG. 2 is a time chart for explaining the data read operation in the SRAM of FIG. 1, FIG. 3 is a circuit diagram showing an example of a level shift circuit that can magnify and output complementary changes in input voltage, and FIG. This figure is an explanatory diagram showing the relationship between input and output in the level shift circuit of FIG. 3. 1...Memory cell, 4...Reading circuit, 5...
Sense amplifier, 6, 7... Level shift circuit, BL□
. B L, ~B Ln, B Ln-bit line pair, WL engineering~WLi... word line, CD, CD... common data line pair, Q7-... precharge MO5FET, Q2
0. Q21... Drive MO8FET, Q24... Power switch MOSFET, Q25. Q26-...Load M
O8FET, φpc... precharge signal, φsa・
...Sense amplifier signal. Figure 1 Figure 2 Figure 3, Figure 4 Pou↑1

Claims (1)

[Claims] 1. In a semiconductor memory device in which a read signal of a memory cell is amplified by a sense amplifier and output, the read signal of a memory cell is shifted to a level near the operating point of the sense amplifier and input to the sense amplifier. A semiconductor memory device comprising a level shift circuit applied to a terminal. 2. It includes a static memory cell equipped with a load element for statically holding memory cell information, and the signal line that can be made conductive to the data input/output terminal of this memory cell has a power supply voltage level applied to the load element or its level. 2. The semiconductor memory device according to claim 1, wherein a neighboring level can be supplied via a precharge element. 3. The semiconductor memory device according to claim 2, further comprising a level shift circuit that shifts the voltage level that can be supplied to the signal line via the precharge element to near the operating point of the sense amplifier. 4. A current amplifier that uses a series connection node of a current amplification transistor and a current source as an output terminal and changes the output terminal voltage to follow the input voltage of the current amplification transistor, and a DC current path in response to activation of the sense amplifier. 2. The semiconductor memory device according to claim 1, further comprising a level shift circuit comprising a power switch that opens. 5. A pair of current amplifiers that use a series connection node of a current amplification transistor and a current source as an output terminal and change the output terminal voltage to follow the input voltage of the current amplification transistor, each of which has the current amplification transistor and the current amplification transistor connected to the output terminal of each current amplifier. connects load transistors of different conductivity types, and connects the control terminals of the load transistors to the output terminals of the other current amplifier, and signals of complementary levels are supplied to the input terminals of the pair of current amplifying transistors. A level shift circuit configured to expand level-shifted complementary levels obtained at a pair of output terminals based on complementary current supply operations of the load transistors. 6. The level shift circuit according to claim 5, wherein the current sources included in the pair of current amplifiers constitute a current mirror circuit. 7. In a semiconductor memory device in which a read signal from a memory cell is amplified by a sense amplifier and output, the patent claim shifts the read signal from a memory cell to a level near the operating point of the sense amplifier and supplies it to the input terminal of the sense amplifier. A semiconductor memory device comprising the level shift circuit according to item 5 or 6.