JPH03102442A - Memory access circuit - Google Patents

Abstract

PURPOSE:To prevent the miswriting operations, the breakage of stored data, etc., by setting a standby memory main body in a non-selection state after a writing process. CONSTITUTION:The enable signal held by a 2nd storage circuit 208 is initialized into an inactive state by the pulse outputted from a delay circuit 210. Then the enable signal supplied to a standby memory main body 205 is set in an inactive state and the body 205 is set in a non-selection state respectively. When the address signal supplied to the body 205 changes synchronously with the pulse, a chip enable signal becomes active and the body 205 is set in a selection state to receive a writing operation. As a result, an address never changes as long as the body 205 is kept in a selection state. Thus it is possible to evade the miswriting operations, the breakage of stored data, etc., due to the address change.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to, for example, data flowing in synchronization with pulses,
The present invention relates to a memory access circuit for a data flow system in which processing is performed as data moves.

[Conventional Technology] FIG. 3 shows a conventional example of a memory access circuit for a data flow type system.

In the figure, 203 and 204 are vibe line registers, 205 is a memory main body, and 208 is an address decoder.

Bucket I/human force line 21 is in the vibration line register 203.
2 are connected. This includes information such as data required for memory access, address signals, read/write flags, etc.
A parallel bit string that propagates in synchronization with a pulse is called a packet.

The write data output from the vibe line register 203 is sent to the memory main body 20 via the write data line 227.
The read/write flag is supplied to the read/write flag line 226 and is also output from the vibe line register 203.
The data is supplied to the memory main body 205 via.

A part of the address signal output from the vibe line l/register 203 is sent to the memory main body 20 via the address line 223.
5, and a part of the address signal is also supplied to the address decoder 206 via the address line 224, and the output of this address decoder 206 is supplied to the memory main body 205 as a chip enable signal via the chip enable line 225. be done.

A portion of bucket 1, whose contents are not changed by memory access and is output from the vibe line register 203, is
It is supplied to the vibe line register 204 via the bucket 1 transfer line 222.

Read data from the memory main body 205 is supplied to the vibe line register 204 via a read data line 228. A packet output line 214 is connected to the vibe line register 204.

Further, 201 and 202 are transfer control circuits that control pulse propagation, and a pulse human power line 211 is connected to this transfer control circuit 201. When a pulse is supplied to the transfer control circuit 201, a write pulse is immediately supplied to the pipeline register 203, and a pulse is supplied to the transfer control circuit 202 after a certain period of time. When a pulse is supplied to the transfer control circuit 202, a write pulse is immediately supplied to the pipeline register 204, and a pulse is output to the pulse output line 213 after a certain period of time.

The above-mentioned vibe line registers 203 and 204 hold the data on the input line and simultaneously output it when a write pulse is supplied.

Further, the memory main body 205 is configured to operate as follows.

When the read/write flag from the read/write flag line 226 is set to a read value and the chip enable signal from the address decoder 206 becomes active,
A read operation is performed in the memo tree 205, and
- Data at the address specified by the address signal from the address line 223 is output to the read data line 228.

When the read/write flag from the read/write flag line 226 is set to the write value ζ and the chip enable signal from the address decoder 206 becomes active,
A write operation is performed in the memory main standby 205, and write data from the write data line 227 is written to the address specified by the address signal from the address line 223.

The data on the read data line 228 has the same value as the data on the write data line 227 regardless of the state of the chip enable signal.

Note that when the chip enable signal is not active, the memory main body 205
becomes unselected and the stored contents are retained.

Consider the case where data is read from the memory main body 205 in the above configuration.

A packet with a read value set in the read/write flag is supplied to the packet power line 212, and a pulse is supplied to the pulse input line 211.

As a result, a write pulse is supplied from the transfer control circuit 201 to the pipeline register 203i, and the packet supplied from the packet power line 212 is held and outputted to the vibe line register 203. Then, after a certain period of time, a pulse is supplied from the transfer control circuit 201 to the transfer control circuit 202.

During this time, the read/write flag from the read/write flag line 226, the address signal from the address lines 223 and 224,
The write data from the write data line 227 is stabilized at the contents of bucket 1, a read operation is performed in the memory body 205, and the read data is output to the read data line 228.

When a pulse is supplied from the transfer jl/J# circuit 201 to the transfer control circuit 202, a write pulse is supplied from the transfer control circuit 202 to the vibe line register 204.
28 and the packet transfer line 222 are held and output to the packet output line 214. Then, after a certain period of time, a pulse is output from the transfer control circuit 202 to the pulse output line 213.

In this way, a series of read processing is executed.

Also when writing to the memory body 205,
By setting a write value to the read/write flag of the packet supplied to the packet 1 human power line 212, the write process is performed in the same manner as the series of operations of the read process described above.

[Section H that the invention seeks to solve] However, the memory access circuit of the example shown in FIG. 3 has the following problems.

First, the first bucket 1 is closed and the write bucket 1 is sent to the memory access circuit of the example shown in FIG. When a series of write processing is performed and a pulse is output from the transfer control circuit 202 to the pulse output line 213, this memory access circuit returns to the standby state, but at this time, the first The contents of the packet are retained, and the data continues to be supplied to the memory main body 205. That is, it is in a standby state while being supplied with a write flag from the read/write flag line 226 and a chip enable signal in an active state from the chip enable line 225.

In this state, close the second bucket I and connect the address line 223.
Only the address signal supplied to the memory body 205 through the memory body 205 causes the write bucket 1 to flow, which is different from the first bucket 1.

Here, attention will be paid to changes in the output data when the contents held in the vibe line register 203 are updated to the contents of the second bucket 1 based on the pulses supplied from the transfer control circuit 201.

The omitted read flag remains unchanged as it is written.

Further, the chip enable signal remains active and unchanged. That is, when viewed from the memory main body 205,
Only the address signal changes while the read/write flag and the chip enable signal remain stable in the write and active states, respectively.

Considering the operating characteristics of the memory main body 205 and whether all bits 1 of the address line 223 are changed at the same time, this may lead to erroneous writing or destruction of stored data.

4A shows the address signal from the address line 223, B shows the read/write flag from the read/write flag line 226, and C shows the chip enable signal from the chip enable line 225. The above-mentioned problem arises at the point in time to when only the value changes.

Therefore, it is an object of the present invention to provide a memory access circuit that can perform stable writing.

[Means for Solving the Problems] The present invention includes a first storage circuit that holds write data and address signals supplied to the memory main body in synchronization with pulses, and an enable signal supplied to the memory main body that holds write data and address signals supplied to the memory main body in synchronization with the pulses. A second memory circuit that holds the pulse in synchronization with the pulse and has an initialization function, and a delay circuit that delays the pulse for a certain period of time.

The present invention is characterized in that the enable signal held in the second storage circuit is initialized to an inactive state by a pulse output from the delay circuit.

[Operation] In the above configuration, the enable signal supplied to the standby memory main body 205 becomes inactive, and the memory main body 205 is placed in a non-selected state. Then, when the address signal supplied to the memory main body 205 changes in synchronization with the pulse, the chip enable signal becomes active, and the memory main body 205 becomes a selected state and writing is performed. Therefore, the address does not change when the memory main body 205 is in the selected state, and erroneous writing and destruction of stored data caused by this are avoided.

[Embodiment] Hereinafter, one embodiment of the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, a packet power line 212 is connected to a pipeline register 207. pipeline register 20
The write data output from 7 is the write data line 2.
The read/write flag output from the vibe line register 207 is supplied to the pipeline register 203 via the read/write flag line 230.

Vibration line register 20? The part of bucket 1 whose contents do not change due to memory access, which is output by
It is supplied to the pipeline register 203 via the bucket 1 transfer line 231.

A part of the address signal output from the vibe line 1 register 207 is supplied to the address decoder 206 via the address line 224. This 71・res decoder 20
The output of No. 6 is supplied to No. 1 resistor 20 via chip enable line 232. The register 208 is supplied with a positive pulse output from the transfer control circuit '#I201. When the write pulse is not supplied, the register 20811 holds the data on the input line and outputs it at the same time. The output of this 1-no-sister 208 is sent to the memory main body 20 via a chip enable line 225.
5 as a chip enable signal.

Further, the pulse input line 211 is connected to the transfer control circuit '#i2 09
(This is connected. When a pulse is supplied to this transfer control circuit 209, a write pulse is immediately supplied to the vibration line register 207, and a pulse is supplied to the transfer control circuit 201 after a fixed time. When the register 207 is supplied with a write pulse, the input line -L
data is held and output at the same time.

Further, the write pulse output from the transfer control circuit 201 is supplied to the delay circuit 210. This delay circuit 210
The delay amount is set to be shorter than the input interval of bucket I and longer than the time required for memory access.

The read/write flag output from the vibe line register 203 is supplied to the delay circuit 210 as a control signal. This delay circuit 210 does not output the pulse input from the transfer control circuit 201 when the read/write flag is set to read, and on the other hand, when the read/write flag indicates write, the pulse input from the transfer control circuit 201 is delayed and output. .

The pulse output from the delay circuit 210 is supplied to the above-mentioned resistor 208 as an initialization pulse. When the initialization pulse is supplied, the output of the resistor 20B, which is supplied to the memory main body 205 as a chip enable signal via the chip enable line 225, is initialized to an inactive state.

The main body is constructed as described above, and the rest is constructed in the same manner as the example in FIG.

The operation of this example will be explained below. First, the memory body 205
Consider the case where reading is performed.

A packet whose read/write flag is set to the value of "read" is supplied to the packet power line 212, and at the same time, the pulse input line 211t is supplied.

As a result, a write pulse is supplied from the transfer control circuit 209 to the pipeline register 207, and the bucket 1 supplied from the packet power line 212 is held and outputted to the vibe line register 207. Then, after a certain period of time, a pulse is supplied from the transfer control circuit 209 to the transfer control circuit 201.

Transfer control circuit 201 and vibe line register 203
A similar operation is performed for a stage composed of
The bucket I is held and output to the vibration line I no register 203. Then, after a certain period of time, the transfer control circuit 202
A pulse is supplied to the

Here, the output of the address decoder 206 is held and output to the register 208 by a write pulse similar to that of the pipeline l register 203.

Until the pulse is supplied to the transfer control circuit 202,
Read/write flag from read/write flag line 226, address signal from address line 223, write data line 22
The write data from 7 becomes stable in the packet contents, and becomes stable at the value ζJ active on the chip enable 13 - 14 line 225, and a read operation is performed in the memory main body 205, and the read data line 228 becomes stable. The read data is output.

In this case, the write pulse supplied from the transfer control circuit 201 to the delay circuit 210 is not output from the delay circuit 210 because the read/write flag has been read, and the output of the register 208 is not set to 11;

When the transfer control circuit 201 supplies a pulse to the transfer control circuit 202, the transfer control circuit 1202 supplies a write pulse to the vibe line register 204, and the vibe line register 204 receives ζJ and the read data line 228.
The data supplied from the packet 1 and the transfer line 222 are held, and are outputted to the bucket I and the output line 214ζ. After a certain period of time, the transfer control circuit 202 outputs a pulse of 1! A pulse is output to u2 1 3.

In this way, a series of read processing is executed.

15- Next, consider the case of writing to the memory body 205.

A packet with a write value set in the read/write flag is supplied to the packet human power line 212, and a pulse is supplied to the pulse human power line vA211.

Then, through a series of operations similar to the reading described above,
The packet is held in the pipeline register 203 and output.

Until the pulse is supplied to the transfer control circuit 202,
Read/write flag from read/write flag line 226, address signal from address line 223, write data line 22
The value of the write data from 7 is stabilized to the contents of bucket I, and the value on the chip enable line 225 is stabilized to the active state, and a write operation is performed in the memory body 205.

In this case, the write pulse supplied from the transfer control circuit 201 to the delay circuit 210 is sent to the delay circuit 210 after a certain period of time because the read/write flag is the omitted value.
It is output from As a result, the output of the 16 register 208 is initialized, and the output of the memory main body 208 is initialized.
The chip enable signal supplied to memory 205 becomes inactive, and the memory main body 205 becomes non-selected. The read data line 228 is connected to the write data line 2.
The same data as 27 is output.

After the pulse is supplied to the transfer control circuit 202, operations similar to reading are performed, and a series of write processing is executed.

Here, the operation of continuous write processing will be explained.

First, when the first bucket 1 is passed through the memory access circuit of this example, a series of write operations is performed, and when a pulse is output to the pulse output line 213, the memory access circuit returns to the standby state.

At this time, the vibe line register 203 holds the contents of the first packet, and the value continues to be supplied to the memory main body 205. However, Chitsubu enable line 225
The chip enable signal from is inactive due to the initialization pulse from delay circuit 210.

Therefore, the read/write flag is written and the chip enable signal is inactive and on standby.

Next, as a second packet, only the address signal supplied to the memory main body 205 via the address line 223 is sent to the first packet.
A write packet different from bucket 1 is sent.

Here, the vibration line register 203 and the register 2
Changes in output data until the contents held in 08 are updated to the contents of the second bucket 1 based on the pulses supplied from the transfer control circuit 201, and the output signal of the register 208 is initialized. Focus on

The read/write flag remains unchanged as it is written.

Also, the chip enable signal is a!・The A/I/Res signal supplied from the reply line 223 to the memory main body 205 is the second
When the content of the packet changes, the state changes from inactive to active, and then returns to inactive after a certain period of time.

When viewed from the memory main body 205, during standby, the bucket enable signal is inactive, so it is in a non-selected state, and when the second bucket 1 reaches the pipeline register 203 and register 20B. At 71
- As the address changes, the chip enable becomes active and writing is performed, and as the chip enable signal returns to the inactive state again, the state returns to the non-selected state.

That is, in the write operation, the memo+) tree body 205
The address does not change while remaining in the selected state, and moves from the non-selected state to the selected state through a change of 71-res.

2A shows the address signal from the address line 223, B shows the read/write flag from the read/write flag line 226, C shows the initialization pulse supplied to the register 208 from the delay circuit 210, and D shows the chip enable signal. The chip enable signal from line 225 is shown, and the chip enable signal changes from an inactive state to an active state at the time to when the A1 address signal changes.

In this way, according to this example, in the write operation for -19 to the memory main body 205, the address does not change while the memory main body 205 is in the selected state, and there is no possibility of erroneous writing or stored data due to address changes in the selected state. Destruction, etc. of the equipment can be avoided.

[Effects of the Invention] As explained above, according to the present invention, the standby memory main body is placed in a non-selected state after the writing process.
The address does not change while the memory body is in the selected state and write is specified, and erroneous writing and destruction of stored data can be avoided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a configuration diagram of a conventional example, and FIG. 4 is an explanatory diagram of its operation. 201, 202. 209 ... Transfer control circuit 203, 204 2 0 7 = 20 - 2 2 2, 2 2 3, 2 2 5, 2 2 6, 2 27, 205 ・ 206 ・ 208 ・ 210 ・ 2 1 1 ◆ 2 1 2・ 2 1 3 ● 2 1 4 ◆ 2 3 1 ・ 2 2 4 ● 2 3 2 ◆ 230 ● 2 2 9 ・ 2 2 8 ◆ ・Vibration register・Memory body・Address decoder・Register・Delay circuit・Pulse input line・Packet input line ・Pulse output line ・Packet output line ・Packet transfer line ・Address line ・Chip enable line ・Read/write flag line ・Write data line ・Read data line

Claims (1)

[Claims] (1) A first storage circuit that holds the write data and address signal supplied to the memory main body in synchronization with the pulse; and a first storage circuit that holds the enable signal supplied to the memory main body in synchronization with the pulse and initializes it. a second memory circuit having a function, and a delay circuit that delays the pulse for a certain period of time, and initializes the enable signal held in the second memory circuit to an inactive state by the pulse output from the delay circuit. A memory access circuit characterized by: