JPH07154236A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the power consumption by providing a 2nd tri-state gate controlled by an output signal of a detection circuit to a latch circuit. CONSTITUTION:A signal through an internal bus 60 is inputted to buffer gates 50, 51 and an inverter 31, an output of the inverter 31 is inputted to a PMOS transistor(TR) 412 and an NMOS 412 of a clocked inverter 40 and an output of the clocked inverter 40 is outputted to an internal bus 60. Then an output of 3-state gates 10-12 whose output state is controlled by control signals 20-22 respectively is outputted to the internal bus 60, and the control signals 20-22 are inputted to a NOR gate 70, its output is inputted to an NMOS TR 422 in the clocked inverter 40 and an inverter 30 and an output of the inverter 30 is inputted to a PMOS TR 411 of the clocked inverter 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a master slice type semiconductor integrated circuit device having an internal bus in which outputs of a plurality of 3-state gates are connected to one signal line. .

[0002]

2. Description of the Related Art An example of an internal bus of a conventional semiconductor integrated circuit device is shown in FIG. 2 (Japanese Patent Laid-Open No. 63-84316).
, The signal on the internal bus 60 is input to the buffer gates 50 and 51. In addition, the control signal 20,
The outputs of the 3-state gates 10, 11 and 12 whose output states are controlled by 21 and 22 are output to the internal bus 60. In addition, P-channel MOS
The source of the transistor 411 is connected to the power supply VDD, the drain is connected to the internal bus 60, and the gate is connected to the ground.
Here, the on resistance of the PMOS transistor 411 is set so as to have a sufficiently higher impedance than other transistors. In this case, the PMOS transistor 411
Operates as a pull-up resistor.

Here, the control signals 20, 21 and 22
Are controlled so that they are all at low level or only at high level. That is, 3-state gate 1
The outputs of 0, 11 and 12 are all controlled to be in a high impedance state or any one of them is in an output state. When only one of the 3-state gates 10, 11 and 12 is in the output state, the signal output from the 3-state gate in that output state is the internal bus 6
It is input to the buffer gates 50 and 51 via 0. When the output of the 3-state gate in the output state is at the high level, there is no potential difference between the pull-up resistor formed by the PMOS transistor 411 and the internal bus 60, and the internal bus 60 is at the high level and the PMOS transistor 411 There is no current flowing through. When the output of the 3-state gater, which is the only output state, is low level, PMO
A potential difference occurs between the pull-up resistor formed by the S transistor 411 and the internal bus 60, and a current flows through the PMOS transistor 411.
Since the on-resistance of 11 is set to a sufficiently higher impedance than other transistors, the internal bus 60 stabilizes at a low level.

3-state gates 10, 11 and 12
When all outputs are in high impedance state,
The transistor 411 charges the internal bus 60 to a high level. After the PMOS transistor 411 charges the internal bus 60 to the high level,
Is stable at a high level, and no current flows through the PMOS transistor 411. It should be noted that only the input circuit in FIG. 1 shown in the above example is omitted and shown in FIG.

[0005]

In the above-described conventional semiconductor integrated circuit device, a plurality of three connected to the internal bus 60 are provided.
-When any one of the state gates 10, 11 and 12 is in the output state and its output level is low level, a current flows through the PMOS transistor which operates as a pull-up resistor. There is a drawback that the power consumption for that is large.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a semiconductor integrated circuit device with reduced power consumption.

[0007]

According to the structure of the present invention, in a semiconductor integrated circuit device having an internal bus in which each output of a plurality of first 3-state gates is connected to one signal line, A latch circuit connected to the internal bus and having an output connected to the internal bus, and a detection circuit for detecting that all of the first 3-state gates are in a high impedance state are provided, and the latch circuit is provided. Is provided with a second 3-state gate controlled by the output signal of the detection circuit.

[0008]

1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, a signal of an internal bus 60 is input to buffer gates 50 and 51 and an inverter 31, and an output of the inverter 31 is output. Is the PMOS transistor 4
11 and 412 are connected in cascade, and NMOS transistors 421 and 422 are connected in cascade. The gates of the PMOS transistor 412 and the NMOS transistor 421 of the clocked inverter 40 are input, and the output of the clocked inverter 40 is input to the internal bus 60. Is output. The outputs of the 3-state gates 10, 11 and 12 whose output states are controlled by the control signals 20, 21 and 22 are output to the internal bus 60. Further, the control signals 20, 21 and 22 are applied to the NOR gate 7
0, its output is input to the NMOS transistor 422 and the inverter 30 in the clocked inverter 40, and the output of the inverter 30 is input to the PMOS transistor 411 of the clocked inverter 40.

Here, the control signals 20, 21 and 22 are
All of them are controlled to be low level or only high level, that is, 3-state gates 10 and 11
The outputs of 12 and 12 are all controlled to be in a high impedance state or any one of them is in an output state. Further, the NOR gate 70 is a 3-state gate 10, 1.
When it is detected that all 1 and 12 are in the high impedance state, they become high level. Clocked inverter 40
Is controlled by the NOR gate 70 and the inverter 30, and when the NOR gate 70 is at the high level and the inverter 30 is at the low level, that is, when the 3-state gates 10, 11 and 12 are all in the high impedance state, The inverter 40 is in the output state and 3
-When only one of the state gates 10, 11 and 12 is in the output state, it is in the high impedance state. That is, the clocked inverter 40 functions as a second 3-state gate.

When the control signal 20 is only at the high level and the control signals 21 and 22 are at the low level, the 3-state gate 10 outputs a signal to the internal bus 60, the 3-state gates 11 and 12 and the clocked inverter. 40
Is in a high impedance state. The signal output from the 3-state gate 10 is input to the inverter 31 via the internal bus 60, the signal is inverted and input to the clocked inverter 40, but the signal is blocked by the clocked inverter 40. It Therefore, the signal output from the 3-state gater 10 is input to the buffer gates 50 and 51.

Next, the control signal 20 becomes low level,
When the 3-state gate 10 is in the high impedance state, the clocked inverter 40 is in the output state and the output of the inverter 31 is inverted and output to the internal bus 60. At this time, the inverter 31 and the clocked inverter 40 have a function of a latch and hold signals to prevent the internal bus 60 from floating. Therefore, stable signals are input to the buffer gates 50 and 51.

Next, when only one of the control signals 20, 21 and 22 becomes high level, the corresponding 3-state gate becomes the output state and the clocked inverter 40 becomes the high impedance state. No signal collision occurs on the internal bus 60, the signal of the corresponding 3-state gate is output, and stable signals are input to the buffer gates 50 and 51.

Further, if any one of the control signals 20, 21 and 22 is at a high level, the corresponding 3-
When the state gate is in the output state and the signal is being output to the internal bus 60 and the signal of the corresponding 3-state gate changes from low level to high level or from high level to low relevance, the clocked inverter 40 has high impedance. In this state, no collision of signals occurs on the internal bus 60, and stable signals are input to the buffer gates 50 and 51.

[0014]

As described above, the present invention does not require the PMOS transistor for the pull-up resistor as in the conventional example, and therefore the PMOS for the pull-up resistor is required.
No current flows through the transistor, and since there is no steady-state current path in any state, power consumption can be reduced.

Now, when the inherence of the pull-up resistor formed by the conventional PMOS transistor is 50 KΩ and the power supply voltage is 5 V, the current and the power consumption which constantly flow in the state where the circuit is not operating are calculated. To do.

Current: 5 (V) / 50 (KΩ) = 100 (μA) Power consumption: 100 (μA) × 5 (V) = 500 (μW) Thus, in the conventional example, consumption of 500 (μW) In the present invention, it is substantially 0 (μW) with respect to electric power.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit added to a conventional internal bus.

[Explanation of symbols]

 10, 11, 12 3-state gate 20, 21, 22 Control signal 30, 31 Inverter 40 Clocked inverter 411, 412, 413 PMOS transistor 421, 422, 423 NMOS transistor 50, 51 Buffer gate 60 Internal bus 70 NOR gate

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising an internal bus in which each output of a plurality of first 3-state gates is connected to one signal line, wherein an input is connected to said internal bus and an output is said A latch circuit connected to the internal bus and a detection circuit for detecting that all of the first 3-state gates are in a high impedance state are provided, and the latch circuit is controlled by the output signal of the detection circuit. A semiconductor integrated circuit device comprising a second 3-state gate according to claim 1.