JPS63114319A - Output circuit - Google Patents

Abstract

PURPOSE:To revise the output form through the designation of a control signal by controlling a P-channel MOSFET and an N-channel MOSFET by a control circuit comprising a 2-input NAND gate and an inverter. CONSTITUTION:With a control signal 102 at An H level, an input signal 101 is outputted in push-pull form at an output terminal 107. With the control signal 102 at an L level, the input signal 101 is outputted in an N-channel open drain form at the output terminal 107. Since either the push-pull or one channel open drain output is supplied by the designation of the control signal, in using a microcomputer built in the output circuit, the output form most suited to the peripheral circuit constitution and its circuit state is set easily and the peripheral circuit of the microcomputer is simplified and the number of components is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits, and particularly to improvements in the configuration of output circuits built into microcomputers.

2. Description of the Related Art Conventionally, output circuits built into microcomputers include push-pull type and single channel open drain type. Below, such a conventional output circuit will be explained with reference to the drawings. FIG. 3 shows a configuration example of a push-pull type output circuit.

The output circuit in FIG. 3 includes a high potential power supply 308 and a low potential power supply 3.
09 between P channel MOS type F E TaO2 and N
A channel MOS type FET 306 is connected in series, and an output terminal 307 is connected between the P channel and N channel MOS type FET. Such an output circuit receives an input signal 301 and a control signal 302, and the inputs are:
2-input NOR gate 304. 2-input NOR gate 304
, each MOS type FET passes through the inverter 312.
305 and 306 and output from an output terminal 307.

In the output circuit configured as above, first, the control signal 3
The case where 02 is at a high level (hereinafter abbreviated as "H") will be explained.

At this time, if the input signal 301 is "H", the NAND gate 303 outputs a low level (hereinafter abbreviated as "L"), and the P-channel MOS type FET 305 becomes conductive. Furthermore, the NOR gate 304 outputs 'L', thereby rendering the N-channel MOS FET 3Q5 non-conductive. Therefore, the output terminal 307 is connected only to the high potential power supply 308 through the P-channel MOS FET, and the input The same "H" as signal 3 old is output from output terminal 307.

Also, if the input signal 3 old is “L”, the NΔAND gate 30
3 is a P-channel MOS type F by outputting “H”.
ET305 becomes non-conductive. Also, NOR gate 3
04 outputs “H” and N-channel MOS type FET306
becomes conductive. Therefore, the output terminal 307c is connected only to the low potential power supply 309 through the N-channel MoS type FET 306, and the same "L" as the input signal 301 is output to the output terminal 307.
7 are output.

Next, the case where the control signal 302 is the force PL'' will be explained.

N A N D K) 303 C, input signal 301 is “
304 is the input signal 301
By outputting "L" when is "Ho" or "L", N-channel MOS type FET 3Q5 also becomes non-conductive. Therefore, the output terminal 307 is not connected to either the high potential power source 308 or the low potential power source 309 and is in a "floating" state, with no output signal.

The truth table of the output circuit shown in FIG. 3 is shown in Table 1.

According to Table 1, this output circuit outputs an output signal from the output terminal 307 only when the control signal 302 is "H".

That is, it can be said that the output terminal 307 of this output circuit is fixed in a push-pull type.

Problems to be Solved by the Invention However, the optimal circuit format for the output terminal in a microcomputer varies depending on the peripheral circuit configuration and circuit state when the microcomputer is used.

Therefore, conventionally, the type of output circuit in a microcomputer has been considered and determined to be suitable for the most uses.

However, in the past, the circuit type was fixed, so it was impossible to make it optimal for all uses.

This not only necessitates extra parts and circuitry around the microcomputer when it is used, but also has the drawback of narrowing the uses of the microcomputer in the worst case.

Therefore, the present invention solves these drawbacks and provides push-pull type output and single channel open drain in order to be adaptable to various uses such as peripheral circuit configurations and circuit conditions when using a microcomputer. The present invention aims to provide an output circuit configuration capable of outputting in any format.

Means for solving the problem, ie, according to the present invention, first and second MOS type FETs are connected in series between a first potential and a second potential,
An output terminal is connected between the first and second MOS FETs, and in an output circuit of a semiconductor integrated circuit that receives a control signal and an input signal, when the control signal is at a first control level, , if the input signal is at a first input level, the first MOS FET is made conductive; if the input signal is at a second input level, the first MOS FET is made conductive;
said first MOS type FE to make the type FET non-conductive.
generates a gate signal at T, and when the control signal is at a second control level, the first MOS type FET is made non-conductive regardless of the input signal. a first control means for generating a gate signal to the FET; and second control means for generating a gate signal to the MOS FET.

According to the output circuit of the present invention, when the control signal is at the first control level, the output circuit is in a push-nible type output state, and when it is at the second control level, the output circuit is in one channel open state. It becomes a drain type output state.

That is, the output type can be changed by specifying the control signal.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of an output circuit according to the present invention.

The output circuit in FIG. 1 includes a high potential power supply 108 and a low potential power supply 1.
09, a P-channel MOS type FET 105 and an N-channel MOS type FET 106 are connected in series, and an output terminal 107 is connected between the P-channel and N-channel MOS type FET. Such an output circuit receives input signal 1
01 and a control signal 102 as inputs, and the inputs are input to respective MOS type FETs 105 and 106 through a first control means 110 consisting of a two-input NAND gate 103 and a second control means 111 consisting of an inverter 104. The signal is configured to be output from an output terminal 107.

In the output circuit having such a configuration, first, the control signal 102"
The case where it is "H" will be explained.

At this time, if the input signal 101 is 11811, the NAN
When the D gate 103 outputs "L", the P channel MOS type FET 105 becomes conductive. Further, the inverter 104 outputs "L", so that the N-channel transistor 106 becomes non-conductive. Therefore, the output terminal 107 is connected to the P-channel MOS FET 105.
is connected only to the high potential power supply 108 through the input signal 10
“H”, which is the same as 1, is output from the output terminal 107.

Furthermore, if the input signal 101 is "L", the NAND gate 103 outputs "H", so that the P-channel MOS type FET 105 becomes non-conductive, but the inverter 104
By outputting H power, N-channel MOS type FE
T106 becomes conductive.

Therefore, the output terminal 107 is an N-channel MO5 type FET1.
It is connected only to the low potential power supply 109 through 06, and the same "L" as the input signal 101 is output from the output terminal 107.

That is, when the control signal 102 is "H'", the input signal 1
01 is output to the output terminal 107 in a push-pull format.

Next, a case where the control signal 102 is "L" will be explained.

At this time, the NAND gate 103 inputs the input signal 101 “
By outputting “H” at both “H” and “L”,
P-channel MOS type FET 105 is always in a non-conductive state. Here, when the input signal 101 is "H", the impark 104 outputs "L", so that the N channel "M"
The OS type FET 106 also becomes non-conductive. Therefore, the output terminal 107 is not connected to either the high potential power source or the low potential power source, and is in a "floating" state. Also, input signal 1
When 01 is "L", the inverter 104 outputs "H", which makes the N-channel MOS type FET 106 conductive, and the output terminal 107 becomes the N-channel MOS type FET1.
It is connected only to the low potential power supply 109 through 06, and the same "L" as the input signal 101 is output from the output terminal 107.

That is, when the control signal 102 is "L", the input signal 101 is outputted to the output terminal 107 in an N-channel open-drain format.

The truth table of the output circuit shown in FIG. 1 is shown in Table 2.

As explained above in Table 2, the output circuit according to this embodiment can be used as either the push-nable format or the N-channel open drain format by specifying the control signal 102.

Figure 2 is also an embodiment of the present invention, and its truth table is shown in Figure 3.
Shown in the table.

The output circuit of Table 3 and FIG. 2 has a NOR gate 204 in the first control means 210 and an inverter 203 in the second control means 211.
are using. The other configurations are basically the same as the output circuit shown in FIG. 1, so instead of the reference numbers in the 100s, reference numbers in the 200s with the same last two digits are given, and the explanation thereof will be omitted. The first control means 210 has N channels M
In the OS type F E T2O6, the second control means 211 is
Since it is connected to the channel MOS type FET 205, as shown in Table 3, when the control signal 202 is "H", the input signal 201 is outputted to the output terminal 207 in P channel oven drain format, and the control signal 202 When is “L”, input signal 201 is output to output terminal 207 in push-pull format.
Output to.

FIG. 4 shows an embodiment in which an input circuit is added by connecting an input buffer 413 to the output terminal 407. Other than this point, the configuration is basically the same as the output circuit in Figure 1, so instead of the reference number in the 100s, we have given the same reference number in the 400s with the same last two digits. The explanation will be omitted. This embodiment shows that the present invention can also be used as an output circuit portion of an input/output circuit.

Effects of the Invention As is clear from the above explanation, the output circuit according to the present invention has the following effects:
Depending on the designation of the control signal, it is possible to output in either a push-pull format or a single channel open drain format. Therefore, when using a microcomputer with a built-in output circuit, it is possible to easily set the most suitable output format for the peripheral circuit configuration and its circuit state, simplifying the peripheral circuitry of the microcomputer and reducing the number of components. This will in turn lead to expanding the uses of microcomputers.

Furthermore, according to the output circuit according to the present invention, even if we focus only on the fact that it is a push-pull type output circuit that can be set to a floating state, the output circuit shown in FIGS. 1 and 2 is better than the conventional output circuit shown in FIG. It is also possible to reduce the number of constituent circuits as in the embodiment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an output circuit embodying the present invention, which enables N-channel open drain type output. FIG. 2 is a block diagram showing another embodiment of an output circuit embodying the present invention, which enables P-channel open-drain type output. FIG. 3 shows a configuration example of a conventional output circuit, which is a push-pull type output circuit that can be set to a floating state. FIG. 4 is a block diagram of the embodiment of the output circuit shown in FIG. 1 with an input circuit added thereto. (Main reference numbers) 101.201.401...Input signal, 102, 302
．． 402...control signal, 103, 303.403...2
Input NAND gates, 104, 203.312. 40
4...Inverter, 105, 205.305.40
5...P-channel MOS type FET. 106, 206.306.406...N channel M
OS type FET. 107, 207.307...output terminal, 108, 208
．． 308.408 ...°High potential power supply, 109, 20
9.309.409 ・Low potential power supply, 110, 21
0.410...first control means, 111, 211.41
1... Second control means, 204, 304... 2-input NOR gate, 407... Input/output terminal, 413... Input buffer Patent applicant NEC Corporation Figure 2

Claims (1)

[Claims] First and second MOS transistors are connected between the first potential and the second potential.
In an output circuit of a semiconductor integrated circuit, MOS type field effect transistors are connected in series, an output terminal is connected between the first and second MOS type field effect transistors, and a control signal and an input signal are input. , when the control signal is at a first control level, if the input signal is at the first input level, the first MOS field effect transistor is made conductive, and the input signal is at the second input level.
If the input level is at a second control level, a gate signal is output to the first MOS field effect transistor to make the first MOS field effect transistor non-conductive, and when the control signal is at a second control level, , a first control means for outputting a gate signal to the first MOS field effect transistor in order to make the first MOS field effect transistor non-conductive regardless of the input signal; a second input signal, and outputs a gate signal to the second MOS field effect transistor to make the second MOS field effect transistor non-conductive if the input signal is at a first input level; An output circuit comprising a control means.