JPH04150315A - Cmos logic circuit - Google Patents

Abstract

PURPOSE:To reduce a logic threshold voltage due to the number of inputs by connecting a series connection circuit in series with the parallel connection circuit of two series circuits each composed of two each MOS transistors(TRs). CONSTITUTION:When the levels of inputs A, B are '1', '0' or '1', '1', N- channel MOS TRs N1, N2 are turned on, the level '0' is fed to a terminal 101 and an N-channel MOS TR 3 is turned off. Thus, a voltage at an output terminal 102 is decided to be '0' by the TRs N1, N2. When the levels of the inputs A, B are '0', '0', P-channel MOS TRs P1, P2 are turned on, N-channel MOS TRs N1, N2, N4 are turned off and the level of the terminal 102 is decided to be '1' by the TRs P1, P2. By such constitution, the fluctuation of the threshold level is minimized by adjusting the driving capability when the N1, N2 and N3, N4 are conductive.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to CMOS logic circuits.

[Conventional technology]

A conventional CMO8''C'' logic circuit is constructed by connecting a P-channel transistor and an N-channel transistor in parallel or series.

FIG. 3 is a circuit diagram of an example of such a conventional two-person NOR circuit. In FIG. 3, this two-manpower (A, B) NOR circuit is composed of series-connected P-channel transistors PL, P2 and parallel-connected N-channel transistors Nl, N2, and has two inputs A, The logical sum (NOR) of B is output.

[Problem to be solved by the invention]

In the conventional logic circuit described above, the logic threshold voltage when input A changes, the logic threshold voltage when input B changes,
Furthermore, the logic threshold voltages when the two inputs A and B both change are different.

There is a large variation in the logic threshold voltage between the one-manpower case and the two-manpower case, and there is a drawback that the noise margin is reduced, especially in the case of a multi-input logic circuit.

As a means to solve the above problem, as shown in Fig. 4 (Japanese Patent Publication No. 62-274925), a current limiting circuit (here, a resistor R) is connected in series with a group of transistors connected in parallel. There is a configuration that reduces fluctuations in the logic threshold voltage, but this current limiting circuit tends to slow down changes in the output voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS logic circuit which solves the above-mentioned drawbacks, reduces fluctuations in the logic threshold voltage due to changes in the number of inputs, and does not change the change time of the output voltage.

[Means to solve the problem]

The configuration of the CMOS logic circuit of the present invention is as follows. second MO
A series body of S transistors and a third. a parallel connection body with a fourth series body of MOS transistors; and a fifth MOS transistor. The fifth MOS transistor is connected in series with the series body of the sixth MOS transistor. The gates of the sixth MOS transistors are connected to the gates of the first and second MOS transistors, respectively. the second input, the parallel connection body and the fifth input; It is characterized in that the connection point with the series body of the sixth MOS transistor is used as an output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In FIG. 1, the first embodiment has a two-manpower NOR circuit configuration.

That is, a P-channel MO to which inputs A and B are respectively applied.
Three transistors PI, P2 and N channel MOS transistors Nl, N2 . N3. It has a terminal N4, a terminal 101, and an output terminal 102.

In the CMOS logic circuit of this embodiment, the source is the first power supply,
a first P-channel MO3 transistor having a gate connected to a first input, a drain connected to a first output, a source connected to a first output, a gate connected to a second input, and a drain connected to a second output; a second P-channel MO3 transistor;
a second N-channel MOS transistor having a source connected to a second power supply, a gate connected to a first input, and a drain connected to a first output; a source connected to a first output; and a gate connected to a first input;
a first N-channel M whose drain is connected to the second output;
an OS transistor, a fourth N-channel MOS transistor whose source is connected to a second power supply, whose gate is connected to a second input, whose drain is connected to one terminal; whose source is connected to the one terminal, whose gate is connected to the first output; and a third N-channel MOS transistor connected to the second output.

Next, the operation of this embodiment will be explained.

When inputs A, B are applied to 1.0, N-channel MO
S transistors Nl and N2 become conductive (ON),
Terminal 101 is applied to O, and N-channel MOSN3 becomes non-conductive (OF'F). Therefore, output terminal 10
2 voltage is the voltage of N channel MOS transistors Nl, N2.
It is determined to be 0 by

When inputs A and B are applied to 1 and 1, the voltage at output terminal 102 is , N-channel MOS transistor Nl.

It is determined to be 0 by N2.

Inputs A and B are 0. If applied to O, the P channel M
O3 transistors Pi and P2 are conductive, N channel M
The OS transistors Nl, N2゜N4 become non-conductive, and the output terminal 102 becomes the P-channel MO3 transistor Pi.
, P2, it is determined to be 1.

From the above results, it can be seen that the variation in the logic threshold value is
) - transistor N1. ．． N2. and N3. By adjusting the drive capability when conducting with N4, it is possible to minimize this.

FIG. 2 is a circuit diagram of a second embodiment of the invention. In FIG. 2, the second embodiment has a two-manpower NAND circuit configuration. That is, N-channel MOS transistors N1. to which inputs A and B are respectively applied. N2 and P channel MO
3 transistors P1, P2. P3. P4 and output terminal 2
02.

In the above embodiment, a two-man powered NOR circuit and a two-man powered NAND circuit have been described, but the number of inputs is three.
Even in the above case, the present invention is similarly applicable. Further, the present invention can be applied to logic circuits other than NOR circuits and NAND circuits.

〔Effect of the invention〕

As explained above, the present invention uses input signal A.

This has the effect of suppressing fluctuations in the logic threshold due to the number of input signals to a low level, compared to the prior art where the logic threshold varied greatly due to B.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a CMOS logic circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a CMOS logic circuit according to a second embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing an example of a human-powered NOR circuit, and is a circuit diagram for suppressing fluctuations in the logic threshold value of a conventional two-human powered NOR circuit. PL, P2. P3. P4...P channel MOS transistor, Nl, N2. N3. N4...N channel MO
S transistor, R...resistance.

Claims (1)

[Claims] A series body of first and second MOS transistors and a third and fourth MOS transistor.
A parallel connection body with a series body of MOS transistors, and a fifth
, connected in series with a sixth series body of MOS transistors,
The gates of the fifth and sixth MOS transistors are used as first and second inputs, respectively, and the parallel connection body and the fifth
, a CMOS logic circuit characterized in that a connection point with a sixth series MOS transistor is used as an output.